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Re: Processor ISAs

From Herbert Kleebauer <klee@unibwm.de>
Newsgroups alt.os.development
Subject Re: Processor ISAs
Date 2016-03-25 12:43 +0100
Organization Aioe.org NNTP Server
Message-ID <nd38bg$7su$1@gioia.aioe.org> (permalink)
References <nd19lt$3h5$1@dont-email.me> <nd2p2s$1eii$1@gioia.aioe.org>

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On 25.03.2016 08:24, wolfgang kern wrote:

> 2650 had the smallest instructions set I found on 8-bit MCUs. 

Here a 16 bit CPU implemented with 65 FlipFlops and about 250 gates.
It has only 3 instructions and no register set:


1.2 Register
To minimize the hardware, there is only a 15 bit program counter (PC) and a 1 bit flag (F). No
other user accessible registers exist. After a reset PC and F are initialized to 0.


1.3 Instructions
MPROZ supports three instructions:

br	adr
+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
|1|         adr                 |  Load adr into PC if F=0
+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+  Clear F


add	adr1,adr2
+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
|0|         adr 1               | Add the contents of memory location adr1 and the contents of
+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ memory location adr2 and store the result in memory location adr2.
|0|         adr 2               | Store the carry of the addition in F.
+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+


nor	adr1,adr2
+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
|0|         adr 1               | Calculate the NOR function of the contents of memory location adr1
+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ and the contents of memory location adr2 and store the result in
|1|         adr 2               | memory location adr2. F=1 if result =0 , else F=0.
+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+


1.4 Interrupt
Because there is no instruction to set or reset the interrupt enable flag (ie), this is done by accessing
memory location $4000. A read from $4000 enables interrupts (ie=1) and a write to $4000 disables
interrupts (ie=0). An external interrupt request (IRQ~) must be asserted until the interrupt is
serviced by MPROZ. The interrupt is serviced by MPROZ, when the interrupt enable flag is set and
a branch instruction with F=0 is executed. Thereby it is not necessary to save the program counter
(PC) and the flag (F), but it is sufficient to save the interrupted branch instruction. This instruction
is saved at the memory location which address is stored in memory location 1 (this normally should
be address $4000, because then the ie flag is automatically cleared, when the instruction is saved).
The execution of the interrupt program starts at address 2. The return from interrupt is done by a
branch to $4000, which also automatically sets the ie flag.

http://www.bitlib.de/pub/mproz/mproz_e.pdf

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Processor ISAs "Bill Cunningham" <billcun-remove-@suddenlink.net> - 2016-03-24 13:58 -0500
  Re: Processor ISAs "Alexei A. Frounze" <alexfrunews@gmail.com> - 2016-03-24 13:50 -0700
    Re: Processor ISAs "Bill Cunningham" <billcun-remove-@suddenlink.net> - 2016-03-24 17:31 -0500
  Re: Processor ISAs Rod Pemberton <NoHaveNotOne@bcczxcfre.cmm> - 2016-03-24 19:17 -0400
  Re: Processor ISAs "Benjamin David Lunt" <zfysz@fysnet.net> - 2016-03-24 17:50 -0700
    Re: Processor ISAs "Bill Cunningham" <billcun-remove-@suddenlink.net> - 2016-03-25 13:21 -0500
  Re: Processor ISAs "wolfgang kern" <nowhere@never.at> - 2016-03-25 08:24 +0100
    Re: Processor ISAs Herbert Kleebauer <klee@unibwm.de> - 2016-03-25 12:43 +0100
  Re: Processor ISAs Lucretia <laguest9000@googlemail.com> - 2016-03-28 06:45 -0700
    Re: Processor ISAs Lucretia <laguest9000@googlemail.com> - 2016-03-28 06:54 -0700
      Re: Processor ISAs "wolfgang kern" <nowhere@never.at> - 2016-03-28 22:40 +0200
        Re: Processor ISAs Lucretia <laguest9000@googlemail.com> - 2016-03-29 13:00 -0700
          Re: Processor ISAs "wolfgang kern" <nowhere@never.at> - 2016-03-30 11:17 +0200
      Re: Processor ISAs James Harris <james.harris.1@gmail.com> - 2016-04-01 10:15 +0100
        Re: Processor ISAs "wolfgang kern" <nowhere@never.at> - 2016-04-01 13:16 +0200
          Re: Processor ISAs James Harris <james.harris.1@gmail.com> - 2016-04-01 22:48 +0100
            OT: processor binary- or pin-compatibility, was [Re: Processor ISAs] Rod Pemberton <NoHaveNotOne@bcczxcfre.cmm> - 2016-04-01 21:22 -0400
              Re: OT: processor binary- or pin-compatibility, was [Re: Processor ISAs] Rod Pemberton <NoHaveNotOne@bcczxcfre.cmm> - 2016-04-01 21:26 -0400
              Re: OT: processor binary- or pin-compatibility, was [Re: Processor ISAs] Bob Eager <news0006@eager.cx> - 2016-04-02 08:46 +0000
                Re: OT: processor binary- or pin-compatibility, was [Re: Processor Bogus@Embarq.com (Steve) - 2016-04-03 12:31 +0000
                Re: OT: processor binary- or pin-compatibility, was [Re: Processor Morten Reistad <first@last.name.invalid> - 2016-04-03 14:44 +0200
                Re: OT: processor binary- or pin-compatibility, was [Re: Processor Bob Eager <news0006@eager.cx> - 2016-04-03 18:53 +0000
                Re: OT: processor binary- or pin-compatibility, was [Re: Processor Bogus@Embarq.com (Steve) - 2016-04-03 20:07 +0000
                Re: OT: processor binary- or pin-compatibility, was [Re: Processor Bob Eager <news0006@eager.cx> - 2016-04-03 21:18 +0000
                Re: OT: processor binary- or pin-compatibility, was [Re: Processor "J. Clarke" <j.clarke.873638@gmail.com> - 2016-04-03 20:20 -0400
                Re: OT: processor binary- or pin-compatibility, was [Re: Processor "J. Clarke" <j.clarke.873638@gmail.com> - 2016-04-03 20:17 -0400
                Re: OT: processor binary- or pin-compatibility, was [Re: Processor pechter@pechter.dyndns.org (William Pechter) - 2016-04-04 15:53 +0000
              Re: processor binary- or pin-compatibility, was [Re: Processor ISAs] "Charles Richmond" <numerist@aquaporin4.com> - 2016-04-04 17:24 -0500
                Re: processor binary- or pin-compatibility, was [Re: Processor ISAs] Bob Eager <news0006@eager.cx> - 2016-04-04 23:08 +0000
                Re: processor binary- or pin-compatibility, was [Re: Processor ISAs] Bogus@Embarq.com (Steve) - 2016-04-05 17:43 +0000
                Re: processor binary- or pin-compatibility, was [Re: Processor ISAs] Ahem A Rivet's Shot <steveo@eircom.net> - 2016-04-05 19:15 +0100
            Re: Processor ISAs "wolfgang kern" <nowhere@never.at> - 2016-04-02 10:59 +0200

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