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Groups > comp.arch > #2207

Re: Memory Transactions per Second.

From Robert Redelmeier <redelm@ev1.net.invalid>
Newsgroups alt.comp.hardware.pc-homebuilt, alt.lang.asm, comp.arch
Subject Re: Memory Transactions per Second.
Date 2011-06-15 02:49 +0000
Organization Aioe.org NNTP Server
Message-ID <it96ir$kfq$3@speranza.aioe.org> (permalink)
References <bb5c3$4df4552b$5419acc3$8855@cache6.tilbu1.nb.home.nl> <8066b340-e3ca-4cc5-a602-03a8b26560b9@j9g2000vbs.googlegroups.com> <17bbc$4df532a6$5419acc3$25813@cache4.tilbu1.nb.home.nl> <it3tsk$vg6$2@speranza.aioe.org> <d0df5$4df6239c$5419acc3$30038@cache5.tilbu1.nb.home.nl>

Cross-posted to 3 groups.

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In alt.lang.asm Skybuck Flying <Windows7IsOK@dreampc2006.com> wrote in part:
> LOL, Next time I will ask the webstore if they wanna
> run a program like that.

Why not?  All they need to do under Linux is make the systems
visible via ssh and give you guest login.

> Ofcourse there is a problem with your reasoning if it's a
> new system I might not yet know how to program it.

It'd better have a C compiler somewhere.  Then you
could run my code.

> " /* lat10m.c - Measure latency of 10 million fresh memory
> reads "
>
> Only 10 million ? I think my AMD x2 3800+ dual core can
> easily do 180 million per core per second.

Maybe in-order.  The quad Athlon/DDR3  I tested could
only do 12 million pseudo-random.  I could try it multicore.


> So your test is already flawed.
> Doesn't that scare you a bit ? ;)

Not in the least.  I know it's flawed.  Going to 100m
iterations is an easy change.


> I'd rather have the manufacturer figure it out... if they
> can't figure it out then who can ? ;)

No-one -- memory performance will depend on the DRAM
used (timings).  Which the CPU mfr doesn't control.

> Also another potential problem is with running out of memory.
>
> Suppose the processor is 1 Terrahertz and the memory is only 10
> gigabytes then one can't simply generate a "unique" table and
> pointer-chase-walk it.
>
> There is a chance that some of the memory addresses will be cached
> and the more transactions happen the more chance it gets cached.

Not really -- if I have 10 GB RAM and 10 MB cache, the
chances a random location will be in cache is 0.001 .

-- Robert

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Thread

Memory Transactions per Second. "Skybuck Flying" <Windows7IsOK@DreamPC2006.com> - 2011-06-12 07:57 +0200
  Re: Memory Transactions per Second. MitchAlsup <MitchAlsup@aol.com> - 2011-06-12 08:59 -0700
    Re: Memory Transactions per Second. "Skybuck Flying" <Windows7IsOK@DreamPC2006.com> - 2011-06-12 23:42 +0200
      Re: Memory Transactions per Second. Robert Redelmeier <redelm@ev1.net.invalid> - 2011-06-13 02:49 +0000
        Re: Memory Transactions per Second. "Skybuck Flying" <Windows7IsOK@DreamPC2006.com> - 2011-06-13 16:50 +0200
          Re: Memory Transactions per Second. Robert Redelmeier <redelm@ev1.net.invalid> - 2011-06-15 02:49 +0000
            Re: Memory Transactions per Second. "Skybuck Flying" <Windows7IsOK@DreamPC2006.com> - 2011-06-15 06:55 +0200
  Re: Memory Transactions per Second. "Andy \"Krazy\" Glew" <andy@SPAM.comp-arch.net> - 2011-06-12 12:51 -0700
    Re: Memory Transactions per Second. MitchAlsup <MitchAlsup@aol.com> - 2011-06-12 14:40 -0700
    Re: Memory Transactions per Second. Jason Riedy <jason@lovesgoodfood.com> - 2011-06-13 09:33 -0400
  Re: Memory Transactions per Second. mr computer <microbrainz@gmail.com> - 2011-06-12 16:06 -0700
    Re: Memory Transactions per Second. "Skybuck Flying" <Windows7IsOK@DreamPC2006.com> - 2011-06-13 16:29 +0200
      Re: Memory Transactions per Second. mr computer <microbrainz@gmail.com> - 2011-06-13 07:54 -0700
        Re: Memory Transactions per Second. "Skybuck Flying" <Windows7IsOK@DreamPC2006.com> - 2011-06-13 17:08 +0200
          Re: Memory Transactions per Second. MitchAlsup <MitchAlsup@aol.com> - 2011-06-13 11:50 -0700
            Re: Memory Transactions per Second. "Skybuck Flying" <Windows7IsOK@DreamPC2006.com> - 2011-06-14 04:07 +0200

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