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Re: Forth in VHDL

Cross-posted to 2 groups.

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On Tue, 26 Jul 2016 16:00:23 GMT
anton@mips.complang.tuwien.ac.at (Anton Ertl) wrote:

> AFAIK the GA144 is not an asynchronous design; it's a clocked
> design, but the clock is generated internally (one clock per
> core).  At least an earlier chip by Chuck Moore worked that
> way (IIRC the MuP21), and the idea that this was an async
> design was already rampant (and contradicted) at the time.

Yes, both Green Arrays and IntellaSys chips [1][2] need 'nop' or
another instruction that does not alter T or S to precede an
addition. This is in order to allow the carry to stabilise. The
earlier manual states that the carry propagates nine bits in
each processor cycle. 

The GA144 is asynchronous at the boundary of each processor
module.  AFAICTell this is a common 'asynchronous' design method.
Otherwise the wikkipedia article [3] "Asynchronous CPU" needs
revision.  There are perhaps zero recent CPU designs built of
purely asynchronous logic?  (And, for good patent readers, what
are Achronix async FPGA parts made of)

The most efficient asynchronous signalling method for random
logic seems to be "four state encoding". This uses two wires to
carry a single bit and a 'time stamp'. The 'time stamp' is the
data cycle to which the data bit belongs, mod 2. 

The encoding is arranged so that in the transition to each new
time phase only one of the two wires changes state, regardless
of whether or not the data has changed.  This avoids race
problems between the two wires. 

I'd like to know what the cost for this is in transistors,
having guessed it is about 10 _times_ more than simple
conventional logic.

Jan Coombs
-- 
[1] DB001-110412-F18A.pdf "F18A Technology Reference" pg8
[2] "SEAforth 40C18 Data Sheet (Preliminary)" pg44
[3] https://en.wikipedia.org/wiki/Asynchronous_circuit

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Forth in VHDL rickman <gnuarm@gmail.com> - 2016-07-24 22:29 -0400
  Re: Forth in VHDL rickman <gnuarm@gmail.com> - 2016-07-24 23:01 -0400
    Re: Forth in VHDL rickman <gnuarm@gmail.com> - 2016-07-24 23:05 -0400
      Re: Forth in VHDL Cecil Bayona <cbayona@cbayona.com> - 2016-07-24 22:25 -0500
        Re: Forth in VHDL rickman <gnuarm@gmail.com> - 2016-07-25 00:08 -0400
          Re: Forth in VHDL Cecil Bayona <cbayona@cbayona.com> - 2016-07-24 23:57 -0500
            Re: Forth in VHDL rickman <gnuarm@gmail.com> - 2016-07-25 01:22 -0400
              Re: Forth in VHDL Paul Rubin <no.email@nospam.invalid> - 2016-07-24 22:38 -0700
                Re: Forth in VHDL rickman <gnuarm@gmail.com> - 2016-07-25 01:53 -0400
              Re: Forth in VHDL Cecil Bayona <cbayona@cbayona.com> - 2016-07-25 14:11 -0500
                Re: Forth in VHDL rickman <gnuarm@gmail.com> - 2016-07-25 17:39 -0400
                Re: Forth in VHDL Cecil Bayona <cbayona@cbayona.com> - 2016-07-25 18:01 -0500
                Re: Forth in VHDL rickman <gnuarm@gmail.com> - 2016-07-25 19:40 -0400
                Re: Forth in VHDL Jan Coombs <jenfhaomndgfwutc@murmic.plus.com> - 2016-07-26 11:04 +0100
                Re: Forth in VHDL rickman <gnuarm@gmail.com> - 2016-07-26 11:13 -0400
                Re: Forth in VHDL anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2016-07-26 16:00 +0000
                Re: Forth in VHDL rickman <gnuarm@gmail.com> - 2016-07-26 12:58 -0400
                Re: Forth in VHDL anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2016-07-27 09:39 +0000
                Re: Forth in VHDL rickman <gnuarm@gmail.com> - 2016-07-27 10:01 -0400
                Re: Forth in VHDL Jan Coombs <jenfhaomndgfwutc@murmic.plus.com> - 2016-07-27 22:46 +0100
    Re: Forth in VHDL rickman <gnuarm@gmail.com> - 2016-07-27 18:15 -0400

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