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Re: adding overflow and carry to every GPR (was Re: OT: Epic RISC-V rant)

Cross-posted to 2 groups.

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Kragen Javier Sitaker <kragen@canonical.org> posted:

> John Ames <commodorejohn@gmail.com> writes:
> > On Wed, 02 Sep 2026 02:04:51 GMT
> > MitchAlsup <user5857@newsgrouper.org.invalid> wrote:
> >> For ADD, carry Rd contains only 1 bit, but for others, it contains
> >> “all the bits that did not make it into the standard result”. This
> >> makes CARRY suitable for all integer multiprecision arithmetic and
> >> for significant quantities of FP arithmetic.
> >> [...]
> >> Multi-precisions shifts use carry
> >
> > Yes, exactly - add/subtract set the designated overflow/carry register
> > to 1 on a carry/borrow (which can then be added/subtracted from the next
> > more significant word) but e.g. multiply can set it to the whole most-
> > significant half of the product, multi-place shifts can catch all the
> > bits that fall off one end in the other so that rotate becomes shift-
> > and-OR, etc. Very flexible, especially if you have the capability to
> > branch on the value of a GPR.
> 
> A bit-shift operation with two source registers is sometimes called a
> “funnel shift”, which is sort of the inverse of this:
> <https://www.eevblog.com/forum/programming/funnel-shifter-where-are-useful/>
> <https://stackoverflow.com/questions/12767113/funnel-shift-what-is-it>
> <https://github.com/rust-lang/rust/issues/145686>
> 
> That is, instead of one source register (for a given bit shift size) and
> two destination registers, a funnel shift has two source registers (plus
> the amount to shift) and possibly just one destination register.
> 
> An interesting thing about funnel shifts is that, if both source
> registers are the same, it provides bit rotation, not just shift.
> Conceivably you could get the same result from this inverse funnel
> shift, depending on how you handle the case where the destination
> register is the same as the CARRY register.

Yes, CARRY is how one gets shift double-wide in My 66000. So, when we
added Rotates, we use a length field (rather than a 2^(3+n) specifier)
so, one can rotate a 6-bit field or a 19-bit field in either direction.
 
> Kragen

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OT: Epic RISC-V rant Paul Rubin <no.email@nospam.invalid> - 2026-08-14 22:22 -0700
  Re: OT: Epic RISC-V rant jkn <jkn+nin@nicorp.co.uk> - 2026-08-15 10:10 +0100
  Re: OT: Epic RISC-V rant albert@spenarnc.xs4all.nl - 2026-08-22 18:23 +0200
    Re: OT: Epic RISC-V rant anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2026-08-22 16:45 +0000
  Re: OT: Epic RISC-V rant antispam@fricas.org (Waldek Hebisch) - 2026-08-22 22:36 +0000
    Re: OT: Epic RISC-V rant albert@spenarnc.xs4all.nl - 2026-08-23 13:44 +0200
      Re: OT: Epic RISC-V rant antispam@fricas.org (Waldek Hebisch) - 2026-08-29 19:49 +0000
    Re: OT: Epic RISC-V rant anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2026-08-24 07:55 +0000
      adding overflow and carry to every GPR (was Re: OT: Epic RISC-V rant) Kragen Javier Sitaker <kragen@canonical.org> - 2026-09-01 17:15 -0300
        Re: adding overflow and carry to every GPR (was Re: OT: Epic RISC-V rant) John Ames <commodorejohn@gmail.com> - 2026-09-01 14:31 -0700
          Re: adding overflow and carry to every GPR (was Re: OT: Epic RISC-V rant) BGB <cr88192@gmail.com> - 2026-09-01 17:18 -0500
          Re: adding overflow and carry to every GPR (was Re: OT: Epic RISC-V rant) MitchAlsup <user5857@newsgrouper.org.invalid> - 2026-09-02 02:04 +0000
            Re: adding overflow and carry to every GPR (was Re: OT: Epic RISC-V rant) John Ames <commodorejohn@gmail.com> - 2026-09-02 08:23 -0700
              Re: adding overflow and carry to every GPR (was Re: OT: Epic RISC-V rant) Kragen Javier Sitaker <kragen@canonical.org> - 2026-09-11 13:48 -0300
                Re: adding overflow and carry to every GPR (was Re: OT: Epic RISC-V rant) MitchAlsup <user5857@newsgrouper.org.invalid> - 2026-09-11 18:03 +0000
          Re: adding overflow and carry to every GPR (was Re: OT: Epic RISC-V rant) anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2026-09-09 11:16 +0000
        Re: adding overflow and carry to every GPR (was Re: OT: Epic RISC-V rant) MitchAlsup <user5857@newsgrouper.org.invalid> - 2026-09-02 01:53 +0000
        Re: adding overflow and carry to every GPR (was Re: OT: Epic RISC-V rant) anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2026-09-09 10:50 +0000
          Re: adding overflow and carry to every GPR (was Re: OT: Epic RISC-V rant) Paul Rubin <no.email@nospam.invalid> - 2026-09-09 22:10 -0700
          Re: adding overflow and carry to every GPR (was Re: OT: Epic RISC-V rant) Kragen Javier Sitaker <kragen@canonical.org> - 2026-09-11 14:28 -0300
    Re: OT: Epic RISC-V rant antispam@fricas.org (Waldek Hebisch) - 2026-08-29 20:12 +0000
    interrupt handling latency and weird register use (was Re: OT: Epic RISC-V rant) Kragen Javier Sitaker <kragen@canonical.org> - 2026-09-01 17:00 -0300
      Re: interrupt handling latency and weird register use (was Re: OT: Epic RISC-V rant) anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2026-09-01 20:51 +0000
      Re: interrupt handling latency and weird register use (was Re: OT: Epic RISC-V rant) MitchAlsup <user5857@newsgrouper.org.invalid> - 2026-09-02 01:43 +0000
    interrupt handling latency and weird register use (was Re: OT: Epic RISC-V rant) Andy Valencia <vandys@vsta.org> - 2026-09-02 08:11 -0700

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