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Re: adding overflow and carry to every GPR (was Re: OT: Epic RISC-V rant)

Cross-posted to 2 groups.

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John Ames <commodorejohn@gmail.com> posted:

> On Tue, 01 Sep 2026 17:15:12 -0300
> Kragen Javier Sitaker <kragen@canonical.org> wrote:
> 
> > > RISC-V follows its ancestor MIPS (from where it also has many
> > > mnemonics) in this respect.  For a new way to add the carry
> > > functionality without adding a condition code register, read
> > >
> > > https://www.complang.tuwien.ac.at/anton/tmp/carry.pdf
> > >
> > > (unpublished).  
> > 
> > This is a fascinating idea.  I guess the MuP21 had a carry bit in
> > every “general-purpose register”, making them 21 bits, but I’ve never
> > seen any other architecture do this, nor a version that separates out
> > overflow bits from carry bits.
> > 
> > I also didn’t realize that (base) RISC-V needed 5 instructions *per
> > word* for multi-precision addition.
> 
> Hm, that *is* a bit interesting, though the idea of including non-
> number info in a numeric register drives me a little crazy. (It is,
> admittedly, no weirder than what you already deal with in floating-
> point hardware.)
> 
> The idea I had last time I dabbled with this stuff was to extend the
> basic add/subtract instructions with an option to save the carry/borrow
> value in another GPR, instead - but I never gave any thought to how to
> represent overflow that way. Hmm.

That is what CARRY does. The Rd register in CARRY supplies a register
used to carry the additional values from calculation to calculation.
The Immediate in CARRY selects which instruction consume Rd {i},
which instructions generate the next Rd {o} and which do both {io}
and which do neither {}.

For ADD, carry Rd contains only 1 bit, but for others, it contains
"all the bits that did not make it into the standard result". This
makes CARRY suitable for all integer multiprecision arithmetic and
for significant quantities of FP arithmetic.

Standard integer calculations {ADD, MUL, DIV, SL, SR, ROL, ROR, PERM,
and a few more esoteric ints}

CARRY {o}  IMUL produces a 128-bit result
CARRY {i}  IMUL performs IMAC
CARRY {io} IMUL performs IMAC producing a 128-bit result

Multi-precisions shifts use carry

IEEE 754 augmented FADD and FMUL use CARRY
> 

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OT: Epic RISC-V rant Paul Rubin <no.email@nospam.invalid> - 2026-08-14 22:22 -0700
  Re: OT: Epic RISC-V rant jkn <jkn+nin@nicorp.co.uk> - 2026-08-15 10:10 +0100
  Re: OT: Epic RISC-V rant albert@spenarnc.xs4all.nl - 2026-08-22 18:23 +0200
    Re: OT: Epic RISC-V rant anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2026-08-22 16:45 +0000
  Re: OT: Epic RISC-V rant antispam@fricas.org (Waldek Hebisch) - 2026-08-22 22:36 +0000
    Re: OT: Epic RISC-V rant albert@spenarnc.xs4all.nl - 2026-08-23 13:44 +0200
      Re: OT: Epic RISC-V rant antispam@fricas.org (Waldek Hebisch) - 2026-08-29 19:49 +0000
    Re: OT: Epic RISC-V rant anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2026-08-24 07:55 +0000
      adding overflow and carry to every GPR (was Re: OT: Epic RISC-V rant) Kragen Javier Sitaker <kragen@canonical.org> - 2026-09-01 17:15 -0300
        Re: adding overflow and carry to every GPR (was Re: OT: Epic RISC-V rant) John Ames <commodorejohn@gmail.com> - 2026-09-01 14:31 -0700
          Re: adding overflow and carry to every GPR (was Re: OT: Epic RISC-V rant) BGB <cr88192@gmail.com> - 2026-09-01 17:18 -0500
          Re: adding overflow and carry to every GPR (was Re: OT: Epic RISC-V rant) MitchAlsup <user5857@newsgrouper.org.invalid> - 2026-09-02 02:04 +0000
            Re: adding overflow and carry to every GPR (was Re: OT: Epic RISC-V rant) John Ames <commodorejohn@gmail.com> - 2026-09-02 08:23 -0700
              Re: adding overflow and carry to every GPR (was Re: OT: Epic RISC-V rant) Kragen Javier Sitaker <kragen@canonical.org> - 2026-09-11 13:48 -0300
                Re: adding overflow and carry to every GPR (was Re: OT: Epic RISC-V rant) MitchAlsup <user5857@newsgrouper.org.invalid> - 2026-09-11 18:03 +0000
          Re: adding overflow and carry to every GPR (was Re: OT: Epic RISC-V rant) anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2026-09-09 11:16 +0000
        Re: adding overflow and carry to every GPR (was Re: OT: Epic RISC-V rant) MitchAlsup <user5857@newsgrouper.org.invalid> - 2026-09-02 01:53 +0000
        Re: adding overflow and carry to every GPR (was Re: OT: Epic RISC-V rant) anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2026-09-09 10:50 +0000
          Re: adding overflow and carry to every GPR (was Re: OT: Epic RISC-V rant) Paul Rubin <no.email@nospam.invalid> - 2026-09-09 22:10 -0700
          Re: adding overflow and carry to every GPR (was Re: OT: Epic RISC-V rant) Kragen Javier Sitaker <kragen@canonical.org> - 2026-09-11 14:28 -0300
    Re: OT: Epic RISC-V rant antispam@fricas.org (Waldek Hebisch) - 2026-08-29 20:12 +0000
    interrupt handling latency and weird register use (was Re: OT: Epic RISC-V rant) Kragen Javier Sitaker <kragen@canonical.org> - 2026-09-01 17:00 -0300
      Re: interrupt handling latency and weird register use (was Re: OT: Epic RISC-V rant) anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2026-09-01 20:51 +0000
      Re: interrupt handling latency and weird register use (was Re: OT: Epic RISC-V rant) MitchAlsup <user5857@newsgrouper.org.invalid> - 2026-09-02 01:43 +0000
    interrupt handling latency and weird register use (was Re: OT: Epic RISC-V rant) Andy Valencia <vandys@vsta.org> - 2026-09-02 08:11 -0700

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