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Re: OT: Epic RISC-V rant

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Paul Rubin <no.email@nospam.invalid> wrote:
> https://dmitry.gr/?r=06.%20Thoughts&proj=12.%20RV
> 
> About various flaws in the RISC-V design.  Not since the days of Erik
> Naggum have I seen a rant like this.  Bellissimo.

Some comments.

1) Interrupt latency claim is half-truth.  First, normal RISC-V has
32 registers while ARM has 16.  If you can do with 16 registers
divide register set into 2 parts, use one part for normal code
and the other for interrupt handler.  That way you will get few
cycle overhead, impossible feat for Cortex M.  So it is really
a tradeof, do you want to have modest overhead for pretty
typical use case or do you for very low overhead in cases that
need it and higher overhead for typical cases.

2) What he writes about irregulaties in instruction encodings looks
really bad.  OTOH that should mostly affect programmer tools, that
is compilers, assemblers, debuggers.  And there is gcc port.  There
is other software (including ciforth).  So to me it is not clear if
this aspect will lower RISC-V adoption.

3) Missing instructions.  I am disappointed that to get effect of
2 word add (with carry between words) one needs 5 instructions.
But other machines disappointed me by making some instructions
slow, frequently slow enough that there is no speed benefit from
using them.  Also, once instrutions in in architecture there is
hard to get rid of it.  You get legacy of binaries using such
instruction and if you try to remove it those binaries will no
longer work.  OTOH adding instructions is easy.  So it is
natrual that new architecture start with small instruction set
and needed things get added when need is clear.

4) Code density.  Various people claim that some RISC-V features
lead to lower code density.  But all that I saw indicates that
RISC-V has very good code density.  Cortex M too has good code
density and they seem to be close one to another, with RISC-V
frequently being slightly better.  So, while code density
probably will not be deciding factor it certainly will not
prevent adaption of RISC-V (which could easily happen with less
dense encoding).  Mitch Asup in comp.arch claim that his
architecture routinly need about 30% less instructions than
RISC-V to do the same task.  But with code size his archiecture
seem be about even.  So for bigger machines it is mainly
question how well instruction fusion will work.

5) Optionality.  I do not like it and it is probably biggest
problem of RISC-V.  OTOH to have any chance of success RISC-V
need a buy-in from several independent parties.  I suspect that
the only practical way to get consensus from varied parties is
by making most of specification optional.  It is likely that
in the future modest number of variations will dominate.  In
microcontoller world I see 2 variations, and modest number for
bigger cores.  RISC-V may loose if vendors will push too many
variations.


-- 
                              Waldek Hebisch

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OT: Epic RISC-V rant Paul Rubin <no.email@nospam.invalid> - 2026-08-14 22:22 -0700
  Re: OT: Epic RISC-V rant jkn <jkn+nin@nicorp.co.uk> - 2026-08-15 10:10 +0100
  Re: OT: Epic RISC-V rant albert@spenarnc.xs4all.nl - 2026-08-22 18:23 +0200
    Re: OT: Epic RISC-V rant anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2026-08-22 16:45 +0000
  Re: OT: Epic RISC-V rant antispam@fricas.org (Waldek Hebisch) - 2026-08-22 22:36 +0000
    Re: OT: Epic RISC-V rant albert@spenarnc.xs4all.nl - 2026-08-23 13:44 +0200
      Re: OT: Epic RISC-V rant antispam@fricas.org (Waldek Hebisch) - 2026-08-29 19:49 +0000
    Re: OT: Epic RISC-V rant anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2026-08-24 07:55 +0000
      adding overflow and carry to every GPR (was Re: OT: Epic RISC-V rant) Kragen Javier Sitaker <kragen@canonical.org> - 2026-09-01 17:15 -0300
        Re: adding overflow and carry to every GPR (was Re: OT: Epic RISC-V rant) John Ames <commodorejohn@gmail.com> - 2026-09-01 14:31 -0700
          Re: adding overflow and carry to every GPR (was Re: OT: Epic RISC-V rant) BGB <cr88192@gmail.com> - 2026-09-01 17:18 -0500
          Re: adding overflow and carry to every GPR (was Re: OT: Epic RISC-V rant) MitchAlsup <user5857@newsgrouper.org.invalid> - 2026-09-02 02:04 +0000
            Re: adding overflow and carry to every GPR (was Re: OT: Epic RISC-V rant) John Ames <commodorejohn@gmail.com> - 2026-09-02 08:23 -0700
              Re: adding overflow and carry to every GPR (was Re: OT: Epic RISC-V rant) Kragen Javier Sitaker <kragen@canonical.org> - 2026-09-11 13:48 -0300
                Re: adding overflow and carry to every GPR (was Re: OT: Epic RISC-V rant) MitchAlsup <user5857@newsgrouper.org.invalid> - 2026-09-11 18:03 +0000
          Re: adding overflow and carry to every GPR (was Re: OT: Epic RISC-V rant) anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2026-09-09 11:16 +0000
        Re: adding overflow and carry to every GPR (was Re: OT: Epic RISC-V rant) MitchAlsup <user5857@newsgrouper.org.invalid> - 2026-09-02 01:53 +0000
        Re: adding overflow and carry to every GPR (was Re: OT: Epic RISC-V rant) anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2026-09-09 10:50 +0000
          Re: adding overflow and carry to every GPR (was Re: OT: Epic RISC-V rant) Paul Rubin <no.email@nospam.invalid> - 2026-09-09 22:10 -0700
          Re: adding overflow and carry to every GPR (was Re: OT: Epic RISC-V rant) Kragen Javier Sitaker <kragen@canonical.org> - 2026-09-11 14:28 -0300
    Re: OT: Epic RISC-V rant antispam@fricas.org (Waldek Hebisch) - 2026-08-29 20:12 +0000
    interrupt handling latency and weird register use (was Re: OT: Epic RISC-V rant) Kragen Javier Sitaker <kragen@canonical.org> - 2026-09-01 17:00 -0300
      Re: interrupt handling latency and weird register use (was Re: OT: Epic RISC-V rant) anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2026-09-01 20:51 +0000
      Re: interrupt handling latency and weird register use (was Re: OT: Epic RISC-V rant) MitchAlsup <user5857@newsgrouper.org.invalid> - 2026-09-02 01:43 +0000
    interrupt handling latency and weird register use (was Re: OT: Epic RISC-V rant) Andy Valencia <vandys@vsta.org> - 2026-09-02 08:11 -0700

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