The Wider von Neumann Neck (Re: FYI: Unified Memory Architecture (UMA))

From	Mild Shock <janburse@fastmail.fm>
Newsgroups	sci.logic
Subject	The Wider von Neumann Neck (Re: FYI: Unified Memory Architecture (UMA))
Date	2026-07-10 07:51 +0200
Message-ID	<112q19r$9puc$4@solani.org> (permalink)
References	<10seeh6$rsl4$2@solani.org> <10siao0$ud5u$2@solani.org> <112nnji$81rj$3@solani.org> <112omk9$8oqk$2@solani.org>

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Hi,

You are a fucking moron, arent you?

Most of the stuff in my pi-WAM happens
inside the L1 and L2 caches of the GPU.
Which is faster than normal RAM and has

a wider von Neuann Neck. You can try
yourself, in case you find an AI Laptop
with similary specs as the Radeon 860M.

The example is open source:

11.4 Giga Lips with a Budget Laptop
https://github.com/Jean-Luc-Picard-2021/gigabudget

I already wrote pi-WAM is designed to
not use memory contention. In particalur
it also uses local variables like pc and

accu of the idependent thread states,
which seems to be also pretty speedy.

Bye

Tanner Babadzhan schrieb:
 > Mild Shock wrote:
 >
 >> These novel GPUs , that are part of AI Laptops, feature Unified Memory
 >> Architecture (UMA).
 >> In the case of my Ryzen the main memory is 32 GB,
 >
 > you are in error talking bullshit, the bottleneck there is the max 4 
GB/s,
 > 4 times by paralleling, however the proper gddr5/6 gpu arrays goes up to
 > 4,000 GB/s by parallel design
 >
 > GDDR7 (2025–2026 standard)
 >      Max Bandwidth: 1,792 GB/s (RTX 5090, 32GB)
 >



Mild Shock schrieb:
> Hi,
> 
> These novel GPUs , that are part of AI Laptops,
> feature Unified Memory Architecture (UMA).
> In the case of my Ryzen the main memory is 32 GB,
> 
> and the GPU can access 16 GB. It is a design where
> CPUs and GPUs share a single coherent memory space,
> eliminating the need for separate host and
> 
> accelerator memory. Nevertheless the WebGPU API,
> works with some copy and synchronization semantics
> and buffer abstractions, which is not a big loss.
> 
> But all buffers reside in the same AI Lapop
> RAM. And the MIMD architecture allows instructions
> where seperate threads access the same
> 
> memory location, either for read or for write.
> There is also a data type atomic(T), which
> features operation such as AtomicAdd() etc.. etc..
> 
> BTW, I made a GitHub project of my exploration:
> 
> 11.4 Giga Lips with a Budget Laptop
> https://github.com/Jean-Luc-Picard-2021/gigabudget
> 
> BTW, pi-WAM is nevertheless optimized to have
> no memory contention. On the other hand pi-WAM
> is happy to access large memory areas.
> 
> Bye
> 
> BTW: The grandmother of these novel GPUs
> is NVIDIAs Volta which already appeared in
> 2017, meanwhile we have 2026.
> 
> See also:
> 
> Starting with the NVIDIA Volta architecture,
> Independent Thread Scheduling allows full
> concurrency between threads, regardless of warp.
> https://forums.developer.nvidia.com/t/back-to-simd/311983
> 
> The AMD Radeon 860M is an integrated graphics
> processor that does not have its own dedicated
> VRAM. Instead, it dynamically shares up to 50%
> of your total system RAM with the CPU in a
> standard Windows configuration.
> https://www.amd.com/en/blogs/2025/faqs-amd-variable-graphics-memory-vram-ai-model-sizes-quantization-mcp-more.html 
> 
> 
> Ryann Likunov schrieb:
>  > Mild Shock wrote:
>  >
>  >> Hi,
>  >>
>  >> I guess, you can read off how to do it here,
>  >> i.e. avoid TDR (DXGI_ERROR_DEVICE_HUNG 0x887A0006). The below compute
>  >> toys example has a similar
>  >>
>  >> approach, just like my π-WAM and Hack GPU backend,
>  >> that is based on a Instruction Set Architecture (ISA):
>  >
>  > how come they are not able to map the local RAM
>  > as gpu arrays for using them as local AI resource
>  >

Thread

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      The Wider von Neumann Neck (Re: FYI: Unified Memory Architecture (UMA)) Mild Shock <janburse@fastmail.fm> - 2026-07-10 07:51 +0200
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