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bad, better delay circuits

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  bad, better delay circuits John Larkin <jjlarkin@highlandtechnology.com> - 2017-03-18 10:04 -0700
    Re: bad, better delay circuits Winfield Hill <hill@rowland.harvard.edu> - 2017-03-18 12:29 -0700
      Re: bad, better delay circuits John Larkin <jjlarkin@highlandtechnology.com> - 2017-03-18 16:15 -0700
        Re: bad, better delay circuits Winfield Hill <hill@rowland.harvard.edu> - 2017-03-18 19:08 -0700
    Re: bad, better delay circuits "Tim Williams" <tiwill@seventransistorlabs.com> - 2017-03-18 17:02 -0500
      Re: bad, better delay circuits John Larkin <jjlarkin@highlandtechnology.com> - 2017-03-18 16:25 -0700
        Re: bad, better delay circuits rickman <gnuarm@gmail.com> - 2017-03-18 19:40 -0400
          Re: bad, better delay circuits dagmargoodboat@yahoo.com - 2017-03-19 10:42 -0700
            Re: bad, better delay circuits John Larkin <jjlarkin@highlandtechnology.com> - 2017-03-19 15:37 -0700
              Re: bad, better delay circuits "Tim Williams" <tiwill@seventransistorlabs.com> - 2017-03-19 22:24 -0500
                Re: bad, better delay circuits dagmargoodboat@yahoo.com - 2017-03-20 08:58 -0700
                  Re: bad, better delay circuits John Larkin <jjlarkin@highlandtechnology.com> - 2017-03-20 09:42 -0700
                    Re: bad, better delay circuits Robert Baer <robertbaer@localnet.com> - 2017-03-20 23:55 -0800
                  Re: bad, better delay circuits "Tim Williams" <tiwill@seventransistorlabs.com> - 2017-03-21 00:46 -0500
                Re: bad, better delay circuits bill.sloman@ieee.org - 2017-03-21 22:54 -0700
                  Re: bad, better delay circuits "Tim Williams" <tiwill@seventransistorlabs.com> - 2017-03-22 02:10 -0500
            Re: bad, better delay circuits rickman <gnuarm@gmail.com> - 2017-03-19 18:47 -0400
              Re: bad, better delay circuits Clifford Heath <no.spam@please.net> - 2017-03-20 09:55 +1100
                Re: bad, better delay circuits John Larkin <jjlarkin@highlandtechnology.com> - 2017-03-19 16:12 -0700
        Re: bad, better delay circuits "Tim Williams" <tiwill@seventransistorlabs.com> - 2017-03-19 10:32 -0500
    Re: bad, better delay circuits Clifford Heath <no.spam@please.net> - 2017-03-19 13:36 +1100
      Re: bad, better delay circuits John Larkin <jjlarkin@highlandtechnology.com> - 2017-03-18 19:44 -0700
        Re: bad, better delay circuits Clifford Heath <no.spam@please.net> - 2017-03-19 15:58 +1100
          Re: bad, better delay circuits John Larkin <jjlarkin@highlandtechnology.com> - 2017-03-19 15:43 -0700
            Re: bad, better delay circuits Winfield Hill <hill@rowland.harvard.edu> - 2017-03-19 17:54 -0700
              Re: bad, better delay circuits Clifford Heath <no.spam@please.net> - 2017-03-20 12:44 +1100
                Re: bad, better delay circuits Winfield Hill <hill@rowland.harvard.edu> - 2017-03-20 12:22 -0700
                  Re: bad, better delay circuits John Larkin <jjlarkin@highlandtechnology.com> - 2017-03-20 15:49 -0700
    Re: bad, better delay circuits whit3rd <whit3rd@gmail.com> - 2017-03-18 23:51 -0700
      Re: bad, better delay circuits John Larkin <jjlarkin@highlandtechnology.com> - 2017-03-19 08:22 -0700
    Re: bad, better delay circuits George Herold <gherold@teachspin.com> - 2017-03-20 17:55 -0700
    Re: bad, better delay circuits John Larkin <jjlarkin@highlandtechnology.com> - 2017-03-22 08:54 -0700
      Re: bad, better delay circuits JM <dontreplytothis173@gmail.com> - 2017-03-22 16:02 +0000
        Re: bad, better delay circuits John Larkin <jjlarkin@highlandtechnology.com> - 2017-03-22 09:47 -0700
      Re: bad, better delay circuits Winfield Hill <hill@rowland.harvard.edu> - 2017-03-22 10:31 -0700
        Re: bad, better delay circuits John Larkin <jjlarkin@highlandtechnology.com> - 2017-03-22 10:52 -0700

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#452539

On 19/03/17 04:04, John Larkin wrote:
>
>
> We want to trim the rising edge times of some pulses. The obvious
> circuit is a current source + capacitor linear ramp followed by a
> comparator.
>
> The first circuit here was the initial idea, seems simple, until I
> started thinking harder.
>
> https://dl.dropboxusercontent.com/u/53724080/Circuits/Timing/Delay_Bad_Good.JPG
>
> BSS123 is about the best compromise between capacitance and ON
> resistance, and we have it. The two problems here are
>
> the g-d capacitance of Q1 shoots an ugly negative spike into C1 at
> ramp start

You could ditch the inverter for a flip-flop, and add a coupling
capacitor from /Q to cancel the g-d capacitance spike... as long
as you could get close enough tolerance to match it.

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#452540

On Sun, 19 Mar 2017 13:36:13 +1100, Clifford Heath
<no.spam@please.net> wrote:

>On 19/03/17 04:04, John Larkin wrote:
>>
>>
>> We want to trim the rising edge times of some pulses. The obvious
>> circuit is a current source + capacitor linear ramp followed by a
>> comparator.
>>
>> The first circuit here was the initial idea, seems simple, until I
>> started thinking harder.
>>
>> https://dl.dropboxusercontent.com/u/53724080/Circuits/Timing/Delay_Bad_Good.JPG
>>
>> BSS123 is about the best compromise between capacitance and ON
>> resistance, and we have it. The two problems here are
>>
>> the g-d capacitance of Q1 shoots an ugly negative spike into C1 at
>> ramp start
>
>You could ditch the inverter for a flip-flop, and add a coupling
>capacitor from /Q to cancel the g-d capacitance spike... as long
>as you could get close enough tolerance to match it.

That sort of thing is always tricky. To keep the ramp from wobbling at
the start, the charge injections would have to be time aligned. The
diode is a lot easier.


-- 

John Larkin         Highland Technology, Inc

lunatic fringe electronics 

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#452544

On 19/03/17 13:44, John Larkin wrote:
> On Sun, 19 Mar 2017 13:36:13 +1100, Clifford Heath
> <no.spam@please.net> wrote:
>
>> On 19/03/17 04:04, John Larkin wrote:
>>>
>>>
>>> We want to trim the rising edge times of some pulses. The obvious
>>> circuit is a current source + capacitor linear ramp followed by a
>>> comparator.
>>>
>>> The first circuit here was the initial idea, seems simple, until I
>>> started thinking harder.
>>>
>>> https://dl.dropboxusercontent.com/u/53724080/Circuits/Timing/Delay_Bad_Good.JPG
>>>
>>> BSS123 is about the best compromise between capacitance and ON
>>> resistance, and we have it. The two problems here are
>>>
>>> the g-d capacitance of Q1 shoots an ugly negative spike into C1 at
>>> ramp start
>>
>> You could ditch the inverter for a flip-flop, and add a coupling
>> capacitor from /Q to cancel the g-d capacitance spike... as long
>> as you could get close enough tolerance to match it.
>
> That sort of thing is always tricky. To keep the ramp from wobbling at
> the start, the charge injections would have to be time aligned.

In general, how closer can you expect Q and /Q to be aligned,
for the kind of CMOS FF you'd choose? (given that rising and falling
slopes might differ, as well).

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#452626

On Sun, 19 Mar 2017 15:58:39 +1100, Clifford Heath
<no.spam@please.net> wrote:

>On 19/03/17 13:44, John Larkin wrote:
>> On Sun, 19 Mar 2017 13:36:13 +1100, Clifford Heath
>> <no.spam@please.net> wrote:
>>
>>> On 19/03/17 04:04, John Larkin wrote:
>>>>
>>>>
>>>> We want to trim the rising edge times of some pulses. The obvious
>>>> circuit is a current source + capacitor linear ramp followed by a
>>>> comparator.
>>>>
>>>> The first circuit here was the initial idea, seems simple, until I
>>>> started thinking harder.
>>>>
>>>> https://dl.dropboxusercontent.com/u/53724080/Circuits/Timing/Delay_Bad_Good.JPG
>>>>
>>>> BSS123 is about the best compromise between capacitance and ON
>>>> resistance, and we have it. The two problems here are
>>>>
>>>> the g-d capacitance of Q1 shoots an ugly negative spike into C1 at
>>>> ramp start
>>>
>>> You could ditch the inverter for a flip-flop, and add a coupling
>>> capacitor from /Q to cancel the g-d capacitance spike... as long
>>> as you could get close enough tolerance to match it.
>>
>> That sort of thing is always tricky. To keep the ramp from wobbling at
>> the start, the charge injections would have to be time aligned.
>
>In general, how closer can you expect Q and /Q to be aligned,
>for the kind of CMOS FF you'd choose? (given that rising and falling
>slopes might differ, as well).

The flop would be fine. We have a 1 ns Tpd CMOS part in stock, edges
maybe 500 ps, and they should be well matched. A flipflop makes a nice
symmetric complement-edge thing even if you don't really need a
flipflop. 

(TI used to make a complementary-output gate, in classic TTL I think.
That's a handy function.)

The problem is the mosfet. Its turn-off behavior is ugly in a very
complex way. Diodes are easier to understand.


-- 

John Larkin         Highland Technology, Inc

jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com

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#452651

John Larkin wrote...
>
> The problem is the mosfet. Its turn-off
> behavior is ugly in a very complex way.
> Diodes are easier to understand.

 The nice thing about tri-state gates, they have
 awesome optimized low-voltage 3.3V mosfets to
 pull down the cap, and optimized gate drive
 to turn them off.  Can't match w/ a discrete.


-- 
 Thanks,
    - Win

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#452661

On 20/03/17 11:54, Winfield Hill wrote:
> John Larkin wrote...
>>
>> The problem is the mosfet. Its turn-off
>> behavior is ugly in a very complex way.
>> Diodes are easier to understand.
>
>  The nice thing about tri-state gates, they have
>  awesome optimized low-voltage 3.3V mosfets to
>  pull down the cap, and optimized gate drive
>  to turn them off.  Can't match w/ a discrete.

You don't lose anything by having a high-side MOSFET connected (though off)?

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#452764

Clifford Heath wrote...
>
>On 20/03/17 11:54, Winfield Hill wrote:
>> John Larkin wrote...
>>>
>>> The problem is the mosfet. Its turn-off
>>> behavior is ugly in a very complex way.
>>> Diodes are easier to understand.
>>
>>  The nice thing about tri-state gates, they have
>>  awesome optimized low-voltage 3.3V mosfets to
>>  pull down the cap, and optimized gate drive
>>  to turn them off.  Can't match w/ a discrete.
>
> You don't lose anything by having a high-side
> MOSFET connected (though off)?

 The issue would only be the gate output node's
 off capacitance.  I found it to be quite small,
 although I haven't measured it, should do so.


-- 
 Thanks,
    - Win

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#452795

On 20 Mar 2017 12:22:18 -0700, Winfield Hill
<hill@rowland.harvard.edu> wrote:

>Clifford Heath wrote...
>>
>>On 20/03/17 11:54, Winfield Hill wrote:
>>> John Larkin wrote...
>>>>
>>>> The problem is the mosfet. Its turn-off
>>>> behavior is ugly in a very complex way.
>>>> Diodes are easier to understand.
>>>
>>>  The nice thing about tri-state gates, they have
>>>  awesome optimized low-voltage 3.3V mosfets to
>>>  pull down the cap, and optimized gate drive
>>>  to turn them off.  Can't match w/ a discrete.
>>
>> You don't lose anything by having a high-side
>> MOSFET connected (though off)?
>
> The issue would only be the gate output node's
> off capacitance.  I found it to be quite small,
> although I haven't measured it, should do so.

Yeah, how much charge injection might you get when the tri-state
output switches hi-Z?

I'f try it but I'm in the mountains, nary an oscilloscope in sight.


-- 

John Larkin         Highland Technology, Inc

jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com

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#452550

On Saturday, March 18, 2017 at 10:04:50 AM UTC-7, John Larkin wrote:
> We want to trim the rising edge times of some pulses. The obvious
> circuit is a current source + capacitor linear ramp ....

> The second circuit looks better. The mux switches in C2...

Why not just modulate that current
source?  A mux/switch isn't the most repeatable of resistors.   

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#452578

On Sat, 18 Mar 2017 23:51:02 -0700 (PDT), whit3rd <whit3rd@gmail.com>
wrote:

>On Saturday, March 18, 2017 at 10:04:50 AM UTC-7, John Larkin wrote:
>> We want to trim the rising edge times of some pulses. The obvious
>> circuit is a current source + capacitor linear ramp ....
>
>> The second circuit looks better. The mux switches in C2...
>
>Why not just modulate that current
>source?  A mux/switch isn't the most repeatable of resistors.   

Sure, that's the easy one. Two currents and two caps gives me four
ranges.

But mux's work fine.




-- 

John Larkin         Highland Technology, Inc

lunatic fringe electronics 

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#452816

On Saturday, March 18, 2017 at 1:04:50 PM UTC-4, John Larkin wrote:
> We want to trim the rising edge times of some pulses. The obvious
> circuit is a current source + capacitor linear ramp followed by a
> comparator.
> 
> The first circuit here was the initial idea, seems simple, until I
> started thinking harder.
> 
> https://dl.dropboxusercontent.com/u/53724080/Circuits/Timing/Delay_Bad_Good.JPG
> 
> BSS123 is about the best compromise between capacitance and ON
> resistance, and we have it. The two problems here are
> 
> the g-d capacitance of Q1 shoots an ugly negative spike into C1 at
> ramp start and
> 
> the drain capacitance of Q2 is nonlinear, which is maybe OK, but the
> drain voltage can wander all over the place. That modulates the ramp
> slope, and the body diode could conduct at ramp discharge time. Fixes
> for that are variations of ugly.
> 
> E-Phemts would be better than mosfets, but that would multiply the
> parts cost by 5x or so. Open-drain cmos gates could be interesting,
> but we don't have any in stock
> 
> 
> The second circuit looks better. The mux switches in C2, or keeps it
> grounded. These "bus switch" parts are actually killer analog
> multiplexers at a fraction of the price of things sold as analog
> mux's.
Huh, can I use one to switch gain in a lock-in thing? 
(sorry, I don't know much about high speed.) 

> 
> The comparator is of course an LVDS line receiver, another example of
> using a part off-label and saving a bunch of dollars and nanoseconds.
> 
> Another bus switch could be used to discharge the cap, instead of the
> diode, but sadly their control-input delays are high. That's the
> pattern in mux's: fast signal path, slow switching.
What's slow?  Or perhaps more important (lockin-wise) is the delay
constant and equal (on/off)?  

George H. 
> 
> 
> 
> 
> -- 
> 
> John Larkin         Highland Technology, Inc
> 
> lunatic fringe electronics

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#453043

On Sat, 18 Mar 2017 10:04:42 -0700, John Larkin
<jjlarkin@highlandtechnology.com> wrote:

>
>
>We want to trim the rising edge times of some pulses. The obvious
>circuit is a current source + capacitor linear ramp followed by a
>comparator.
>
>The first circuit here was the initial idea, seems simple, until I
>started thinking harder.
>
>https://dl.dropboxusercontent.com/u/53724080/Circuits/Timing/Delay_Bad_Good.JPG
>
>BSS123 is about the best compromise between capacitance and ON
>resistance, and we have it. The two problems here are
>
>the g-d capacitance of Q1 shoots an ugly negative spike into C1 at
>ramp start and
>
>the drain capacitance of Q2 is nonlinear, which is maybe OK, but the
>drain voltage can wander all over the place. That modulates the ramp
>slope, and the body diode could conduct at ramp discharge time. Fixes
>for that are variations of ugly.
>
>E-Phemts would be better than mosfets, but that would multiply the
>parts cost by 5x or so. Open-drain cmos gates could be interesting,
>but we don't have any in stock
>
>
>The second circuit looks better. The mux switches in C2, or keeps it
>grounded. These "bus switch" parts are actually killer analog
>multiplexers at a fraction of the price of things sold as analog
>mux's.
>
>The comparator is of course an LVDS line receiver, another example of
>using a part off-label and saving a bunch of dollars and nanoseconds.
>
>Another bus switch could be used to discharge the cap, instead of the
>diode, but sadly their control-input delays are high. That's the
>pattern in mux's: fast signal path, slow switching.


One of my guys is arguing that we should use an ATF-55143 ephemt to
discharge the caps. That would slam them hard all the way to ground
and eliminate the diode tempco effect on timing. Those phemts have
absurdly small Cg-d, so wouldn't pump the ramp down at startup.

He's right of course. I hate it when other people are right.

I think we could keep the analog mux/bus switch thing to switch the
big cap in and out.


-- 

John Larkin         Highland Technology, Inc

jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com

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#453046

On 22/03/2017 15:54, John Larkin wrote:
> On Sat, 18 Mar 2017 10:04:42 -0700, John Larkin
> <jjlarkin@highlandtechnology.com> wrote:
>
>>
>>
>> We want to trim the rising edge times of some pulses. The obvious
>> circuit is a current source + capacitor linear ramp followed by a
>> comparator.
>>
>> The first circuit here was the initial idea, seems simple, until I
>> started thinking harder.
>>
>> https://dl.dropboxusercontent.com/u/53724080/Circuits/Timing/Delay_Bad_Good.JPG
>>
>> BSS123 is about the best compromise between capacitance and ON
>> resistance, and we have it. The two problems here are
>>
>> the g-d capacitance of Q1 shoots an ugly negative spike into C1 at
>> ramp start and
>>
>> the drain capacitance of Q2 is nonlinear, which is maybe OK, but the
>> drain voltage can wander all over the place. That modulates the ramp
>> slope, and the body diode could conduct at ramp discharge time. Fixes
>> for that are variations of ugly.
>>
>> E-Phemts would be better than mosfets, but that would multiply the
>> parts cost by 5x or so. Open-drain cmos gates could be interesting,
>> but we don't have any in stock
>>
>>
>> The second circuit looks better. The mux switches in C2, or keeps it
>> grounded. These "bus switch" parts are actually killer analog
>> multiplexers at a fraction of the price of things sold as analog
>> mux's.
>>
>> The comparator is of course an LVDS line receiver, another example of
>> using a part off-label and saving a bunch of dollars and nanoseconds.
>>
>> Another bus switch could be used to discharge the cap, instead of the
>> diode, but sadly their control-input delays are high. That's the
>> pattern in mux's: fast signal path, slow switching.
>
>
> One of my guys is arguing that we should use an ATF-55143 ephemt to
> discharge the caps. That would slam them hard all the way to ground
> and eliminate the diode tempco effect on timing. Those phemts have
> absurdly small Cg-d, so wouldn't pump the ramp down at startup.
>
> He's right of course. I hate it when other people are right.
>

Sack him! Get in a yes man... ;-)

> I think we could keep the analog mux/bus switch thing to switch the
> big cap in and out.
>
>

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#453049

On Wed, 22 Mar 2017 16:02:17 +0000, JM <dontreplytothis173@gmail.com>
wrote:

>On 22/03/2017 15:54, John Larkin wrote:
>> On Sat, 18 Mar 2017 10:04:42 -0700, John Larkin
>> <jjlarkin@highlandtechnology.com> wrote:
>>
>>>
>>>
>>> We want to trim the rising edge times of some pulses. The obvious
>>> circuit is a current source + capacitor linear ramp followed by a
>>> comparator.
>>>
>>> The first circuit here was the initial idea, seems simple, until I
>>> started thinking harder.
>>>
>>> https://dl.dropboxusercontent.com/u/53724080/Circuits/Timing/Delay_Bad_Good.JPG
>>>
>>> BSS123 is about the best compromise between capacitance and ON
>>> resistance, and we have it. The two problems here are
>>>
>>> the g-d capacitance of Q1 shoots an ugly negative spike into C1 at
>>> ramp start and
>>>
>>> the drain capacitance of Q2 is nonlinear, which is maybe OK, but the
>>> drain voltage can wander all over the place. That modulates the ramp
>>> slope, and the body diode could conduct at ramp discharge time. Fixes
>>> for that are variations of ugly.
>>>
>>> E-Phemts would be better than mosfets, but that would multiply the
>>> parts cost by 5x or so. Open-drain cmos gates could be interesting,
>>> but we don't have any in stock
>>>
>>>
>>> The second circuit looks better. The mux switches in C2, or keeps it
>>> grounded. These "bus switch" parts are actually killer analog
>>> multiplexers at a fraction of the price of things sold as analog
>>> mux's.
>>>
>>> The comparator is of course an LVDS line receiver, another example of
>>> using a part off-label and saving a bunch of dollars and nanoseconds.
>>>
>>> Another bus switch could be used to discharge the cap, instead of the
>>> diode, but sadly their control-input delays are high. That's the
>>> pattern in mux's: fast signal path, slow switching.
>>
>>
>> One of my guys is arguing that we should use an ATF-55143 ephemt to
>> discharge the caps. That would slam them hard all the way to ground
>> and eliminate the diode tempco effect on timing. Those phemts have
>> absurdly small Cg-d, so wouldn't pump the ramp down at startup.
>>
>> He's right of course. I hate it when other people are right.
>>
>
>Sack him! Get in a yes man... ;-)

It's great when other people have good ideas. But it means that I
missed or dismissed a good idea. That's the part that I hate.


-- 

John Larkin         Highland Technology, Inc

jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com

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#453066

John Larkin wrote...
>
> One of my guys is arguing that we should use
> an ATF-55143 ephemt to discharge the caps.

 What's Coss for that FET?


-- 
 Thanks,
    - Win

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#453077

On 22 Mar 2017 10:31:20 -0700, Winfield Hill
<hill@rowland.harvard.edu> wrote:

>John Larkin wrote...
>>
>> One of my guys is arguing that we should use
>> an ATF-55143 ephemt to discharge the caps.
>
> What's Coss for that FET?

My guy says that the Spice model has Cds+Cpackage totalling about 0.22
pF. I'd guess a tad higher from eyeballing the s-parameters, maybe 0.6
pF, but that includes the Miller feedback, not an issue if we are
switching on and off. Cd just adds a tiny bit to my ramp capacitor.

The gate-drain capacitances are tiny in phemts, 0.143 pF in the ATF
model. And the gate on/off swing will be small, 0.6 volts or so, so
the g-d charge injection will be almost nil. I wish data sheets would
include more capacitance specs; the RF boys sort of dump RF into the
gate and expect more RF at the drain, not much help if you want to
switch.


-- 

John Larkin         Highland Technology, Inc

jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com

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