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really bad oscillators

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  really bad oscillators John Larkin <jjlarkin@highlandtechnology.com> - 2018-10-06 10:33 -0700
    Re: really bad oscillators "Tim Williams" <tiwill@seventransistorlabs.com> - 2018-10-06 12:51 -0500
      Re: really bad oscillators whit3rd <whit3rd@gmail.com> - 2018-10-06 15:16 -0700
        Re: really bad oscillators John Larkin <jjlarkin@highlandtechnology.com> - 2018-10-06 15:52 -0700
        Re: really bad oscillators "Tim Williams" <tiwill@seventransistorlabs.com> - 2018-10-06 22:55 -0500
    Re: really bad oscillators George Herold <gherold@teachspin.com> - 2018-10-06 11:33 -0700
    Re: really bad oscillators John Larkin <jjlarkin@highlandtechnology.com> - 2018-10-06 11:35 -0700
    Re: really bad oscillators <698839253X6D445TD@nospam.org> - 2018-10-06 18:49 +0000
    Re: really bad oscillators Steve Wilson <9fe142ac@gmail.com> - 2018-10-06 11:50 -0700
    Re: really bad oscillators bloggs.fredbloggs.fred@gmail.com - 2018-10-06 12:13 -0700
      Re: really bad oscillators John Larkin <jjlarkin@highlandtechnology.com> - 2018-10-06 15:55 -0700
    Re: really bad oscillators Gerhard Hoffmann <ghf@hoffmann-hochfrequenz.de> - 2018-10-06 21:28 +0200
      Re: really bad oscillators Gerhard Hoffmann <ghf@hoffmann-hochfrequenz.de> - 2018-10-06 21:35 +0200
      Re: really bad oscillators John Larkin <jjlarkin@highlandtechnology.com> - 2018-10-06 16:01 -0700
    Re: really bad oscillators bitrex <user@example.net> - 2018-10-06 21:59 -0400
      Re: really bad oscillators John Larkin <jjlarkin@highlandtechnology.com> - 2018-10-07 08:05 -0700
        Re: really bad oscillators bitrex <user@example.net> - 2018-10-07 23:04 -0400
          Re: really bad oscillators John Larkin <jjlarkin@highlandtechnology.com> - 2018-10-07 21:10 -0700
        Re: really bad oscillators bitrex <user@example.net> - 2018-10-07 23:12 -0400

#518545 — really bad oscillators

A timestamper is a circuit that latches the time of arrival of a pulse
edge. We use a clock and a binary counter as MC, the master counter
definition of time. We extend those MC bits down into picoseconds with
a time interpolator, adding 8 to 12 bits below the counter LSB.

One way to test a time stamper is to stamp pulses that are random in
time, and then histogram/analyze the codes. That can catch all sorts
of nasties, like stuck or shorted bits or interpolator problems; we've
done the math on that. In the test set that I'm designing, I want a
simple but really bad pulse generator, maybe around 1 MHz with tons of
period jitter, to get good statistics and never alias against the
master clock. Aliasing can make really weird histograms.

https://www.dropbox.com/s/vv6dqeffxrkmca3/Timestamp_Noisy_Osc.jpg?raw=1

The single inverting schmitt oscillator is probably good enough, but
it's fun to consider other really nasty oscillators. A bad power
supply will only help.

We have an FPGA, so I guess we could build a pseudorandom bit stream,
filter that a little, and use that to confuse a schmitt oscillator.
The kids might enjoy programming that.




-- 

John Larkin         Highland Technology, Inc

lunatic fringe electronics 

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#518548

Zener diode noise generator + bandpass + comparator.

Tim

-- 
Seven Transistor Labs, LLC
Electrical Engineering Consultation and Design
Website: https://www.seventransistorlabs.com/

"John Larkin" <jjlarkin@highlandtechnology.com> wrote in message 
news:k5rhrdp40aavhpffehpmnc5ipkcb91lg9j@4ax.com...
>
>
> A timestamper is a circuit that latches the time of arrival of a pulse
> edge. We use a clock and a binary counter as MC, the master counter
> definition of time. We extend those MC bits down into picoseconds with
> a time interpolator, adding 8 to 12 bits below the counter LSB.
>
> One way to test a time stamper is to stamp pulses that are random in
> time, and then histogram/analyze the codes. That can catch all sorts
> of nasties, like stuck or shorted bits or interpolator problems; we've
> done the math on that. In the test set that I'm designing, I want a
> simple but really bad pulse generator, maybe around 1 MHz with tons of
> period jitter, to get good statistics and never alias against the
> master clock. Aliasing can make really weird histograms.
>
> https://www.dropbox.com/s/vv6dqeffxrkmca3/Timestamp_Noisy_Osc.jpg?raw=1
>
> The single inverting schmitt oscillator is probably good enough, but
> it's fun to consider other really nasty oscillators. A bad power
> supply will only help.
>
> We have an FPGA, so I guess we could build a pseudorandom bit stream,
> filter that a little, and use that to confuse a schmitt oscillator.
> The kids might enjoy programming that.
>
>
>
>
> -- 
>
> John Larkin         Highland Technology, Inc
>
> lunatic fringe electronics
> 

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#518588

On Saturday, October 6, 2018 at 10:51:56 AM UTC-7, Tim Williams wrote:
> Zener diode noise generator + bandpass + comparator.

Good, but the Zener capacitance might have some bandpass as well.
A neon lamp, transformer-coupled to a sense/trigger, and biased
to conduction, is plenty noisy over a broad band; there's plenty
of lore on the corrections for gas diode noise correlations.

As I understand it, good Zener noise sources need aged, selected
components.

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#518591

On Sat, 6 Oct 2018 15:16:47 -0700 (PDT), whit3rd <whit3rd@gmail.com>
wrote:

>On Saturday, October 6, 2018 at 10:51:56 AM UTC-7, Tim Williams wrote:
>> Zener diode noise generator + bandpass + comparator.
>
>Good, but the Zener capacitance might have some bandpass as well.
>A neon lamp, transformer-coupled to a sense/trigger, and biased
>to conduction, is plenty noisy over a broad band; there's plenty
>of lore on the corrections for gas diode noise correlations.
>
>As I understand it, good Zener noise sources need aged, selected
>components.

If you just want noise, and aren't too picky about spectra and such, a
maybe 10 volt zener biased to around 1 mA will make about 300 nv/rthz
wideband noise.


-- 

John Larkin         Highland Technology, Inc

lunatic fringe electronics 

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#518616

"whit3rd" <whit3rd@gmail.com> wrote in message 
news:4b7b87b7-b261-493f-975b-1b75364a4828@googlegroups.com...
> On Saturday, October 6, 2018 at 10:51:56 AM UTC-7, Tim Williams wrote:
>> Zener diode noise generator + bandpass + comparator.
>
> Good, but the Zener capacitance might have some bandpass as well.

Right, that sets the maximum bandwidth.  You can tone it down from there as 
you like, for whatever frequency / phase noise range you want.  Presumably, 
the smaller fraction of the distribution you take, the more sigmas you'll 
have that look "normal" around f_c.  Setting the bandwidth to be a few times 
the interpolator step would seem appropriate.

And if this is still too slow (~100s kHz would be typical), tack on a high 
frequency clock and mixer, and bandpass some more.  Of course if that 
doesn't offer enough bandwidth, you'll need to figure something else out, 
but in any case, noise generators are probably not something John has a 
shortage of. :)

Tim

-- 
Seven Transistor Labs, LLC
Electrical Engineering Consultation and Design
Website: https://www.seventransistorlabs.com/ 

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#518555

On Saturday, October 6, 2018 at 1:33:36 PM UTC-4, John Larkin wrote:
> A timestamper is a circuit that latches the time of arrival of a pulse
> edge. We use a clock and a binary counter as MC, the master counter
> definition of time. We extend those MC bits down into picoseconds with
> a time interpolator, adding 8 to 12 bits below the counter LSB.
> 
> One way to test a time stamper is to stamp pulses that are random in
> time, and then histogram/analyze the codes. That can catch all sorts
> of nasties, like stuck or shorted bits or interpolator problems; we've
> done the math on that. In the test set that I'm designing, I want a
> simple but really bad pulse generator, maybe around 1 MHz with tons of
> period jitter, to get good statistics and never alias against the
> master clock. Aliasing can make really weird histograms.
> 
> https://www.dropbox.com/s/vv6dqeffxrkmca3/Timestamp_Noisy_Osc.jpg?raw=1
> 
> The single inverting schmitt oscillator is probably good enough, but
> it's fun to consider other really nasty oscillators. A bad power
> supply will only help.
> 
> We have an FPGA, so I guess we could build a pseudorandom bit stream,
> filter that a little, and use that to confuse a schmitt oscillator.
> The kids might enjoy programming that.
> 
Hmm I don't know exactly what you want.
But led spads come in all varieties, 
some are really nice 'ideal' counters,
(shine light and get the 'right' statistics.) 
and others have all sorts of after-pulsing and such,
that gives long time frame 1/f type noise... 
(I don't understand the 1/f part.)

I think I have two led spad's now, a red at 25V and green 
at 80V... I haven't done the statistics on the green one. 

You can get the same sort of thing with an avalanche zener, 
but no light intensity knob.  

George H.  

> 
> 
> 
> -- 
> 
> John Larkin         Highland Technology, Inc
> 
> lunatic fringe electronics

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#518556

On Sat, 06 Oct 2018 10:33:25 -0700, John Larkin
<jjlarkin@highlandtechnology.com> wrote:

>
>
>A timestamper is a circuit that latches the time of arrival of a pulse
>edge. We use a clock and a binary counter as MC, the master counter
>definition of time. We extend those MC bits down into picoseconds with
>a time interpolator, adding 8 to 12 bits below the counter LSB.
>
>One way to test a time stamper is to stamp pulses that are random in
>time, and then histogram/analyze the codes. That can catch all sorts
>of nasties, like stuck or shorted bits or interpolator problems; we've
>done the math on that. In the test set that I'm designing, I want a
>simple but really bad pulse generator, maybe around 1 MHz with tons of
>period jitter, to get good statistics and never alias against the
>master clock. Aliasing can make really weird histograms.
>
>https://www.dropbox.com/s/vv6dqeffxrkmca3/Timestamp_Noisy_Osc.jpg?raw=1
>
>The single inverting schmitt oscillator is probably good enough, but
>it's fun to consider other really nasty oscillators. A bad power
>supply will only help.
>
>We have an FPGA, so I guess we could build a pseudorandom bit stream,
>filter that a little, and use that to confuse a schmitt oscillator.
>The kids might enjoy programming that.

I already use a TPS54302 spread-spectrum switcher in the power supply!


-- 

John Larkin         Highland Technology, Inc

lunatic fringe electronics 

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#518562

John Larkin wrote
>A timestamper is a circuit that latches the time of arrival of a pulse
>edge. We use a clock and a binary counter as MC, the master counter
>definition of time. We extend those MC bits down into picoseconds with
>a time interpolator, adding 8 to 12 bits below the counter LSB.
>
>One way to test a time stamper is to stamp pulses that are random in
>time, and then histogram/analyze the codes. That can catch all sorts
>of nasties, like stuck or shorted bits or interpolator problems; we've
>done the math on that. In the test set that I'm designing, I want a
>simple but really bad pulse generator, maybe around 1 MHz with tons of
>period jitter, to get good statistics and never alias against the
>master clock. Aliasing can make really weird histograms.
>
>https://www.dropbox.com/s/vv6dqeffxrkmca3/Timestamp_Noisy_Osc.jpg?raw=1
>
>The single inverting schmitt oscillator is probably good enough, but
>it's fun to consider other really nasty oscillators. A bad power
>supply will only help.
>
>We have an FPGA, so I guess we could build a pseudorandom bit stream,
>filter that a little, and use that to confuse a schmitt oscillator.
>The kids might enjoy programming that.

74HC4046 with the VCO input connected to noise source?
Radioactive decay, noise diode...
?

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#518565

On Saturday, October 6, 2018 at 1:33:36 PM UTC-4, John Larkin wrote:
> A timestamper is a circuit that latches the time of arrival of a pulse
> edge. We use a clock and a binary counter as MC, the master counter
> definition of time. We extend those MC bits down into picoseconds with
> a time interpolator, adding 8 to 12 bits below the counter LSB.
> 
> One way to test a time stamper is to stamp pulses that are random in
> time, and then histogram/analyze the codes. That can catch all sorts
> of nasties, like stuck or shorted bits or interpolator problems; we've
> done the math on that. In the test set that I'm designing, I want a
> simple but really bad pulse generator, maybe around 1 MHz with tons of
> period jitter, to get good statistics and never alias against the
> master clock. Aliasing can make really weird histograms.
> 
> https://www.dropbox.com/s/vv6dqeffxrkmca3/Timestamp_Noisy_Osc.jpg?raw=1
 
> The single inverting schmitt oscillator is probably good enough, but
> it's fun to consider other really nasty oscillators. A bad power
> supply will only help.

Just for reference, truly random noise generators are hard. Terry Ritter did some analysis a while back and discovered problems in circuits that appeared to work well.

PRELIMINARY Noise Source Experiments
http://www.ciphersbyritter.com/NOISE/NOISRC.HTM

Experimental measures reveal problems where previously none were suspected
http://www.ciphersbyritter.com/NOISE/NOISCHAR.HTM 

An alternative is a Linear Feedback Shift Register as a pseudorandom noise generator. Here are some examples. Sorry for the wrap.

https://en.wikipedia.org/wiki/Linear-feedback_shift_register

https://en.wikipedia.org/wiki/Xorshift

http://www.xilinx.com/support/documentation/application_notes/xapp052.pdf

https://en.wikipedia.org/wiki/Linear-feedback_shift_register

https://en.wikipedia.org/wiki/Pseudorandom_binary_sequence

https://web.archive.org/web/20161007061934/http://courses.cse.tamu.edu/csce680/walker/lfsr_table.pdf

https://web.archive.org/web/20161007061934if_/http://courses.cse.tamu.edu/csce680/walker/lfsr_table.pdf 

https://www.elektormagazine.com/files/attachment/281


> John Larkin         Highland Technology, Inc
> 
> lunatic fringe electronics

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#518570

On Saturday, October 6, 2018 at 1:33:36 PM UTC-4, John Larkin wrote:
> A timestamper is a circuit that latches the time of arrival of a pulse
> edge. We use a clock and a binary counter as MC, the master counter
> definition of time. We extend those MC bits down into picoseconds with
> a time interpolator, adding 8 to 12 bits below the counter LSB.
> 
> One way to test a time stamper is to stamp pulses that are random in
> time, and then histogram/analyze the codes. That can catch all sorts
> of nasties, like stuck or shorted bits or interpolator problems; we've
> done the math on that. In the test set that I'm designing, I want a
> simple but really bad pulse generator, maybe around 1 MHz with tons of
> period jitter, to get good statistics and never alias against the
> master clock. Aliasing can make really weird histograms.
> 
> https://www.dropbox.com/s/vv6dqeffxrkmca3/Timestamp_Noisy_Osc.jpg?raw=1
> 
> The single inverting schmitt oscillator is probably good enough, but
> it's fun to consider other really nasty oscillators. A bad power
> supply will only help.
> 
> We have an FPGA, so I guess we could build a pseudorandom bit stream,
> filter that a little, and use that to confuse a schmitt oscillator.
> The kids might enjoy programming that.

Is that interpolator the ramp based method? May be simpler to add a test port wherein you can mung up the current source ( or whatever you're using) with some noise.

> 
> 
> 
> 
> -- 
> 
> John Larkin         Highland Technology, Inc
> 
> lunatic fringe electronics

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#518592

On Sat, 6 Oct 2018 12:13:57 -0700 (PDT),
bloggs.fredbloggs.fred@gmail.com wrote:

>On Saturday, October 6, 2018 at 1:33:36 PM UTC-4, John Larkin wrote:
>> A timestamper is a circuit that latches the time of arrival of a pulse
>> edge. We use a clock and a binary counter as MC, the master counter
>> definition of time. We extend those MC bits down into picoseconds with
>> a time interpolator, adding 8 to 12 bits below the counter LSB.
>> 
>> One way to test a time stamper is to stamp pulses that are random in
>> time, and then histogram/analyze the codes. That can catch all sorts
>> of nasties, like stuck or shorted bits or interpolator problems; we've
>> done the math on that. In the test set that I'm designing, I want a
>> simple but really bad pulse generator, maybe around 1 MHz with tons of
>> period jitter, to get good statistics and never alias against the
>> master clock. Aliasing can make really weird histograms.
>> 
>> https://www.dropbox.com/s/vv6dqeffxrkmca3/Timestamp_Noisy_Osc.jpg?raw=1
>> 
>> The single inverting schmitt oscillator is probably good enough, but
>> it's fun to consider other really nasty oscillators. A bad power
>> supply will only help.
>> 
>> We have an FPGA, so I guess we could build a pseudorandom bit stream,
>> filter that a little, and use that to confuse a schmitt oscillator.
>> The kids might enjoy programming that.
>
>Is that interpolator the ramp based method? 

Yes.

>May be simpler to add a test port wherein you can mung up the current source ( or whatever you're using) with some noise.

I need to do a closed-box test on both a new design and a legacy
version, so I don't want to do inside the DUT.

It's just an interesting little problem in an otherwise tedious
design.



-- 

John Larkin         Highland Technology, Inc

lunatic fringe electronics 

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#518573

Am 06.10.2018 um 19:33 schrieb John Larkin:
> 
> 
> A timestamper is a circuit that latches the time of arrival of a pulse
> edge. We use a clock and a binary counter as MC, the master counter
> definition of time. We extend those MC bits down into picoseconds with
> a time interpolator, adding 8 to 12 bits below the counter LSB.
> 
> One way to test a time stamper is to stamp pulses that are random in
> time, and then histogram/analyze the codes. That can catch all sorts
> of nasties, like stuck or shorted bits or interpolator problems; we've
> done the math on that. In the test set that I'm designing, I want a
> simple but really bad pulse generator, maybe around 1 MHz with tons of
> period jitter, to get good statistics and never alias against the
> master clock. Aliasing can make really weird histograms.
> 
> https://www.dropbox.com/s/vv6dqeffxrkmca3/Timestamp_Noisy_Osc.jpg?raw=1
> 
> The single inverting schmitt oscillator is probably good enough, but
> it's fun to consider other really nasty oscillators. A bad power
> supply will only help.
> 
> We have an FPGA, so I guess we could build a pseudorandom bit stream,
> filter that a little, and use that to confuse a schmitt oscillator.
> The kids might enjoy programming that.

I do not think that this is a really good idea. If your test signal
is REALLY noisy, it will dither away the contributions of your
interpolator / pulse stretcher. You get nice statistics, but for a
wrong reason.

The standard way to measure linearity of an interpolator is to have
two OCXOs that drift very slowly against each other, maybe 20 nsec
difference per hour. Then you know the value to be expected and you
have enough time to do statistics wrt single vs. 1000 times averaged.
Dynamic nonlinearity (arbitrary pulse width, cycle-to-cycle) can only
be worse than that.

And it is a task for itself to make sure that the 2 VCXOs
do not injection lock, even when they happen to be close.
We used our house reference (hydrogen maser based) and an offset generator.

I also had good results with a switchable Synergy CML delay line and
measured the resulting pulse width in parallel with a Stanford SR-620.
The SR620 is quite old by now (Z80..) but still there are no TICs that
are SIGNIFICANTLY better.

Back then, when men still were men and HP still was HP, they published
a description of the two-stage time stretcher of the HP54570A sampling
scope in HP journal. Still worth reading. All of HP journal.

cheers,
Gerhard

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#518576

Am 06.10.2018 um 21:28 schrieb Gerhard Hoffmann:
>
> Back then, when men still were men and HP still was HP, they published
> a description of the two-stage time stretcher of the HP54570A sampling
> scope in HP journal. Still worth reading. All of HP journal.

Ooohps, 54750A

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#518593

On Sat, 6 Oct 2018 21:28:18 +0200, Gerhard Hoffmann
<ghf@hoffmann-hochfrequenz.de> wrote:

>Am 06.10.2018 um 19:33 schrieb John Larkin:
>> 
>> 
>> A timestamper is a circuit that latches the time of arrival of a pulse
>> edge. We use a clock and a binary counter as MC, the master counter
>> definition of time. We extend those MC bits down into picoseconds with
>> a time interpolator, adding 8 to 12 bits below the counter LSB.
>> 
>> One way to test a time stamper is to stamp pulses that are random in
>> time, and then histogram/analyze the codes. That can catch all sorts
>> of nasties, like stuck or shorted bits or interpolator problems; we've
>> done the math on that. In the test set that I'm designing, I want a
>> simple but really bad pulse generator, maybe around 1 MHz with tons of
>> period jitter, to get good statistics and never alias against the
>> master clock. Aliasing can make really weird histograms.
>> 
>> https://www.dropbox.com/s/vv6dqeffxrkmca3/Timestamp_Noisy_Osc.jpg?raw=1
>> 
>> The single inverting schmitt oscillator is probably good enough, but
>> it's fun to consider other really nasty oscillators. A bad power
>> supply will only help.
>> 
>> We have an FPGA, so I guess we could build a pseudorandom bit stream,
>> filter that a little, and use that to confuse a schmitt oscillator.
>> The kids might enjoy programming that.
>
>I do not think that this is a really good idea. If your test signal
>is REALLY noisy, it will dither away the contributions of your
>interpolator / pulse stretcher. You get nice statistics, but for a
>wrong reason.
>
>The standard way to measure linearity of an interpolator is to have
>two OCXOs that drift very slowly against each other, maybe 20 nsec
>difference per hour. Then you know the value to be expected and you
>have enough time to do statistics wrt single vs. 1000 times averaged.
>Dynamic nonlinearity (arbitrary pulse width, cycle-to-cycle) can only
>be worse than that.
>
>And it is a task for itself to make sure that the 2 VCXOs
>do not injection lock, even when they happen to be close.
>We used our house reference (hydrogen maser based) and an offset generator.

The random pulse histogram thing works well and is fairly fast. It can
fine-tune the interpolator to a fraction of an LSB. And it's easy. I
just got interested in designing a cheap but
statistically-good-jitterey oscillator.

This will be a production test, so I don't have to prove that the
theory is right, just that every unit is built and calibrated
correctly. One or two spot delay measurements will supplement the
statistics thing.


-- 

John Larkin         Highland Technology, Inc

lunatic fringe electronics 

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#518602

On 10/06/2018 01:33 PM, John Larkin wrote:
> 
> 
> A timestamper is a circuit that latches the time of arrival of a pulse
> edge. We use a clock and a binary counter as MC, the master counter
> definition of time. We extend those MC bits down into picoseconds with
> a time interpolator, adding 8 to 12 bits below the counter LSB.
> 
> One way to test a time stamper is to stamp pulses that are random in
> time, and then histogram/analyze the codes. That can catch all sorts
> of nasties, like stuck or shorted bits or interpolator problems; we've
> done the math on that. In the test set that I'm designing, I want a
> simple but really bad pulse generator, maybe around 1 MHz with tons of
> period jitter, to get good statistics and never alias against the
> master clock. Aliasing can make really weird histograms.
> 
> https://www.dropbox.com/s/vv6dqeffxrkmca3/Timestamp_Noisy_Osc.jpg?raw=1
> 
> The single inverting schmitt oscillator is probably good enough, but
> it's fun to consider other really nasty oscillators. A bad power
> supply will only help.
> 
> We have an FPGA, so I guess we could build a pseudorandom bit stream,
> filter that a little, and use that to confuse a schmitt oscillator.
> The kids might enjoy programming that.
> 
> 

Chua's circuit is the textbook chaotic oscillator:

<https://en.wikipedia.org/wiki/Chua%27s_circuit>

Adding a single capacitor to the usual "blocking oscillator" can make a 
chaotic oscillator:

"The output signal of such chaotic oscillator is a series of short term 
pulses characterized by chaotic fluctuations of time intervals between 
pulses. Such chaotic pulse signals possess a broad-band continuous power 
spectrum and short correlation length."

(PDF) Generation of broad-band chaos using blocking oscillator. 
Available from: 
<https://www.researchgate.net/publication/3323718_Generation_of_broad-band_chaos_using_blocking_oscillator>

Two sheet-beam tube oscillators, each configured as self-oscillating 
singly-balanced mixers, cross coupled to each other would probably make 
a pretty crappy oscillator

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#518634

On Sat, 6 Oct 2018 21:59:11 -0400, bitrex <user@example.net> wrote:

>On 10/06/2018 01:33 PM, John Larkin wrote:
>> 
>> 
>> A timestamper is a circuit that latches the time of arrival of a pulse
>> edge. We use a clock and a binary counter as MC, the master counter
>> definition of time. We extend those MC bits down into picoseconds with
>> a time interpolator, adding 8 to 12 bits below the counter LSB.
>> 
>> One way to test a time stamper is to stamp pulses that are random in
>> time, and then histogram/analyze the codes. That can catch all sorts
>> of nasties, like stuck or shorted bits or interpolator problems; we've
>> done the math on that. In the test set that I'm designing, I want a
>> simple but really bad pulse generator, maybe around 1 MHz with tons of
>> period jitter, to get good statistics and never alias against the
>> master clock. Aliasing can make really weird histograms.
>> 
>> https://www.dropbox.com/s/vv6dqeffxrkmca3/Timestamp_Noisy_Osc.jpg?raw=1
>> 
>> The single inverting schmitt oscillator is probably good enough, but
>> it's fun to consider other really nasty oscillators. A bad power
>> supply will only help.
>> 
>> We have an FPGA, so I guess we could build a pseudorandom bit stream,
>> filter that a little, and use that to confuse a schmitt oscillator.
>> The kids might enjoy programming that.
>> 
>> 
>
>Chua's circuit is the textbook chaotic oscillator:
>
><https://en.wikipedia.org/wiki/Chua%27s_circuit>

It's chaotic but it still has strong periodicties, and would probably
alias against my clock.

>
>Adding a single capacitor to the usual "blocking oscillator" can make a 
>chaotic oscillator:
>
>"The output signal of such chaotic oscillator is a series of short term 
>pulses characterized by chaotic fluctuations of time intervals between 
>pulses. Such chaotic pulse signals possess a broad-band continuous power 
>spectrum and short correlation length."
>
>(PDF) Generation of broad-band chaos using blocking oscillator. 
>Available from: 
><https://www.researchgate.net/publication/3323718_Generation_of_broad-band_chaos_using_blocking_oscillator>
>

Right. A blocking oscilllator is like a super-regen receiver in that,
if the time constants are right, the period is dominated by noise. 

>Two sheet-beam tube oscillators, each configured as self-oscillating 
>singly-balanced mixers, cross coupled to each other would probably make 
>a pretty crappy oscillator

Again, in my application, I want the oscillator periods to be jitterey
at all time scales. I want "the spectrum of the jitter" to be
broadband so it doesn't correlate with any periodic clock.

I wish I knew more about the TPS54302 spread-spectrum mechanism. I'll
have one on my board, so that noise is free.

https://www.dropbox.com/s/s9aqx1z3glab423/TPS54302_PWM.JPG?raw=1







-- 

John Larkin         Highland Technology, Inc

lunatic fringe electronics 

[toc] | [prev] | [next] | [standalone]

#518676

On 10/07/2018 11:05 AM, John Larkin wrote:
> On Sat, 6 Oct 2018 21:59:11 -0400, bitrex <user@example.net> wrote:
> 
>> On 10/06/2018 01:33 PM, John Larkin wrote:
>>>
>>>
>>> A timestamper is a circuit that latches the time of arrival of a pulse
>>> edge. We use a clock and a binary counter as MC, the master counter
>>> definition of time. We extend those MC bits down into picoseconds with
>>> a time interpolator, adding 8 to 12 bits below the counter LSB.
>>>
>>> One way to test a time stamper is to stamp pulses that are random in
>>> time, and then histogram/analyze the codes. That can catch all sorts
>>> of nasties, like stuck or shorted bits or interpolator problems; we've
>>> done the math on that. In the test set that I'm designing, I want a
>>> simple but really bad pulse generator, maybe around 1 MHz with tons of
>>> period jitter, to get good statistics and never alias against the
>>> master clock. Aliasing can make really weird histograms.
>>>
>>> https://www.dropbox.com/s/vv6dqeffxrkmca3/Timestamp_Noisy_Osc.jpg?raw=1
>>>
>>> The single inverting schmitt oscillator is probably good enough, but
>>> it's fun to consider other really nasty oscillators. A bad power
>>> supply will only help.
>>>
>>> We have an FPGA, so I guess we could build a pseudorandom bit stream,
>>> filter that a little, and use that to confuse a schmitt oscillator.
>>> The kids might enjoy programming that.
>>>
>>>
>>
>> Chua's circuit is the textbook chaotic oscillator:
>>
>> <https://en.wikipedia.org/wiki/Chua%27s_circuit>
> 
> It's chaotic but it still has strong periodicties, and would probably
> alias against my clock.
> 
>>
>> Adding a single capacitor to the usual "blocking oscillator" can make a
>> chaotic oscillator:
>>
>> "The output signal of such chaotic oscillator is a series of short term
>> pulses characterized by chaotic fluctuations of time intervals between
>> pulses. Such chaotic pulse signals possess a broad-band continuous power
>> spectrum and short correlation length."
>>
>> (PDF) Generation of broad-band chaos using blocking oscillator.
>> Available from:
>> <https://www.researchgate.net/publication/3323718_Generation_of_broad-band_chaos_using_blocking_oscillator>
>>
> 
> Right. A blocking oscilllator is like a super-regen receiver in that,
> if the time constants are right, the period is dominated by noise.
> 
>> Two sheet-beam tube oscillators, each configured as self-oscillating
>> singly-balanced mixers, cross coupled to each other would probably make
>> a pretty crappy oscillator
> 
> Again, in my application, I want the oscillator periods to be jitterey
> at all time scales. I want "the spectrum of the jitter" to be
> broadband so it doesn't correlate with any periodic clock.

Why does the blocking osc pulse generator not fit that requirement? I'm 
not sure what "spectrum of the jitter" should be broadband means do you 
mean the process that generates the pulses should be ergodic?

<https://en.wikipedia.org/wiki/Ergodic_process>

> I wish I knew more about the TPS54302 spread-spectrum mechanism. I'll
> have one on my board, so that noise is free.
> 
> https://www.dropbox.com/s/s9aqx1z3glab423/TPS54302_PWM.JPG?raw=1
> 
> 

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#518682

On Sun, 7 Oct 2018 23:04:52 -0400, bitrex <user@example.net> wrote:

>On 10/07/2018 11:05 AM, John Larkin wrote:
>> On Sat, 6 Oct 2018 21:59:11 -0400, bitrex <user@example.net> wrote:
>> 
>>> On 10/06/2018 01:33 PM, John Larkin wrote:
>>>>
>>>>
>>>> A timestamper is a circuit that latches the time of arrival of a pulse
>>>> edge. We use a clock and a binary counter as MC, the master counter
>>>> definition of time. We extend those MC bits down into picoseconds with
>>>> a time interpolator, adding 8 to 12 bits below the counter LSB.
>>>>
>>>> One way to test a time stamper is to stamp pulses that are random in
>>>> time, and then histogram/analyze the codes. That can catch all sorts
>>>> of nasties, like stuck or shorted bits or interpolator problems; we've
>>>> done the math on that. In the test set that I'm designing, I want a
>>>> simple but really bad pulse generator, maybe around 1 MHz with tons of
>>>> period jitter, to get good statistics and never alias against the
>>>> master clock. Aliasing can make really weird histograms.
>>>>
>>>> https://www.dropbox.com/s/vv6dqeffxrkmca3/Timestamp_Noisy_Osc.jpg?raw=1
>>>>
>>>> The single inverting schmitt oscillator is probably good enough, but
>>>> it's fun to consider other really nasty oscillators. A bad power
>>>> supply will only help.
>>>>
>>>> We have an FPGA, so I guess we could build a pseudorandom bit stream,
>>>> filter that a little, and use that to confuse a schmitt oscillator.
>>>> The kids might enjoy programming that.
>>>>
>>>>
>>>
>>> Chua's circuit is the textbook chaotic oscillator:
>>>
>>> <https://en.wikipedia.org/wiki/Chua%27s_circuit>
>> 
>> It's chaotic but it still has strong periodicties, and would probably
>> alias against my clock.
>> 
>>>
>>> Adding a single capacitor to the usual "blocking oscillator" can make a
>>> chaotic oscillator:
>>>
>>> "The output signal of such chaotic oscillator is a series of short term
>>> pulses characterized by chaotic fluctuations of time intervals between
>>> pulses. Such chaotic pulse signals possess a broad-band continuous power
>>> spectrum and short correlation length."
>>>
>>> (PDF) Generation of broad-band chaos using blocking oscillator.
>>> Available from:
>>> <https://www.researchgate.net/publication/3323718_Generation_of_broad-band_chaos_using_blocking_oscillator>
>>>
>> 
>> Right. A blocking oscilllator is like a super-regen receiver in that,
>> if the time constants are right, the period is dominated by noise.
>> 
>>> Two sheet-beam tube oscillators, each configured as self-oscillating
>>> singly-balanced mixers, cross coupled to each other would probably make
>>> a pretty crappy oscillator
>> 
>> Again, in my application, I want the oscillator periods to be jitterey
>> at all time scales. I want "the spectrum of the jitter" to be
>> broadband so it doesn't correlate with any periodic clock.
>
>Why does the blocking osc pulse generator not fit that requirement? I'm 
>not sure what "spectrum of the jitter" should be broadband means do you 
>mean the process that generates the pulses should be ergodic?
>
><https://en.wikipedia.org/wiki/Ergodic_process>

We use to call that "stationary."

No, I want pulses whose period is random, without any periodicities.
That corresponds to a flat spectrum. Or if you histogram the periods,
that looks pretty flat. 

Possibly I could use a crystal oscillator that has some specific
frequency ratio to the clock in my DUT time stamper, some
relatively-prime thing I guess. But I'd have to be careful about
oscillator frequency tolerances, which might require too much
thinking.



>
>> I wish I knew more about the TPS54302 spread-spectrum mechanism. I'll
>> have one on my board, so that noise is free.
>> 
>> https://www.dropbox.com/s/s9aqx1z3glab423/TPS54302_PWM.JPG?raw=1
>> 
>> 

-- 

John Larkin         Highland Technology, Inc

lunatic fringe electronics 

[toc] | [prev] | [next] | [standalone]

#518677

On 10/07/2018 11:05 AM, John Larkin wrote:
> On Sat, 6 Oct 2018 21:59:11 -0400, bitrex <user@example.net> wrote:
> 
>> On 10/06/2018 01:33 PM, John Larkin wrote:
>>>
>>>
>>> A timestamper is a circuit that latches the time of arrival of a pulse
>>> edge. We use a clock and a binary counter as MC, the master counter
>>> definition of time. We extend those MC bits down into picoseconds with
>>> a time interpolator, adding 8 to 12 bits below the counter LSB.
>>>
>>> One way to test a time stamper is to stamp pulses that are random in
>>> time, and then histogram/analyze the codes. That can catch all sorts
>>> of nasties, like stuck or shorted bits or interpolator problems; we've
>>> done the math on that. In the test set that I'm designing, I want a
>>> simple but really bad pulse generator, maybe around 1 MHz with tons of
>>> period jitter, to get good statistics and never alias against the
>>> master clock. Aliasing can make really weird histograms.
>>>
>>> https://www.dropbox.com/s/vv6dqeffxrkmca3/Timestamp_Noisy_Osc.jpg?raw=1
>>>
>>> The single inverting schmitt oscillator is probably good enough, but
>>> it's fun to consider other really nasty oscillators. A bad power
>>> supply will only help.
>>>
>>> We have an FPGA, so I guess we could build a pseudorandom bit stream,
>>> filter that a little, and use that to confuse a schmitt oscillator.
>>> The kids might enjoy programming that.
>>>
>>>
>>
>> Chua's circuit is the textbook chaotic oscillator:
>>
>> <https://en.wikipedia.org/wiki/Chua%27s_circuit>
> 
> It's chaotic but it still has strong periodicties, and would probably
> alias against my clock.
> 
>>
>> Adding a single capacitor to the usual "blocking oscillator" can make a
>> chaotic oscillator:
>>
>> "The output signal of such chaotic oscillator is a series of short term
>> pulses characterized by chaotic fluctuations of time intervals between
>> pulses. Such chaotic pulse signals possess a broad-band continuous power
>> spectrum and short correlation length."
>>
>> (PDF) Generation of broad-band chaos using blocking oscillator.
>> Available from:
>> <https://www.researchgate.net/publication/3323718_Generation_of_broad-band_chaos_using_blocking_oscillator>
>>
> 
> Right. A blocking oscilllator is like a super-regen receiver in that,
> if the time constants are right, the period is dominated by noise.
> 
>> Two sheet-beam tube oscillators, each configured as self-oscillating
>> singly-balanced mixers, cross coupled to each other would probably make
>> a pretty crappy oscillator
> 
> Again, in my application, I want the oscillator periods to be jitterey
> at all time scales. I want "the spectrum of the jitter" to be
> broadband so it doesn't correlate with any periodic clock.
> 
> I wish I knew more about the TPS54302 spread-spectrum mechanism. I'll
> have one on my board, so that noise is free.
> 
> https://www.dropbox.com/s/s9aqx1z3glab423/TPS54302_PWM.JPG?raw=1

This gentlemen made a random-bit generator just from abusing the race 
conditions that can naturally occur in multi-core, multi-threaded 
processors where resource access is not properly synchronized between 
code in different threads of execution, kinda interesting!

<https://groups.google.com/forum/#!topic/comp.lang.c++/7u_rLgQe86k/discussion>

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