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Re: [PATCH v1 3/5] dt-bindings: Add DT bindings for NVIDIA Tegra AHB DMA controller

Started byDmitry Osipenko <digetx@gmail.com>
First post2017-09-27 04:00 +0200
Last post2017-10-02 22:50 +0200
Articles 11 — 4 participants

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  Re: [PATCH v1 3/5] dt-bindings: Add DT bindings for NVIDIA Tegra AHB  DMA controller Dmitry Osipenko <digetx@gmail.com> - 2017-09-27 04:00 +0200
    Re: [PATCH v1 3/5] dt-bindings: Add DT bindings for NVIDIA Tegra AHB  DMA controller Jon Hunter <jonathanh@nvidia.com> - 2017-09-27 10:40 +0200
      Re: [PATCH v1 3/5] dt-bindings: Add DT bindings for NVIDIA Tegra AHB  DMA controller Dmitry Osipenko <digetx@gmail.com> - 2017-09-27 14:20 +0200
        Re: [PATCH v1 3/5] dt-bindings: Add DT bindings for NVIDIA Tegra AHB  DMA controller Jon Hunter <jonathanh@nvidia.com> - 2017-09-27 15:50 +0200
          Re: [PATCH v1 3/5] dt-bindings: Add DT bindings for NVIDIA Tegra AHB  DMA controller Jon Hunter <jonathanh@nvidia.com> - 2017-09-27 15:50 +0200
            Re: [PATCH v1 3/5] dt-bindings: Add DT bindings for NVIDIA Tegra AHB  DMA controller Dmitry Osipenko <digetx@gmail.com> - 2017-09-27 16:30 +0200
      Re: [PATCH v1 3/5] dt-bindings: Add DT bindings for NVIDIA Tegra AHB  DMA controller Stephen Boyd <sboyd@codeaurora.org> - 2017-09-28 01:40 +0200
        Re: [PATCH v1 3/5] dt-bindings: Add DT bindings for NVIDIA Tegra AHB  DMA controller Jon Hunter <jonathanh@nvidia.com> - 2017-09-28 10:40 +0200
      Re: [PATCH v1 3/5] dt-bindings: Add DT bindings for NVIDIA Tegra AHB  DMA controller Stephen Warren <swarren@wwwdotorg.org> - 2017-09-29 21:40 +0200
        Re: [PATCH v1 3/5] dt-bindings: Add DT bindings for NVIDIA Tegra AHB  DMA controller Dmitry Osipenko <digetx@gmail.com> - 2017-09-30 05:20 +0200
          Re: [PATCH v1 3/5] dt-bindings: Add DT bindings for NVIDIA Tegra AHB  DMA controller Stephen Warren <swarren@wwwdotorg.org> - 2017-10-02 22:50 +0200

#1740343 — Re: [PATCH v1 3/5] dt-bindings: Add DT bindings for NVIDIA Tegra AHB DMA controller

FromDmitry Osipenko <digetx@gmail.com>
Date2017-09-27 04:00 +0200
SubjectRe: [PATCH v1 3/5] dt-bindings: Add DT bindings for NVIDIA Tegra AHB DMA controller
Message-ID<uu9NN-4b6-15@gated-at.bofh.it>
On 26.09.2017 17:50, Jon Hunter wrote:
> 
> On 26/09/17 00:22, Dmitry Osipenko wrote:
>> Document DT bindings for NVIDIA Tegra AHB DMA controller that presents
>> on Tegra20/30 SoC's.
>>
>> Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
>> ---
>>  .../bindings/dma/nvidia,tegra20-ahbdma.txt         | 23 ++++++++++++++++++++++
>>  1 file changed, 23 insertions(+)
>>  create mode 100644 Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt
>>
>> diff --git a/Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt b/Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt
>> new file mode 100644
>> index 000000000000..2af9aa76ae11
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt
>> @@ -0,0 +1,23 @@
>> +* NVIDIA Tegra AHB DMA controller
>> +
>> +Required properties:
>> +- compatible:	Must be "nvidia,tegra20-ahbdma"
>> +- reg:		Should contain registers base address and length.
>> +- interrupts:	Should contain one entry, DMA controller interrupt.
>> +- clocks:	Should contain one entry, DMA controller clock.
>> +- resets :	Should contain one entry, DMA controller reset.
>> +- #dma-cells:	Should be <1>. The cell represents DMA request select value
>> +		for the peripheral. For more details consult the Tegra TRM's
>> +		documentation, in particular AHB DMA channel control register
>> +		REQ_SEL field.
> 
> What about the TRIG_SEL field? Do we need to handle this here as well?
> 

Actually, DMA transfer trigger isn't related a hardware description. It's up to
software to decide what trigger to select. So it shouldn't be in the binding.

And I think the same applies to requester... any objections?

-- 
Dmitry

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#1740501

FromJon Hunter <jonathanh@nvidia.com>
Date2017-09-27 10:40 +0200
Message-ID<uug2S-8no-19@gated-at.bofh.it>
In reply to#1740343
On 27/09/17 02:57, Dmitry Osipenko wrote:
> On 26.09.2017 17:50, Jon Hunter wrote:
>>
>> On 26/09/17 00:22, Dmitry Osipenko wrote:
>>> Document DT bindings for NVIDIA Tegra AHB DMA controller that presents
>>> on Tegra20/30 SoC's.
>>>
>>> Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
>>> ---
>>>  .../bindings/dma/nvidia,tegra20-ahbdma.txt         | 23 ++++++++++++++++++++++
>>>  1 file changed, 23 insertions(+)
>>>  create mode 100644 Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt
>>>
>>> diff --git a/Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt b/Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt
>>> new file mode 100644
>>> index 000000000000..2af9aa76ae11
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt
>>> @@ -0,0 +1,23 @@
>>> +* NVIDIA Tegra AHB DMA controller
>>> +
>>> +Required properties:
>>> +- compatible:	Must be "nvidia,tegra20-ahbdma"
>>> +- reg:		Should contain registers base address and length.
>>> +- interrupts:	Should contain one entry, DMA controller interrupt.
>>> +- clocks:	Should contain one entry, DMA controller clock.
>>> +- resets :	Should contain one entry, DMA controller reset.
>>> +- #dma-cells:	Should be <1>. The cell represents DMA request select value
>>> +		for the peripheral. For more details consult the Tegra TRM's
>>> +		documentation, in particular AHB DMA channel control register
>>> +		REQ_SEL field.
>>
>> What about the TRIG_SEL field? Do we need to handle this here as well?
>>
> 
> Actually, DMA transfer trigger isn't related a hardware description. It's up to
> software to decide what trigger to select. So it shouldn't be in the binding.

I think it could be, if say a board wanted a GPIO to trigger a transfer.

> And I think the same applies to requester... any objections?

Well, the REQ_SEL should definitely be in the binding.

Laxman, Stephen, what are your thoughts on the TRIG_SEL field? Looks
like we never bothered with it for the APB DMA and so maybe no ones uses
this.

Cheers
Jon

-- 
nvpublic

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#1740663

FromDmitry Osipenko <digetx@gmail.com>
Date2017-09-27 14:20 +0200
Message-ID<uujtN-2gN-37@gated-at.bofh.it>
In reply to#1740501
On 27.09.2017 11:34, Jon Hunter wrote:
> 
> On 27/09/17 02:57, Dmitry Osipenko wrote:
>> On 26.09.2017 17:50, Jon Hunter wrote:
>>>
>>> On 26/09/17 00:22, Dmitry Osipenko wrote:
>>>> Document DT bindings for NVIDIA Tegra AHB DMA controller that presents
>>>> on Tegra20/30 SoC's.
>>>>
>>>> Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
>>>> ---
>>>>  .../bindings/dma/nvidia,tegra20-ahbdma.txt         | 23 ++++++++++++++++++++++
>>>>  1 file changed, 23 insertions(+)
>>>>  create mode 100644 Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt b/Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt
>>>> new file mode 100644
>>>> index 000000000000..2af9aa76ae11
>>>> --- /dev/null
>>>> +++ b/Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt
>>>> @@ -0,0 +1,23 @@
>>>> +* NVIDIA Tegra AHB DMA controller
>>>> +
>>>> +Required properties:
>>>> +- compatible:	Must be "nvidia,tegra20-ahbdma"
>>>> +- reg:		Should contain registers base address and length.
>>>> +- interrupts:	Should contain one entry, DMA controller interrupt.
>>>> +- clocks:	Should contain one entry, DMA controller clock.
>>>> +- resets :	Should contain one entry, DMA controller reset.
>>>> +- #dma-cells:	Should be <1>. The cell represents DMA request select value
>>>> +		for the peripheral. For more details consult the Tegra TRM's
>>>> +		documentation, in particular AHB DMA channel control register
>>>> +		REQ_SEL field.
>>>
>>> What about the TRIG_SEL field? Do we need to handle this here as well?
>>>
>>
>> Actually, DMA transfer trigger isn't related a hardware description. It's up to
>> software to decide what trigger to select. So it shouldn't be in the binding.
> 
> I think it could be, if say a board wanted a GPIO to trigger a transfer.
> 

GPIO isn't a very good example, there is no "GPIO" trigger. To me all triggers
are software-defined, so that software could create transfer chains.

>> And I think the same applies to requester... any objections?
> 
> Well, the REQ_SEL should definitely be in the binding.
> 

Okay.

> Laxman, Stephen, what are your thoughts on the TRIG_SEL field? Looks
> like we never bothered with it for the APB DMA and so maybe no ones uses
> this.
> 

-- 
Dmitry

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#1740734

FromJon Hunter <jonathanh@nvidia.com>
Date2017-09-27 15:50 +0200
Message-ID<uukSR-3A0-1@gated-at.bofh.it>
In reply to#1740663
On 27/09/17 13:12, Dmitry Osipenko wrote:
> On 27.09.2017 11:34, Jon Hunter wrote:
>>
>> On 27/09/17 02:57, Dmitry Osipenko wrote:
>>> On 26.09.2017 17:50, Jon Hunter wrote:
>>>>
>>>> On 26/09/17 00:22, Dmitry Osipenko wrote:
>>>>> Document DT bindings for NVIDIA Tegra AHB DMA controller that presents
>>>>> on Tegra20/30 SoC's.
>>>>>
>>>>> Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
>>>>> ---
>>>>>  .../bindings/dma/nvidia,tegra20-ahbdma.txt         | 23 ++++++++++++++++++++++
>>>>>  1 file changed, 23 insertions(+)
>>>>>  create mode 100644 Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt
>>>>>
>>>>> diff --git a/Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt b/Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt
>>>>> new file mode 100644
>>>>> index 000000000000..2af9aa76ae11
>>>>> --- /dev/null
>>>>> +++ b/Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt
>>>>> @@ -0,0 +1,23 @@
>>>>> +* NVIDIA Tegra AHB DMA controller
>>>>> +
>>>>> +Required properties:
>>>>> +- compatible:	Must be "nvidia,tegra20-ahbdma"
>>>>> +- reg:		Should contain registers base address and length.
>>>>> +- interrupts:	Should contain one entry, DMA controller interrupt.
>>>>> +- clocks:	Should contain one entry, DMA controller clock.
>>>>> +- resets :	Should contain one entry, DMA controller reset.
>>>>> +- #dma-cells:	Should be <1>. The cell represents DMA request select value
>>>>> +		for the peripheral. For more details consult the Tegra TRM's
>>>>> +		documentation, in particular AHB DMA channel control register
>>>>> +		REQ_SEL field.
>>>>
>>>> What about the TRIG_SEL field? Do we need to handle this here as well?
>>>>
>>>
>>> Actually, DMA transfer trigger isn't related a hardware description. It's up to
>>> software to decide what trigger to select. So it shouldn't be in the binding.
>>
>> I think it could be, if say a board wanted a GPIO to trigger a transfer.
>>
> 
> GPIO isn't a very good example, there is no "GPIO" trigger. To me all triggers
> are software-defined, so that software could create transfer chains.

TRM shows the following in the APBDMA_TRIG_REG_0 ...

"XRQ_A: XRQ.A (GPIOA) (Hardware initiated DMA request)"

Jon

-- 
nvpublic

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#1740740

FromJon Hunter <jonathanh@nvidia.com>
Date2017-09-27 15:50 +0200
Message-ID<uukSS-3A0-21@gated-at.bofh.it>
In reply to#1740734
On 27/09/17 14:44, Jon Hunter wrote:
> 
> On 27/09/17 13:12, Dmitry Osipenko wrote:
>> On 27.09.2017 11:34, Jon Hunter wrote:
>>>
>>> On 27/09/17 02:57, Dmitry Osipenko wrote:
>>>> On 26.09.2017 17:50, Jon Hunter wrote:
>>>>>
>>>>> On 26/09/17 00:22, Dmitry Osipenko wrote:
>>>>>> Document DT bindings for NVIDIA Tegra AHB DMA controller that presents
>>>>>> on Tegra20/30 SoC's.
>>>>>>
>>>>>> Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
>>>>>> ---
>>>>>>  .../bindings/dma/nvidia,tegra20-ahbdma.txt         | 23 ++++++++++++++++++++++
>>>>>>  1 file changed, 23 insertions(+)
>>>>>>  create mode 100644 Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt
>>>>>>
>>>>>> diff --git a/Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt b/Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt
>>>>>> new file mode 100644
>>>>>> index 000000000000..2af9aa76ae11
>>>>>> --- /dev/null
>>>>>> +++ b/Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt
>>>>>> @@ -0,0 +1,23 @@
>>>>>> +* NVIDIA Tegra AHB DMA controller
>>>>>> +
>>>>>> +Required properties:
>>>>>> +- compatible:	Must be "nvidia,tegra20-ahbdma"
>>>>>> +- reg:		Should contain registers base address and length.
>>>>>> +- interrupts:	Should contain one entry, DMA controller interrupt.
>>>>>> +- clocks:	Should contain one entry, DMA controller clock.
>>>>>> +- resets :	Should contain one entry, DMA controller reset.
>>>>>> +- #dma-cells:	Should be <1>. The cell represents DMA request select value
>>>>>> +		for the peripheral. For more details consult the Tegra TRM's
>>>>>> +		documentation, in particular AHB DMA channel control register
>>>>>> +		REQ_SEL field.
>>>>>
>>>>> What about the TRIG_SEL field? Do we need to handle this here as well?
>>>>>
>>>>
>>>> Actually, DMA transfer trigger isn't related a hardware description. It's up to
>>>> software to decide what trigger to select. So it shouldn't be in the binding.
>>>
>>> I think it could be, if say a board wanted a GPIO to trigger a transfer.
>>>
>>
>> GPIO isn't a very good example, there is no "GPIO" trigger. To me all triggers
>> are software-defined, so that software could create transfer chains.
> 
> TRM shows the following in the APBDMA_TRIG_REG_0 ...
> 
> "XRQ_A: XRQ.A (GPIOA) (Hardware initiated DMA request)"

Furthermore there are timer and hw-semaphore triggers as well.

Jon

-- 
nvpublic

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#1740781

FromDmitry Osipenko <digetx@gmail.com>
Date2017-09-27 16:30 +0200
Message-ID<uulvz-4kL-11@gated-at.bofh.it>
In reply to#1740740
On 27.09.2017 16:46, Jon Hunter wrote:
> 
> On 27/09/17 14:44, Jon Hunter wrote:
>>
>> On 27/09/17 13:12, Dmitry Osipenko wrote:
>>> On 27.09.2017 11:34, Jon Hunter wrote:
>>>>
>>>> On 27/09/17 02:57, Dmitry Osipenko wrote:
>>>>> On 26.09.2017 17:50, Jon Hunter wrote:
>>>>>>
>>>>>> On 26/09/17 00:22, Dmitry Osipenko wrote:
>>>>>>> Document DT bindings for NVIDIA Tegra AHB DMA controller that presents
>>>>>>> on Tegra20/30 SoC's.
>>>>>>>
>>>>>>> Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
>>>>>>> ---
>>>>>>>  .../bindings/dma/nvidia,tegra20-ahbdma.txt         | 23 ++++++++++++++++++++++
>>>>>>>  1 file changed, 23 insertions(+)
>>>>>>>  create mode 100644 Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt
>>>>>>>
>>>>>>> diff --git a/Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt b/Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt
>>>>>>> new file mode 100644
>>>>>>> index 000000000000..2af9aa76ae11
>>>>>>> --- /dev/null
>>>>>>> +++ b/Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt
>>>>>>> @@ -0,0 +1,23 @@
>>>>>>> +* NVIDIA Tegra AHB DMA controller
>>>>>>> +
>>>>>>> +Required properties:
>>>>>>> +- compatible:	Must be "nvidia,tegra20-ahbdma"
>>>>>>> +- reg:		Should contain registers base address and length.
>>>>>>> +- interrupts:	Should contain one entry, DMA controller interrupt.
>>>>>>> +- clocks:	Should contain one entry, DMA controller clock.
>>>>>>> +- resets :	Should contain one entry, DMA controller reset.
>>>>>>> +- #dma-cells:	Should be <1>. The cell represents DMA request select value
>>>>>>> +		for the peripheral. For more details consult the Tegra TRM's
>>>>>>> +		documentation, in particular AHB DMA channel control register
>>>>>>> +		REQ_SEL field.
>>>>>>
>>>>>> What about the TRIG_SEL field? Do we need to handle this here as well?
>>>>>>
>>>>>
>>>>> Actually, DMA transfer trigger isn't related a hardware description. It's up to
>>>>> software to decide what trigger to select. So it shouldn't be in the binding.
>>>>
>>>> I think it could be, if say a board wanted a GPIO to trigger a transfer.
>>>>
>>>
>>> GPIO isn't a very good example, there is no "GPIO" trigger. To me all triggers
>>> are software-defined, so that software could create transfer chains.
>>
>> TRM shows the following in the APBDMA_TRIG_REG_0 ...
>>
>> "XRQ_A: XRQ.A (GPIOA) (Hardware initiated DMA request)"
> 
> Furthermore there are timer and hw-semaphore triggers as well.
> 

Aha, I wasn't sure about what XRQ is. AHB DMA doesn't have XRQ.A as a trigger,
but XRQ.C/D which I suppose corresponds to GPIO C/D.

Timer and hw-semaphore are more questionable, aren't semaphores software-only
triggerable?

-- 
Dmitry

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#1741095

FromStephen Boyd <sboyd@codeaurora.org>
Date2017-09-28 01:40 +0200
Message-ID<uuu5P-1aK-1@gated-at.bofh.it>
In reply to#1740501
On 09/27, Jon Hunter wrote:
> 
> 
> Well, the REQ_SEL should definitely be in the binding.
> 
> Laxman, Stephen, what are your thoughts on the TRIG_SEL field? Looks

Wrong Stephen?

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

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#1741289

FromJon Hunter <jonathanh@nvidia.com>
Date2017-09-28 10:40 +0200
Message-ID<uuCwr-6Fg-29@gated-at.bofh.it>
In reply to#1741095

On 28/09/17 00:32, Stephen Boyd wrote:
> On 09/27, Jon Hunter wrote:
>>
>>
>> Well, the REQ_SEL should definitely be in the binding.
>>
>> Laxman, Stephen, what are your thoughts on the TRIG_SEL field? Looks
> 
> Wrong Stephen?

Indeed! With all the folks in copy, I assumed we had the right one :-)

Cheers
Jon

-- 
nvpublic

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#1742305

FromStephen Warren <swarren@wwwdotorg.org>
Date2017-09-29 21:40 +0200
Message-ID<uv9iF-20d-3@gated-at.bofh.it>
In reply to#1740501
On 09/27/2017 02:34 AM, Jon Hunter wrote:
> 
> On 27/09/17 02:57, Dmitry Osipenko wrote:
>> On 26.09.2017 17:50, Jon Hunter wrote:
>>>
>>> On 26/09/17 00:22, Dmitry Osipenko wrote:
>>>> Document DT bindings for NVIDIA Tegra AHB DMA controller that presents
>>>> on Tegra20/30 SoC's.
>>>>
>>>> Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
>>>> ---
>>>>   .../bindings/dma/nvidia,tegra20-ahbdma.txt         | 23 ++++++++++++++++++++++
>>>>   1 file changed, 23 insertions(+)
>>>>   create mode 100644 Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt b/Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt
>>>> new file mode 100644
>>>> index 000000000000..2af9aa76ae11
>>>> --- /dev/null
>>>> +++ b/Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt
>>>> @@ -0,0 +1,23 @@
>>>> +* NVIDIA Tegra AHB DMA controller
>>>> +
>>>> +Required properties:
>>>> +- compatible:	Must be "nvidia,tegra20-ahbdma"
>>>> +- reg:		Should contain registers base address and length.
>>>> +- interrupts:	Should contain one entry, DMA controller interrupt.
>>>> +- clocks:	Should contain one entry, DMA controller clock.
>>>> +- resets :	Should contain one entry, DMA controller reset.
>>>> +- #dma-cells:	Should be <1>. The cell represents DMA request select value
>>>> +		for the peripheral. For more details consult the Tegra TRM's
>>>> +		documentation, in particular AHB DMA channel control register
>>>> +		REQ_SEL field.
>>>
>>> What about the TRIG_SEL field? Do we need to handle this here as well?
>>>
>>
>> Actually, DMA transfer trigger isn't related a hardware description. It's up to
>> software to decide what trigger to select. So it shouldn't be in the binding.
> 
> I think it could be, if say a board wanted a GPIO to trigger a transfer.
> 
>> And I think the same applies to requester... any objections?
> 
> Well, the REQ_SEL should definitely be in the binding.
> 
> Laxman, Stephen, what are your thoughts on the TRIG_SEL field? Looks
> like we never bothered with it for the APB DMA and so maybe no ones uses
> this.

I don't think TRIG_SEL should be in the binding, at least at present. 
While TRIG_SEL certainly is something used to configure the transfer, I 
believe the semantics of the current DMA binding only cover DMA 
transfers that are initiated when SW desires, rather than being a 
combination of after SW programs the transfer plus some other HW event. 
So, we always use a default/hard-coded TRIG_SEL value. As such, there's 
no need for a TRIG_SEL value in DT. There's certainly no known use-case 
that requires a non-default TRIG_SEL value at present. We could add an 
extra #dma-cells value later if we find a use for it, and the semantics 
of that use-case make sense to add it to the DMA specifier, rather than 
some other separate higher-level property/driver/...

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#1742468

FromDmitry Osipenko <digetx@gmail.com>
Date2017-09-30 05:20 +0200
Message-ID<uvgtP-6XF-1@gated-at.bofh.it>
In reply to#1742305
On 29.09.2017 22:30, Stephen Warren wrote:
> On 09/27/2017 02:34 AM, Jon Hunter wrote:
>>
>> On 27/09/17 02:57, Dmitry Osipenko wrote:
>>> On 26.09.2017 17:50, Jon Hunter wrote:
>>>>
>>>> On 26/09/17 00:22, Dmitry Osipenko wrote:
>>>>> Document DT bindings for NVIDIA Tegra AHB DMA controller that presents
>>>>> on Tegra20/30 SoC's.
>>>>>
>>>>> Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
>>>>> ---
>>>>>   .../bindings/dma/nvidia,tegra20-ahbdma.txt         | 23
>>>>> ++++++++++++++++++++++
>>>>>   1 file changed, 23 insertions(+)
>>>>>   create mode 100644
>>>>> Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt
>>>>>
>>>>> diff --git
>>>>> a/Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt
>>>>> b/Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt
>>>>> new file mode 100644
>>>>> index 000000000000..2af9aa76ae11
>>>>> --- /dev/null
>>>>> +++ b/Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt
>>>>> @@ -0,0 +1,23 @@
>>>>> +* NVIDIA Tegra AHB DMA controller
>>>>> +
>>>>> +Required properties:
>>>>> +- compatible:    Must be "nvidia,tegra20-ahbdma"
>>>>> +- reg:        Should contain registers base address and length.
>>>>> +- interrupts:    Should contain one entry, DMA controller interrupt.
>>>>> +- clocks:    Should contain one entry, DMA controller clock.
>>>>> +- resets :    Should contain one entry, DMA controller reset.
>>>>> +- #dma-cells:    Should be <1>. The cell represents DMA request select value
>>>>> +        for the peripheral. For more details consult the Tegra TRM's
>>>>> +        documentation, in particular AHB DMA channel control register
>>>>> +        REQ_SEL field.
>>>>
>>>> What about the TRIG_SEL field? Do we need to handle this here as well?
>>>>
>>>
>>> Actually, DMA transfer trigger isn't related a hardware description. It's up to
>>> software to decide what trigger to select. So it shouldn't be in the binding.
>>
>> I think it could be, if say a board wanted a GPIO to trigger a transfer.
>>
>>> And I think the same applies to requester... any objections?
>>
>> Well, the REQ_SEL should definitely be in the binding.
>>
>> Laxman, Stephen, what are your thoughts on the TRIG_SEL field? Looks
>> like we never bothered with it for the APB DMA and so maybe no ones uses
>> this.
> 
> I don't think TRIG_SEL should be in the binding, at least at present. While
> TRIG_SEL certainly is something used to configure the transfer, I believe the
> semantics of the current DMA binding only cover DMA transfers that are initiated
> when SW desires, rather than being a combination of after SW programs the
> transfer plus some other HW event. So, we always use a default/hard-coded
> TRIG_SEL value. As such, there's no need for a TRIG_SEL value in DT. There's
> certainly no known use-case that requires a non-default TRIG_SEL value at
> present. We could add an extra #dma-cells value later if we find a use for it,
> and the semantics of that use-case make sense to add it to the DMA specifier,
> rather than some other separate higher-level property/driver/...

Thank you for the comment. If we'd want to extend the binding further with the
trigger, how to differentiate trigger from the requester in a case of a single
#data-cell?

Of course realistically a chance that the further extension would be needed is
very-very low, so we may defer the efforts to solve that question and for now
make driver aware of the potential #dma-cells extension.

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#1743280

FromStephen Warren <swarren@wwwdotorg.org>
Date2017-10-02 22:50 +0200
Message-ID<uwfPc-ur-167@gated-at.bofh.it>
In reply to#1742468
On 09/29/2017 09:11 PM, Dmitry Osipenko wrote:
> On 29.09.2017 22:30, Stephen Warren wrote:
>> On 09/27/2017 02:34 AM, Jon Hunter wrote:
>>>
>>> On 27/09/17 02:57, Dmitry Osipenko wrote:
>>>> On 26.09.2017 17:50, Jon Hunter wrote:
>>>>>
>>>>> On 26/09/17 00:22, Dmitry Osipenko wrote:
>>>>>> Document DT bindings for NVIDIA Tegra AHB DMA controller that presents
>>>>>> on Tegra20/30 SoC's.
>>>>>>
>>>>>> Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
>>>>>> ---
>>>>>>    .../bindings/dma/nvidia,tegra20-ahbdma.txt         | 23
>>>>>> ++++++++++++++++++++++
>>>>>>    1 file changed, 23 insertions(+)
>>>>>>    create mode 100644
>>>>>> Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt
>>>>>>
>>>>>> diff --git
>>>>>> a/Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt
>>>>>> b/Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt
>>>>>> new file mode 100644
>>>>>> index 000000000000..2af9aa76ae11
>>>>>> --- /dev/null
>>>>>> +++ b/Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt
>>>>>> @@ -0,0 +1,23 @@
>>>>>> +* NVIDIA Tegra AHB DMA controller
>>>>>> +
>>>>>> +Required properties:
>>>>>> +- compatible:    Must be "nvidia,tegra20-ahbdma"
>>>>>> +- reg:        Should contain registers base address and length.
>>>>>> +- interrupts:    Should contain one entry, DMA controller interrupt.
>>>>>> +- clocks:    Should contain one entry, DMA controller clock.
>>>>>> +- resets :    Should contain one entry, DMA controller reset.
>>>>>> +- #dma-cells:    Should be <1>. The cell represents DMA request select value
>>>>>> +        for the peripheral. For more details consult the Tegra TRM's
>>>>>> +        documentation, in particular AHB DMA channel control register
>>>>>> +        REQ_SEL field.
>>>>>
>>>>> What about the TRIG_SEL field? Do we need to handle this here as well?
>>>>>
>>>>
>>>> Actually, DMA transfer trigger isn't related a hardware description. It's up to
>>>> software to decide what trigger to select. So it shouldn't be in the binding.
>>>
>>> I think it could be, if say a board wanted a GPIO to trigger a transfer.
>>>
>>>> And I think the same applies to requester... any objections?
>>>
>>> Well, the REQ_SEL should definitely be in the binding.
>>>
>>> Laxman, Stephen, what are your thoughts on the TRIG_SEL field? Looks
>>> like we never bothered with it for the APB DMA and so maybe no ones uses
>>> this.
>>
>> I don't think TRIG_SEL should be in the binding, at least at present. While
>> TRIG_SEL certainly is something used to configure the transfer, I believe the
>> semantics of the current DMA binding only cover DMA transfers that are initiated
>> when SW desires, rather than being a combination of after SW programs the
>> transfer plus some other HW event. So, we always use a default/hard-coded
>> TRIG_SEL value. As such, there's no need for a TRIG_SEL value in DT. There's
>> certainly no known use-case that requires a non-default TRIG_SEL value at
>> present. We could add an extra #dma-cells value later if we find a use for it,
>> and the semantics of that use-case make sense to add it to the DMA specifier,
>> rather than some other separate higher-level property/driver/...
> 
> Thank you for the comment. If we'd want to extend the binding further with the
> trigger, how to differentiate trigger from the requester in a case of a single
> #data-cell?
> 
> Of course realistically a chance that the further extension would be needed is
> very-very low, so we may defer the efforts to solve that question and for now
> make driver aware of the potential #dma-cells extension.

The request selector cell isn't optional, so is always present. If we 
later add an optional trig_sel cell, we'll either have:

#dma-cells=<1>: req_sel

or:

#dma-cells=<2>: req_sel, trig_sel

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