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Groups > linux.kernel > #1731332 > unrolled thread
| Started by | Masahiro Yamada <yamada.masahiro@socionext.com> |
|---|---|
| First post | 2017-09-13 04:10 +0200 |
| Last post | 2017-09-22 12:10 +0200 |
| Articles | 3 — 2 participants |
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[PATCH v2 0/2] mtd: nand: introduce NAND_ROW_ADDR_3 flag and improve Denali driver Masahiro Yamada <yamada.masahiro@socionext.com> - 2017-09-13 04:10 +0200
[PATCH v2 2/2] mtd: nand: denali: support two row address cycle devices Masahiro Yamada <yamada.masahiro@socionext.com> - 2017-09-13 04:10 +0200
Re: [PATCH v2 0/2] mtd: nand: introduce NAND_ROW_ADDR_3 flag and improve Denali driver Boris Brezillon <boris.brezillon@free-electrons.com> - 2017-09-22 12:10 +0200
| From | Masahiro Yamada <yamada.masahiro@socionext.com> |
|---|---|
| Date | 2017-09-13 04:10 +0200 |
| Subject | [PATCH v2 0/2] mtd: nand: introduce NAND_ROW_ADDR_3 flag and improve Denali driver |
| Message-ID | <up5hM-16U-7@gated-at.bofh.it> |
Currently, Denali NAND driver always expects 3 row address cycle devices because the driver init code hard-code the register setting. I will fix it in 2/2. Many drivers check chip->chipsize if the third row address cycle is needed or not. This is not nice because 32MB, 128MB are magic numbers. nand_scan_ident can decide it and provide a driver-friendly flag. 1/2 is touching verious drivers. I hope Acked-by from driver maintainers if this change looks good. Changes in v2: - Fix build error Masahiro Yamada (2): mtd: nand: introduce NAND_ROW_ADDR_3 flag mtd: nand: denali: support two row address cycle devices drivers/mtd/nand/atmel/nand-controller.c | 3 +-- drivers/mtd/nand/au1550nd.c | 3 +-- drivers/mtd/nand/denali.c | 4 ++-- drivers/mtd/nand/diskonchip.c | 3 +-- drivers/mtd/nand/hisi504_nand.c | 3 +-- drivers/mtd/nand/mxc_nand.c | 3 +-- drivers/mtd/nand/nand_base.c | 9 +++++---- drivers/mtd/nand/nuc900_nand.c | 2 +- include/linux/mtd/rawnand.h | 3 +++ 9 files changed, 16 insertions(+), 17 deletions(-) -- 2.7.4
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| From | Masahiro Yamada <yamada.masahiro@socionext.com> |
|---|---|
| Date | 2017-09-13 04:10 +0200 |
| Subject | [PATCH v2 2/2] mtd: nand: denali: support two row address cycle devices |
| Message-ID | <up5hM-16U-9@gated-at.bofh.it> |
| In reply to | #1731332 |
The register TWO_ROW_ADDR_CYCLES specifies the number of row address cycles of the device, but it is fixed to 0 in the driver init code (i.e. always 3 row address cycles). Reflect the result of nand_scan_ident() to the register setting in order to support 2 row address cycle devices. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> --- Changes in v2: None drivers/mtd/nand/denali.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/nand/denali.c b/drivers/mtd/nand/denali.c index 3087b0b..aefdc83 100644 --- a/drivers/mtd/nand/denali.c +++ b/drivers/mtd/nand/denali.c @@ -1137,8 +1137,6 @@ static void denali_hw_init(struct denali_nand_info *denali) iowrite32(0xffff, denali->reg + SPARE_AREA_MARKER); - /* Should set value for these registers when init */ - iowrite32(0, denali->reg + TWO_ROW_ADDR_CYCLES); iowrite32(1, denali->reg + ECC_ENABLE); } @@ -1379,6 +1377,8 @@ int denali_init(struct denali_nand_info *denali) denali->reg + PAGES_PER_BLOCK); iowrite32(chip->options & NAND_BUSWIDTH_16 ? 1 : 0, denali->reg + DEVICE_WIDTH); + iowrite32(chip->options & NAND_ROW_ADDR_3 ? 0 : TWO_ROW_ADDR_CYCLES__FLAG, + denali->reg + TWO_ROW_ADDR_CYCLES); iowrite32(mtd->writesize, denali->reg + DEVICE_MAIN_AREA_SIZE); iowrite32(mtd->oobsize, denali->reg + DEVICE_SPARE_AREA_SIZE); -- 2.7.4
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| From | Boris Brezillon <boris.brezillon@free-electrons.com> |
|---|---|
| Date | 2017-09-22 12:10 +0200 |
| Subject | Re: [PATCH v2 0/2] mtd: nand: introduce NAND_ROW_ADDR_3 flag and improve Denali driver |
| Message-ID | <ust4f-4Qp-43@gated-at.bofh.it> |
| In reply to | #1731332 |
On Wed, 13 Sep 2017 11:05:49 +0900 Masahiro Yamada <yamada.masahiro@socionext.com> wrote: > Currently, Denali NAND driver always expects 3 row address cycle > devices because the driver init code hard-code the register setting. > I will fix it in 2/2. > > Many drivers check chip->chipsize if the third row address cycle > is needed or not. This is not nice because 32MB, 128MB are > magic numbers. nand_scan_ident can decide it and provide a > driver-friendly flag. > > 1/2 is touching verious drivers. > I hope Acked-by from driver maintainers if this change looks good. > Applied. Thanks, Boris > > Changes in v2: > - Fix build error > > Masahiro Yamada (2): > mtd: nand: introduce NAND_ROW_ADDR_3 flag > mtd: nand: denali: support two row address cycle devices > > drivers/mtd/nand/atmel/nand-controller.c | 3 +-- > drivers/mtd/nand/au1550nd.c | 3 +-- > drivers/mtd/nand/denali.c | 4 ++-- > drivers/mtd/nand/diskonchip.c | 3 +-- > drivers/mtd/nand/hisi504_nand.c | 3 +-- > drivers/mtd/nand/mxc_nand.c | 3 +-- > drivers/mtd/nand/nand_base.c | 9 +++++---- > drivers/mtd/nand/nuc900_nand.c | 2 +- > include/linux/mtd/rawnand.h | 3 +++ > 9 files changed, 16 insertions(+), 17 deletions(-) >
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