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Re: [PATCH v2 0/2] mtd: nand: introduce NAND_ROW_ADDR_3 flag and improve Denali driver

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On Wed, 13 Sep 2017 11:05:49 +0900
Masahiro Yamada <yamada.masahiro@socionext.com> wrote:

> Currently, Denali NAND driver always expects 3 row address cycle
> devices because the driver init code hard-code the register setting.
> I will fix it in 2/2.
> 
> Many drivers check chip->chipsize if the third row address cycle
> is needed or not.  This is not nice because 32MB, 128MB are
> magic numbers.  nand_scan_ident can decide it and provide a
> driver-friendly flag.
> 
> 1/2 is touching verious drivers.
> I hope Acked-by from driver maintainers if this change looks good.
> 

Applied.

Thanks,

Boris

> 
> Changes in v2:
>  - Fix build error
> 
> Masahiro Yamada (2):
>   mtd: nand: introduce NAND_ROW_ADDR_3 flag
>   mtd: nand: denali: support two row address cycle devices
> 
>  drivers/mtd/nand/atmel/nand-controller.c | 3 +--
>  drivers/mtd/nand/au1550nd.c              | 3 +--
>  drivers/mtd/nand/denali.c                | 4 ++--
>  drivers/mtd/nand/diskonchip.c            | 3 +--
>  drivers/mtd/nand/hisi504_nand.c          | 3 +--
>  drivers/mtd/nand/mxc_nand.c              | 3 +--
>  drivers/mtd/nand/nand_base.c             | 9 +++++----
>  drivers/mtd/nand/nuc900_nand.c           | 2 +-
>  include/linux/mtd/rawnand.h              | 3 +++
>  9 files changed, 16 insertions(+), 17 deletions(-)
> 

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[PATCH v2 0/2] mtd: nand: introduce NAND_ROW_ADDR_3 flag and improve Denali driver Masahiro Yamada <yamada.masahiro@socionext.com> - 2017-09-13 04:10 +0200
  [PATCH v2 2/2] mtd: nand: denali: support two row address cycle devices Masahiro Yamada <yamada.masahiro@socionext.com> - 2017-09-13 04:10 +0200
  Re: [PATCH v2 0/2] mtd: nand: introduce NAND_ROW_ADDR_3 flag and  improve Denali driver Boris Brezillon <boris.brezillon@free-electrons.com> - 2017-09-22 12:10 +0200

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