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[PATCH 0/6] Host1x and VIC support for Tegra186

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  [PATCH 0/6] Host1x and VIC support for Tegra186 Mikko Perttunen <mperttunen@nvidia.com> - 2017-08-17 21:00 +0200
    [PATCH 4/6] dt-bindings: host1x: Fix and add Tegra186 information Mikko Perttunen <mperttunen@nvidia.com> - 2017-08-17 21:00 +0200
      Re: [PATCH 4/6] dt-bindings: host1x: Fix and add Tegra186 information Rob Herring <robh@kernel.org> - 2017-08-22 04:40 +0200
    Re: [PATCH 5/6] gpu: host1x: Add Tegra186 support Dmitry Osipenko <digetx@gmail.com> - 2017-08-18 00:20 +0200

#1714299 — [PATCH 0/6] Host1x and VIC support for Tegra186

Hi everyone,

this series adds basic support for the Host1x channel engine and the
VIC 2d compositor unit on Tegra186. The first three patches do the
required device tree changes, the fourth patch updates the device tree
binding documentation, and the two remaining patches add the actual
implementation, almost all of which is in Host1x itself.

The Tegra186 Host1x is a relatively large update over previous
generations, which can be seen in the diffstat. The biggest change is
that Host1x is now contains separate hypervisor and vm register
apertures to support virtualization at the hardware level. This driver,
however, currently assumes that this instance of Linux is the sole
operating system having access to the hardware.

This combined with increased numbers of supported channels and
syncpoints have caused a number of register space changes that are
responsible for most of the updated code.

The series has been tested on the Jetson TX1 (T210) and TX2 (T186)
using the host1x_test test suite available at

http://github.com/cyndis/host1x_test

The series itself is available at

http://github.com/cyndis/linux, branch host1x-t186-1

Cheers,
Mikko

Mikko Perttunen (6):
  arm64: tegra: Add #power-domain-cells for BPMP
  arm64: tegra: Add host1x on Tegra186
  arm64: tegra: Add VIC on Tegra186
  dt-bindings: host1x: Fix and add Tegra186 information
  gpu: host1x: Add Tegra186 support
  drm/tegra: Add Tegra186 support for VIC

 .../display/tegra/nvidia,tegra20-host1x.txt        |   9 +-
 arch/arm64/boot/dts/nvidia/tegra186.dtsi           |  31 ++++
 drivers/gpu/drm/tegra/drm.c                        |   1 +
 drivers/gpu/drm/tegra/vic.c                        |  10 ++
 drivers/gpu/host1x/Makefile                        |   3 +-
 drivers/gpu/host1x/dev.c                           |  60 ++++++-
 drivers/gpu/host1x/dev.h                           |   4 +
 drivers/gpu/host1x/hw/cdma_hw.c                    |  49 +++---
 drivers/gpu/host1x/hw/debug_hw.c                   | 137 +---------------
 .../gpu/host1x/hw/{debug_hw.c => debug_hw_1x01.c}  | 160 ------------------
 drivers/gpu/host1x/hw/debug_hw_1x06.c              | 133 +++++++++++++++
 drivers/gpu/host1x/hw/host1x01.c                   |   2 +
 drivers/gpu/host1x/hw/host1x02.c                   |   2 +
 drivers/gpu/host1x/hw/host1x04.c                   |   2 +
 drivers/gpu/host1x/hw/host1x05.c                   |   2 +
 drivers/gpu/host1x/hw/{host1x02.c => host1x06.c}   |  12 +-
 drivers/gpu/host1x/hw/{host1x02.c => host1x06.h}   |  30 +---
 drivers/gpu/host1x/hw/host1x06_hardware.h          | 142 ++++++++++++++++
 drivers/gpu/host1x/hw/hw_host1x06_hypervisor.h     |  32 ++++
 drivers/gpu/host1x/hw/hw_host1x06_uclass.h         | 181 +++++++++++++++++++++
 drivers/gpu/host1x/hw/hw_host1x06_vm.h             |  47 ++++++
 drivers/gpu/host1x/hw/intr_hw.c                    |  29 ++--
 22 files changed, 719 insertions(+), 359 deletions(-)
 copy drivers/gpu/host1x/hw/{debug_hw.c => debug_hw_1x01.c} (53%)
 create mode 100644 drivers/gpu/host1x/hw/debug_hw_1x06.c
 copy drivers/gpu/host1x/hw/{host1x02.c => host1x06.c} (84%)
 copy drivers/gpu/host1x/hw/{host1x02.c => host1x06.h} (50%)
 create mode 100644 drivers/gpu/host1x/hw/host1x06_hardware.h
 create mode 100644 drivers/gpu/host1x/hw/hw_host1x06_hypervisor.h
 create mode 100644 drivers/gpu/host1x/hw/hw_host1x06_uclass.h
 create mode 100644 drivers/gpu/host1x/hw/hw_host1x06_vm.h

-- 
2.14.1

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#1714300 — [PATCH 4/6] dt-bindings: host1x: Fix and add Tegra186 information

Add note that address/size-cells should be 2 on 64-bit systems,
and add Tegra186-specific register range properties.

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
---
 .../devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt  | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt
index 74e1e8add5a1..b3e785b47100 100644
--- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt
+++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt
@@ -3,11 +3,16 @@ NVIDIA Tegra host1x
 Required properties:
 - compatible: "nvidia,tegra<chip>-host1x"
 - reg: Physical base address and length of the controller's registers.
+  For pre-Tegra186, one entry describing the whole register area.
+  For Tegra186, one entry for each entry in reg-names:
+    "vm" - VM region assigned to Linux
+    "hypervisor" - Hypervisor region (only if Linux acts as hypervisor)
 - interrupts: The interrupt outputs from the controller.
 - #address-cells: The number of cells used to represent physical base addresses
-  in the host1x address space. Should be 1.
+  in the host1x address space. Should be 1 for 32-bit and 2 for 64-bit systems.
 - #size-cells: The number of cells used to represent the size of an address
-  range in the host1x address space. Should be 1.
+  range in the host1x address space. Should be 1 for 32-bit and 2 for 64-bit
+  systems.
 - ranges: The mapping of the host1x address space to the CPU address space.
 - clocks: Must contain one entry, for the module clock.
   See ../clocks/clock-bindings.txt for details.
-- 
2.14.1

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#1716987 — Re: [PATCH 4/6] dt-bindings: host1x: Fix and add Tegra186 information

On Thu, Aug 17, 2017 at 09:54:11PM +0300, Mikko Perttunen wrote:
> Add note that address/size-cells should be 2 on 64-bit systems,
> and add Tegra186-specific register range properties.

Generally the cell sizes have nothing to do with the addressing size of 
the cpu. They should be as small as what fits for the given sub-tree. If 
all the register space fits into 4GB, then there's no reason for the 
#size-cells to be 2. The same is true if the sub-tree has a parent bus.

Rob

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#1714445 — Re: [PATCH 5/6] gpu: host1x: Add Tegra186 support

On 17.08.2017 21:54, Mikko Perttunen wrote:
> Add support for the implementation of Host1x present on the Tegra186.
> The register space has been shuffled around a little bit, requiring
> addition of some chip-specific code sections. Tegra186 also adds
> several new features, most importantly the hypervisor, but those are
> not yet supported with this commit.
> 
> Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
> ---

I haven't reviewed Tegra186-specific code since I'm not familiar with that
platform. Code movement related to pre-Tegra186 looks fine, no regressions
spotted on Tegra20.

Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
Tested-by: Dmitry Osipenko <digetx@gmail.com>

-- 
Dmitry

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