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[PATCH v2 1/6] devicetree: Extend synopsys ddrc binding for Xilinx ZynqMP

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  [PATCH v2 1/6] devicetree: Extend synopsys ddrc binding for Xilinx ZynqMP Michal Simek <michal.simek@xilinx.com> - 2017-08-07 09:40 +0200
    [PATCH v2 6/6] edac: synopsys: Enable CE and UE interrupts for ZynqMP DDRC Michal Simek <michal.simek@xilinx.com> - 2017-08-07 09:40 +0200
    [PATCH v2 2/6] edac: synopsys: Add platform specific structures for ddrc controller Michal Simek <michal.simek@xilinx.com> - 2017-08-07 09:50 +0200
      Re: [PATCH v2 2/6] edac: synopsys: Add platform specific structures  for ddrc controller Borislav Petkov <bp@alien8.de> - 2017-08-11 11:10 +0200
        Re: [PATCH v2 2/6] edac: synopsys: Add platform specific structures  for ddrc controller Borislav Petkov <bp@alien8.de> - 2017-08-11 11:30 +0200
    [PATCH v2 4/6] edac: synopsys: Add ECC error injection support Michal Simek <michal.simek@xilinx.com> - 2017-08-07 09:50 +0200
    [PATCH v2 5/6] edac: synopsys: Update ECC error message info Michal Simek <michal.simek@xilinx.com> - 2017-08-07 09:50 +0200
    Re: [PATCH v2 1/6] devicetree: Extend synopsys ddrc binding for  Xilinx ZynqMP Rob Herring <robh@kernel.org> - 2017-08-10 22:50 +0200

#1705179 — [PATCH v2 1/6] devicetree: Extend synopsys ddrc binding for Xilinx ZynqMP

Add ZynqMP support to Synopsys memory controller.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---

Changes in v2:
- New patch in this series

 .../devicetree/bindings/memory-controllers/synopsys.txt    | 14 +++++++++++++-
 1 file changed, 13 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/memory-controllers/synopsys.txt b/Documentation/devicetree/bindings/memory-controllers/synopsys.txt
index a43d26d41e04..08c058d5ad76 100644
--- a/Documentation/devicetree/bindings/memory-controllers/synopsys.txt
+++ b/Documentation/devicetree/bindings/memory-controllers/synopsys.txt
@@ -5,11 +5,23 @@ configuration. The ECC controller corrects one bit error and detects
 two bit errors.
 
 Required properties:
- - compatible: Should be 'xlnx,zynq-ddrc-a05'
+ - compatible: Should be 'xlnx,zynq-ddrc-a05' for Zynq
+	       and 'xlnx,zynqmp-ddrc-2.40a' for ZynqMP
  - reg: Base address and size of the controllers memory area
+ - interrupt-parent: Should be core interrupt controller
+		     valid for ZynqMP DDR Controller
+ - interrupts: Property with a value describing the interrupt number
+	       valid for ZynqMP DDR Controller
 
 Example:
 	memory-controller@f8006000 {
 		compatible = "xlnx,zynq-ddrc-a05";
 		reg = <0xf8006000 0x1000>;
 	};
+
+	mc: memory-controller@fd070000 {
+		compatible = "xlnx,zynqmp-ddrc-2.40a";
+		reg = <0x0 0xfd070000 0x0 0x30000>;
+		interrupt-parent = <&gic>;
+		interrupts = <0 112 4>;
+	};
-- 
1.9.1

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#1705181 — [PATCH v2 6/6] edac: synopsys: Enable CE and UE interrupts for ZynqMP DDRC

From: Naga Sureshkumar Relli <naga.sureshkumar.relli@xilinx.com>

This patch enables Corrected and Uncorrected Error
interrupts for ZynqMP DDRC controller

Signed-off-by: Naga Sureshkumar Relli <nagasure@xilinx.com>
Reviewed-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---

Changes in v2:
- Fix function alignment
- Fix macro indentation

 drivers/edac/synopsys_edac.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/drivers/edac/synopsys_edac.c b/drivers/edac/synopsys_edac.c
index 24490334a4f2..f185a28d2db3 100644
--- a/drivers/edac/synopsys_edac.c
+++ b/drivers/edac/synopsys_edac.c
@@ -165,6 +165,8 @@
 #define DDR_QOSUE_MASK		0x4
 #define DDR_QOSCE_MASK		0x2
 #define ECC_CE_UE_INTR_MASK	0x6
+#define DDR_QOS_IRQ_EN_OFST	0x20208
+#define DDR_QOS_IRQ_DB_OFST	0x2020C
 
 /* ECC Corrected Error Register Mask and Shifts*/
 #define ECC_CEADDR0_RW_MASK	0x3FFFF
@@ -1112,6 +1114,10 @@ static int synps_edac_mc_probe(struct platform_device *pdev)
 			edac_printk(KERN_ERR, EDAC_MC, "Failed to request Irq\n");
 			goto free_edac_mc;
 		}
+
+		/* Enable UE/CE Interrupts */
+		writel((DDR_QOSUE_MASK | DDR_QOSCE_MASK),
+		       priv->baseaddr + DDR_QOS_IRQ_EN_OFST);
 	}
 
 	rc = edac_mc_add_mc(mci);
@@ -1154,6 +1160,10 @@ static int synps_edac_mc_remove(struct platform_device *pdev)
 	struct synps_edac_priv *priv;
 
 	priv = mci->pvt_info;
+	if (priv->p_data->quirks & DDR_ECC_INTR_SUPPORT)
+		/* Disable UE/CE Interrupts */
+		writel((DDR_QOSUE_MASK | DDR_QOSCE_MASK),
+		       priv->baseaddr + DDR_QOS_IRQ_DB_OFST);
 	edac_mc_del_mc(&pdev->dev);
 	if (priv->p_data->quirks & DDR_ECC_DATA_POISON_SUPPORT)
 		synps_edac_remove_sysfs_attributes(mci);
-- 
1.9.1

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#1705189 — [PATCH v2 2/6] edac: synopsys: Add platform specific structures for ddrc controller

From: Naga Sureshkumar Relli <naga.sureshkumar.relli@xilinx.com>

Adds platform specific structures, so that we can add
different IP support later using quirks.

Signed-off-by: Naga Sureshkumar Relli <nagasure@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---

Changes in v2:
- Update commit message
- Update patch subject
- Update kernel-doc description for struct synps_platform_data
- Change synps_platform_data pointer names and update code

 drivers/edac/synopsys_edac.c | 70 ++++++++++++++++++++++++++++++++++++--------
 1 file changed, 58 insertions(+), 12 deletions(-)

diff --git a/drivers/edac/synopsys_edac.c b/drivers/edac/synopsys_edac.c
index 0c9c59e2b5a3..293380f884fe 100644
--- a/drivers/edac/synopsys_edac.c
+++ b/drivers/edac/synopsys_edac.c
@@ -22,6 +22,7 @@
 #include <linux/edac.h>
 #include <linux/module.h>
 #include <linux/platform_device.h>
+#include <linux/of.h>
 
 #include "edac_module.h"
 
@@ -95,6 +96,9 @@
 #define SCRUB_MODE_MASK		0x7
 #define SCRUB_MODE_SECDED	0x4
 
+/* DDR ECC Quirks */
+#define DDR_ECC_INTR_SUPPORT		BIT(0)
+
 /**
  * struct ecc_error_info - ECC error log information
  * @row:	Row number
@@ -130,6 +134,7 @@ struct synps_ecc_status {
  * @baseaddr:	Base address of the DDR controller
  * @message:	Buffer for framing the event specific info
  * @stat:	ECC status information
+ * @p_data:	Pointer to platform data
  * @ce_cnt:	Correctable Error count
  * @ue_cnt:	Uncorrectable Error count
  */
@@ -137,11 +142,29 @@ struct synps_edac_priv {
 	void __iomem *baseaddr;
 	char message[SYNPS_EDAC_MSG_SIZE];
 	struct synps_ecc_status stat;
+	const struct synps_platform_data *p_data;
 	u32 ce_cnt;
 	u32 ue_cnt;
 };
 
 /**
+ * struct synps_platform_data -  synps platform data structure
+ * @edac_geterror_info:	function which returns the current ecc error info
+ * @edac_get_mtype:	function which returns the memory type
+ * @edac_get_dtype:	function which returns the DIMM type
+ * @edac_get_eccstate:	function which returns the ecc enable/disable status
+ * @quirks:		a bitfield of quirks
+ */
+struct synps_platform_data {
+	int (*edac_geterror_info)(void __iomem *base,
+				  struct synps_ecc_status *p);
+	enum mem_type (*edac_get_mtype)(const void __iomem *base);
+	enum dev_type (*edac_get_dtype)(const void __iomem *base);
+	bool (*edac_get_eccstate)(void __iomem *base);
+	int quirks;
+};
+
+/**
  * synps_edac_geterror_info - Get the current ecc error info
  * @base:	Pointer to the base address of the ddr memory controller
  * @p:		Pointer to the synopsys ecc status structure
@@ -242,7 +265,8 @@ static void synps_edac_check(struct mem_ctl_info *mci)
 	struct synps_edac_priv *priv = mci->pvt_info;
 	int status;
 
-	status = synps_edac_geterror_info(priv->baseaddr, &priv->stat);
+	status = priv->p_data->edac_geterror_info(priv->baseaddr,
+						  &priv->stat);
 	if (status)
 		return;
 
@@ -372,10 +396,12 @@ static int synps_edac_init_csrows(struct mem_ctl_info *mci)
 		for (j = 0; j < csi->nr_channels; j++) {
 			dimm            = csi->channels[j]->dimm;
 			dimm->edac_mode = EDAC_FLAG_SECDED;
-			dimm->mtype     = synps_edac_get_mtype(priv->baseaddr);
+			dimm->mtype     = priv->p_data->edac_get_mtype(
+						priv->baseaddr);
 			dimm->nr_pages  = (size >> PAGE_SHIFT) / csi->nr_channels;
 			dimm->grain     = SYNPS_EDAC_ERR_GRAIN;
-			dimm->dtype     = synps_edac_get_dtype(priv->baseaddr);
+			dimm->dtype     = priv->p_data->edac_get_dtype(
+						priv->baseaddr);
 		}
 	}
 
@@ -423,6 +449,21 @@ static int synps_edac_mc_init(struct mem_ctl_info *mci,
 	return status;
 }
 
+static const struct synps_platform_data zynq_edac_def = {
+	.edac_geterror_info	= synps_edac_geterror_info,
+	.edac_get_mtype		= synps_edac_get_mtype,
+	.edac_get_dtype		= synps_edac_get_dtype,
+	.edac_get_eccstate	= synps_edac_get_eccstate,
+	.quirks			= 0,
+};
+
+static const struct of_device_id synps_edac_match[] = {
+	{ .compatible = "xlnx,zynq-ddrc-a05", .data = (void *)&zynq_edac_def },
+	{ /* end of table */ }
+};
+
+MODULE_DEVICE_TABLE(of, synps_edac_match);
+
 /**
  * synps_edac_mc_probe - Check controller and bind driver
  * @pdev:	Pointer to the platform_device struct
@@ -440,13 +481,22 @@ static int synps_edac_mc_probe(struct platform_device *pdev)
 	int rc;
 	struct resource *res;
 	void __iomem *baseaddr;
+	const struct of_device_id *match;
+	const struct synps_platform_data *p_data;
 
 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	baseaddr = devm_ioremap_resource(&pdev->dev, res);
 	if (IS_ERR(baseaddr))
 		return PTR_ERR(baseaddr);
 
-	if (!synps_edac_get_eccstate(baseaddr)) {
+	match = of_match_node(synps_edac_match, pdev->dev.of_node);
+	if (!match && !match->data) {
+		dev_err(&pdev->dev, "of_match_node() failed\n");
+		return -EINVAL;
+	}
+
+	p_data = (struct synps_platform_data *)match->data;
+	if (!(p_data->edac_get_eccstate(baseaddr))) {
 		edac_printk(KERN_INFO, EDAC_MC, "ECC not enabled\n");
 		return -ENXIO;
 	}
@@ -468,6 +518,8 @@ static int synps_edac_mc_probe(struct platform_device *pdev)
 
 	priv = mci->pvt_info;
 	priv->baseaddr = baseaddr;
+	priv->p_data = match->data;
+
 	rc = synps_edac_mc_init(mci, pdev);
 	if (rc) {
 		edac_printk(KERN_ERR, EDAC_MC,
@@ -486,7 +538,8 @@ static int synps_edac_mc_probe(struct platform_device *pdev)
 	 * Start capturing the correctable and uncorrectable errors. A write of
 	 * 0 starts the counters.
 	 */
-	writel(0x0, baseaddr + ECC_CTRL_OFST);
+	if (!(priv->p_data->quirks & DDR_ECC_INTR_SUPPORT))
+		writel(0x0, baseaddr + ECC_CTRL_OFST);
 	return rc;
 
 free_edac_mc:
@@ -511,13 +564,6 @@ static int synps_edac_mc_remove(struct platform_device *pdev)
 	return 0;
 }
 
-static const struct of_device_id synps_edac_match[] = {
-	{ .compatible = "xlnx,zynq-ddrc-a05", },
-	{ /* end of table */ }
-};
-
-MODULE_DEVICE_TABLE(of, synps_edac_match);
-
 static struct platform_driver synps_edac_mc_driver = {
 	.driver = {
 		   .name = "synopsys-edac",
-- 
1.9.1

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#1709391 — Re: [PATCH v2 2/6] edac: synopsys: Add platform specific structures for ddrc controller

On Mon, Aug 07, 2017 at 09:39:24AM +0200, Michal Simek wrote:
> From: Naga Sureshkumar Relli <naga.sureshkumar.relli@xilinx.com>
> 
> Adds platform specific structures, so that we can add
> different IP support later using quirks.
> 
> Signed-off-by: Naga Sureshkumar Relli <nagasure@xilinx.com>
> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
> ---
> 
> Changes in v2:

Subject says "2/6" but I can't find 1/6 in my mbox. Nothing in spam
folder either. What's up?

Are you using the --cover-letter option to git format-patch ?

-- 
Regards/Gruss,
    Boris.

ECO tip #101: Trim your mails when you reply.
--

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#1709400 — Re: [PATCH v2 2/6] edac: synopsys: Add platform specific structures for ddrc controller

On Fri, Aug 11, 2017 at 11:16:15AM +0200, Michal Simek wrote:
> https://lkml.org/lkml/2017/8/7/105
> ACK by Rob yesterday.

Ok, pls bounce it to me as I don't have it.

Also, pls refrain from using lkml.org. Simply do:

http://lkml.kernel.org/r/<Message-ID>

> I am using patman - u-boot tools for sending patch. It read MAINTAINERS
> file and copy right people.
> It has option to explicitly CC people. I need to resend this as v3
> anyway that's why I will add you there.

Yes, if you send cross-maintainer changes, please make sure to CC them on all
patches because otherwise stuff like that happens and people start wondering
where is the rest and so on.

Thx.

-- 
Regards/Gruss,
    Boris.

ECO tip #101: Trim your mails when you reply.
--

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#1705192 — [PATCH v2 4/6] edac: synopsys: Add ECC error injection support

From: Naga Sureshkumar Relli <naga.sureshkumar.relli@xilinx.com>

The ZynqMP DDRC controller has data poisoning support
to inject CE or UE errors. this patch adds this support
using sysfs attributes.

created the following sysfs entries to support this.
-> /sys/devices/system/edac/mc/mc0/inject_data_poison
-> /sys/devices/system/edac/mc/mc0/inject_data_error

Signed-off-by: Naga Sureshkumar Relli <nagasure@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---

Changes in v2:
- s/ecc/ECC/ is subject
- fix function parameters alignment
- fix some kernel-doc descriptions

 drivers/edac/synopsys_edac.c | 288 ++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 287 insertions(+), 1 deletion(-)

diff --git a/drivers/edac/synopsys_edac.c b/drivers/edac/synopsys_edac.c
index 11016cd13a08..4cd9e3d8161c 100644
--- a/drivers/edac/synopsys_edac.c
+++ b/drivers/edac/synopsys_edac.c
@@ -99,6 +99,7 @@
 
 /* DDR ECC Quirks */
 #define DDR_ECC_INTR_SUPPORT		BIT(0)
+#define DDR_ECC_DATA_POISON_SUPPORT	BIT(1)
 
 /* ZynqMP Enhanced DDR memory controller registers that are relevant to ECC */
 /* ECC Configuration Registers */
@@ -174,6 +175,11 @@
 #define ECC_CEADDR1_BNKGRP_SHIFT	24
 #define ECC_CEADDR1_BNKNR_SHIFT	16
 
+/* ECC Poison register shifts */
+#define ECC_POISON0_RANK_SHIFT		24
+#define ECC_POISON1_BANKGRP_SHIFT	28
+#define ECC_POISON1_BANKNR_SHIFT	24
+
 /* DDR Memory type defines */
 #define MEM_TYPE_DDR3	0x1
 #define MEM_TYPE_LPDDR3	0x1
@@ -181,6 +187,38 @@
 #define MEM_TYPE_DDR4	0x10
 #define MEM_TYPE_LPDDR4	0x10
 
+/* DDRC Software control register */
+#define DDRC_SWCTL	0x320
+
+/* DDRC ECC CE & UE poison mask */
+#define ECC_CEPOISON_MASK	0x3
+#define ECC_UEPOISON_MASK	0x1
+
+/* DDRC Device config masks */
+#define DDRC_MSTR_DEV_CONFIG_MASK	0xC0000000
+#define DDRC_MSTR_DEV_CONFIG_SHIFT	30
+#define DDRC_MSTR_DEV_CONFIG_X4_MASK	0
+#define DDRC_MSTR_DEV_CONFIG_X8_MASK	1
+#define DDRC_MSTR_DEV_CONFIG_X16_MASK	0x10
+#define DDRC_MSTR_DEV_CONFIG_X32_MASK	0X11
+
+/* DDR4 and DDR3 device Row,Column,Bank Mapping */
+#define DDR4_COL_SHIFT		3
+#define DDR4_BANKGRP_SHIFT	13
+#define DDR4_BANK_SHIFT		15
+#define DDR4_ROW_SHIFT		17
+#define DDR4_COL_MASK		0x3FF
+#define DDR4_BANKGRP_MASK	0x3
+#define DDR4_BANK_MASK		0x3
+#define DDR4_ROW_MASK		0x7FFF
+
+#define DDR3_COL_SHIFT		3
+#define DDR3_BANK_SHIFT		13
+#define DDR3_ROW_SHIFT		16
+#define DDR3_COL_MASK		0x3FF
+#define DDR3_BANK_MASK		0x7
+#define DDR3_ROW_MASK		0x3FFF
+
 /**
  * struct ecc_error_info - ECC error log information
  * @row:	Row number
@@ -223,6 +261,7 @@ struct synps_ecc_status {
  * @p_data:	Pointer to platform data
  * @ce_cnt:	Correctable Error count
  * @ue_cnt:	Uncorrectable Error count
+ * @poison_addr: Data poison address
  */
 struct synps_edac_priv {
 	void __iomem *baseaddr;
@@ -231,6 +270,7 @@ struct synps_edac_priv {
 	const struct synps_platform_data *p_data;
 	u32 ce_cnt;
 	u32 ue_cnt;
+	ulong poison_addr;
 };
 
 /**
@@ -732,7 +772,8 @@ static int synps_edac_mc_init(struct mem_ctl_info *mci,
 	.edac_get_mtype		= synps_enh_edac_get_mtype,
 	.edac_get_dtype		= synps_enh_edac_get_dtype,
 	.edac_get_eccstate	= synps_enh_edac_get_eccstate,
-	.quirks			= DDR_ECC_INTR_SUPPORT,
+	.quirks			= (DDR_ECC_INTR_SUPPORT |
+				   DDR_ECC_DATA_POISON_SUPPORT),
 };
 
 static const struct of_device_id synps_edac_match[] = {
@@ -744,6 +785,240 @@ static int synps_edac_mc_init(struct mem_ctl_info *mci,
 
 MODULE_DEVICE_TABLE(of, synps_edac_match);
 
+#define to_mci(k) container_of(k, struct mem_ctl_info, dev)
+
+/**
+ * ddr4_poison_setup - update poison registers
+ * @dttype:		Device structure variable
+ * @device_config:	Device configuration
+ * @priv:		Pointer to synps_edac_priv struct
+ *
+ * Update poison registers as per ddr4 mapping
+ */
+static void ddr4_poison_setup(enum dev_type dttype, int device_config,
+			      struct synps_edac_priv *priv)
+{
+	int col, row, bank, bankgrp, regval, shift_val = 0, col_shift;
+
+	/* Check the Configuration of the device */
+	if (device_config & DDRC_MSTR_DEV_CONFIG_X8_MASK) {
+		/* For Full Dq bus */
+		if (dttype == DEV_X8)
+			shift_val = 0;
+		/* For Half Dq bus */
+		else if (dttype == DEV_X4)
+			shift_val = 1;
+		col_shift = 0;
+	} else if (device_config & DDRC_MSTR_DEV_CONFIG_X16_MASK) {
+		if (dttype == DEV_X8)
+			shift_val = 1;
+		else if (dttype == DEV_X4)
+			shift_val = 2;
+		col_shift = 1;
+	}
+
+	col = (priv->poison_addr >> (DDR4_COL_SHIFT -
+				(shift_val - col_shift))) &
+				DDR4_COL_MASK;
+	row = priv->poison_addr >> (DDR4_ROW_SHIFT - shift_val);
+	row &= DDR4_ROW_MASK;
+	bank = priv->poison_addr >> (DDR4_BANK_SHIFT - shift_val);
+	bank &= DDR4_BANK_MASK;
+	bankgrp = (priv->poison_addr >> (DDR4_BANKGRP_SHIFT -
+				(shift_val - col_shift))) &
+				DDR4_BANKGRP_MASK;
+
+	writel(col, priv->baseaddr + ECC_POISON0_OFST);
+	regval = (bankgrp << ECC_POISON1_BANKGRP_SHIFT) |
+		 (bank << ECC_POISON1_BANKNR_SHIFT) | row;
+	writel(regval, priv->baseaddr + ECC_POISON1_OFST);
+}
+
+/**
+ * ddr3_poison_setup - update poison registers
+ * @dttype:		Device structure variable
+ * @device_config:	Device configuration
+ * @priv:		Pointer to synps_edac_priv struct
+ *
+ * Update poison registers as per ddr3 mapping
+ */
+static void ddr3_poison_setup(enum dev_type dttype, int device_config,
+			      struct synps_edac_priv *priv)
+{
+	int col, row, bank, bankgrp, regval, shift_val = 0;
+
+	if (dttype == DEV_X8)
+		/* For Full Dq bus */
+		shift_val = 0;
+	else if (dttype == DEV_X4)
+		/* For Half Dq bus */
+		shift_val = 1;
+
+	col = (priv->poison_addr >> (DDR3_COL_SHIFT - shift_val)) &
+		DDR3_COL_MASK;
+	row = priv->poison_addr >> (DDR3_ROW_SHIFT - shift_val);
+	row &= DDR3_ROW_MASK;
+	bank = priv->poison_addr >> (DDR3_BANK_SHIFT - shift_val);
+	bank &= DDR3_BANK_MASK;
+	bankgrp = 0;
+	writel(col, priv->baseaddr + ECC_POISON0_OFST);
+	regval = (bankgrp << ECC_POISON1_BANKGRP_SHIFT) |
+			 (bank << ECC_POISON1_BANKNR_SHIFT) | row;
+	writel(regval, priv->baseaddr + ECC_POISON1_OFST);
+}
+
+/**
+ * synps_edac_mc_inject_data_error_show - Get Poison0 & 1 register contents
+ * @dev:	Pointer to the device struct
+ * @mattr:	Pointer to device attributes
+ * @data:	Pointer to user data
+ *
+ * Get the Poison0 and Poison1 register contents
+ * Return: Number of bytes copied.
+ */
+static ssize_t
+synps_edac_mc_inject_data_error_show(struct device *dev,
+				     struct device_attribute *mattr,
+				     char *data)
+{
+	struct mem_ctl_info *mci = to_mci(dev);
+	struct synps_edac_priv *priv = mci->pvt_info;
+
+	return sprintf(data, "Poison0 Addr: 0x%08x\n\rPoison1 Addr: 0x%08x\n\r"
+			"Error injection Address: 0x%lx\n\r",
+			readl(priv->baseaddr + ECC_POISON0_OFST),
+			readl(priv->baseaddr + ECC_POISON1_OFST),
+			priv->poison_addr);
+}
+
+/**
+ * synps_edac_mc_inject_data_error_store - Configure Poison0 Poison1 registers
+ * @dev:	Pointer to the device struct
+ * @mattr:	Pointer to device attributes
+ * @data:	Pointer to user data
+ * @count:	read the size bytes from buffer
+ *
+ * Configures the Poison0 and Poison1 register contents as per user given
+ * address
+ * Return: Number of bytes copied.
+ */
+static ssize_t
+synps_edac_mc_inject_data_error_store(struct device *dev,
+				      struct device_attribute *mattr,
+				      const char *data, size_t count)
+{
+	struct mem_ctl_info *mci = to_mci(dev);
+	struct synps_edac_priv *priv = mci->pvt_info;
+	int device_config;
+	enum mem_type mttype;
+	enum dev_type dttype;
+
+	mttype = priv->p_data->edac_get_mtype(priv->baseaddr);
+	dttype = priv->p_data->edac_get_dtype(priv->baseaddr);
+	if (kstrtoul(data, 0, &priv->poison_addr))
+		return -EINVAL;
+
+	device_config = readl(priv->baseaddr + CTRL_OFST);
+	device_config = (device_config & DDRC_MSTR_DEV_CONFIG_MASK) >>
+					DDRC_MSTR_DEV_CONFIG_SHIFT;
+	if (mttype == MEM_DDR4)
+		ddr4_poison_setup(dttype, device_config, priv);
+	else if (mttype == MEM_DDR3)
+		ddr3_poison_setup(dttype, device_config, priv);
+
+	return count;
+}
+
+/**
+ * synps_edac_mc_inject_data_poison_show - Shows type of Data poison
+ * @dev:	Pointer to the device struct
+ * @mattr:	Pointer to device attributes
+ * @data:	Pointer to user data
+ *
+ * Shows the type of Error injection enabled, either UE or CE
+ * Return: Number of bytes copied.
+ */
+static ssize_t
+synps_edac_mc_inject_data_poison_show(struct device *dev,
+				      struct device_attribute *mattr,
+				      char *data)
+{
+	struct mem_ctl_info *mci = to_mci(dev);
+	struct synps_edac_priv *priv = mci->pvt_info;
+
+	return sprintf(data, "Data Poisoning: %s\n\r",
+		       (readl(priv->baseaddr + ECC_CFG1_OFST)) & 0x3 ?
+		       "Correctable Error" : "UnCorrectable Error");
+}
+
+/**
+ * synps_edac_mc_inject_data_poison_store - Enbles Data poison CE/UE
+ * @dev:	Pointer to the device struct
+ * @mattr:	Pointer to device attributes
+ * @data:	Pointer to user data
+ * @count:	read the size bytes from buffer
+ *
+ * Enables the CE or UE Data poison
+ * Return: Number of bytes copied.
+ */
+static ssize_t
+synps_edac_mc_inject_data_poison_store(struct device *dev,
+				       struct device_attribute *mattr,
+				       const char *data, size_t count)
+{
+	struct mem_ctl_info *mci = to_mci(dev);
+	struct synps_edac_priv *priv = mci->pvt_info;
+
+	writel(0, priv->baseaddr + DDRC_SWCTL);
+	if (strncmp(data, "CE", 2) == 0)
+		writel(ECC_CEPOISON_MASK, priv->baseaddr + ECC_CFG1_OFST);
+	else
+		writel(ECC_UEPOISON_MASK, priv->baseaddr + ECC_CFG1_OFST);
+	writel(1, priv->baseaddr + DDRC_SWCTL);
+
+	return count;
+}
+
+static DEVICE_ATTR(inject_data_error, 0644,
+	    synps_edac_mc_inject_data_error_show,
+	    synps_edac_mc_inject_data_error_store);
+static DEVICE_ATTR(inject_data_poison, 0644,
+	    synps_edac_mc_inject_data_poison_show,
+	    synps_edac_mc_inject_data_poison_store);
+
+/**
+ * synps_edac_create_sysfs_attributes - Create sysfs entries
+ * @mci:	Pointer to the edac memory controller instance
+ *
+ * Create sysfs attributes for injecting ECC errors using data poison.
+ *
+ * Return: 0 if sysfs creation was successful, else return negative error code.
+ */
+static int synps_edac_create_sysfs_attributes(struct mem_ctl_info *mci)
+{
+	int rc;
+
+	rc = device_create_file(&mci->dev, &dev_attr_inject_data_error);
+	if (rc < 0)
+		return rc;
+	rc = device_create_file(&mci->dev, &dev_attr_inject_data_poison);
+	if (rc < 0)
+		return rc;
+	return 0;
+}
+
+/**
+ * synps_edac_remove_sysfs_attributes - Removes sysfs entries
+ * @mci:	Pointer to the edac memory controller instance
+ *
+ * Removes sysfs attributes.
+ */
+static void synps_edac_remove_sysfs_attributes(struct mem_ctl_info *mci)
+{
+	device_remove_file(&mci->dev, &dev_attr_inject_data_error);
+	device_remove_file(&mci->dev, &dev_attr_inject_data_poison);
+}
+
 /**
  * synps_edac_mc_probe - Check controller and bind driver
  * @pdev:	Pointer to the platform_device struct
@@ -831,6 +1106,13 @@ static int synps_edac_mc_probe(struct platform_device *pdev)
 		goto free_edac_mc;
 	}
 
+	if (priv->p_data->quirks & DDR_ECC_DATA_POISON_SUPPORT) {
+		if (synps_edac_create_sysfs_attributes(mci)) {
+			edac_printk(KERN_ERR, EDAC_MC,
+				    "Failed to create sysfs entries\n");
+			goto free_edac_mc;
+		}
+	}
 	/*
 	 * Start capturing the correctable and uncorrectable errors. A write of
 	 * 0 starts the counters.
@@ -854,8 +1136,12 @@ static int synps_edac_mc_probe(struct platform_device *pdev)
 static int synps_edac_mc_remove(struct platform_device *pdev)
 {
 	struct mem_ctl_info *mci = platform_get_drvdata(pdev);
+	struct synps_edac_priv *priv;
 
+	priv = mci->pvt_info;
 	edac_mc_del_mc(&pdev->dev);
+	if (priv->p_data->quirks & DDR_ECC_DATA_POISON_SUPPORT)
+		synps_edac_remove_sysfs_attributes(mci);
 	edac_mc_free(mci);
 
 	return 0;
-- 
1.9.1

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#1705202 — [PATCH v2 5/6] edac: synopsys: Update ECC error message info

From: Naga Sureshkumar Relli <naga.sureshkumar.relli@xilinx.com>

This patch updates the ECC error message info
for zynqmp ddrc. added Block number and Bankgroup
in the message info.

Signed-off-by: Naga Sureshkumar Relli <nagasure@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---

Changes in v2:
- s/ecc/ECC/ in commit message

 drivers/edac/synopsys_edac.c | 27 +++++++++++++++++++++------
 1 file changed, 21 insertions(+), 6 deletions(-)

diff --git a/drivers/edac/synopsys_edac.c b/drivers/edac/synopsys_edac.c
index 4cd9e3d8161c..24490334a4f2 100644
--- a/drivers/edac/synopsys_edac.c
+++ b/drivers/edac/synopsys_edac.c
@@ -418,9 +418,17 @@ static void synps_edac_handle_error(struct mem_ctl_info *mci,
 
 	if (p->ce_cnt) {
 		pinf = &p->ceinfo;
-		snprintf(priv->message, SYNPS_EDAC_MSG_SIZE,
-			 "DDR ECC error type :%s Row %d Bank %d Col %d ",
-			 "CE", pinf->row, pinf->bank, pinf->col);
+		if (priv->p_data->quirks == 0)
+			snprintf(priv->message, SYNPS_EDAC_MSG_SIZE,
+				 "DDR ECC error type :%s Row %d Bank %d Col %d ",
+				 "CE", pinf->row, pinf->bank, pinf->col);
+		else
+			snprintf(priv->message, SYNPS_EDAC_MSG_SIZE,
+				 "DDR ECC error type :%s Row %d Bank %d Col %d "
+				 "BankGroup Number %d Block Number %d",
+				 "CE", pinf->row, pinf->bank, pinf->col,
+				 pinf->bankgrpnr, pinf->blknr);
+
 		edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci,
 				     p->ce_cnt, 0, 0, 0, 0, 0, -1,
 				     priv->message, "");
@@ -428,9 +436,16 @@ static void synps_edac_handle_error(struct mem_ctl_info *mci,
 
 	if (p->ue_cnt) {
 		pinf = &p->ueinfo;
-		snprintf(priv->message, SYNPS_EDAC_MSG_SIZE,
-			 "DDR ECC error type :%s Row %d Bank %d Col %d ",
-			 "UE", pinf->row, pinf->bank, pinf->col);
+		if (priv->p_data->quirks == 0)
+			snprintf(priv->message, SYNPS_EDAC_MSG_SIZE,
+				 "DDR ECC error type :%s Row %d Bank %d Col %d ",
+				"UE", pinf->row, pinf->bank, pinf->col);
+		else
+			snprintf(priv->message, SYNPS_EDAC_MSG_SIZE,
+				 "DDR ECC error type :%s Row %d Bank %d Col %d "
+				 "BankGroup Number %d Block Number %d",
+				 "UE", pinf->row, pinf->bank, pinf->col,
+				 pinf->bankgrpnr, pinf->blknr);
 		edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci,
 				     p->ue_cnt, 0, 0, 0, 0, 0, -1,
 				     priv->message, "");
-- 
1.9.1

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#1709019 — Re: [PATCH v2 1/6] devicetree: Extend synopsys ddrc binding for Xilinx ZynqMP

On Mon, Aug 07, 2017 at 09:39:23AM +0200, Michal Simek wrote:
> Add ZynqMP support to Synopsys memory controller.
> 
> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
> ---
> 
> Changes in v2:
> - New patch in this series
> 
>  .../devicetree/bindings/memory-controllers/synopsys.txt    | 14 +++++++++++++-
>  1 file changed, 13 insertions(+), 1 deletion(-)

Acked-by: Rob Herring <robh@kernel.org>

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