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Groups > linux.kernel > #1691591 > unrolled thread
| Started by | Abhishek Sahu <absahu@codeaurora.org> |
|---|---|
| First post | 2017-07-19 13:50 +0200 |
| Last post | 2017-07-19 14:00 +0200 |
| Articles | 20 on this page of 24 — 3 participants |
Back to article view | Back to linux.kernel
[PATCH v2 00/25] Add QCOM QPIC NAND support Abhishek Sahu <absahu@codeaurora.org> - 2017-07-19 13:50 +0200
[PATCH v2 09/25] mtd: nand: qcom: remove memset for clearing read register buffer Abhishek Sahu <absahu@codeaurora.org> - 2017-07-19 14:00 +0200
[PATCH v2 10/25] mtd: nand: qcom: reorganize nand devices probing Abhishek Sahu <absahu@codeaurora.org> - 2017-07-19 14:00 +0200
[PATCH v2 23/25] mtd: nand: qcom: change register offset defines with enums Abhishek Sahu <absahu@codeaurora.org> - 2017-07-19 14:00 +0200
[PATCH v2 20/25] mtd: nand: qcom: erased codeword detection configuration Abhishek Sahu <absahu@codeaurora.org> - 2017-07-19 14:00 +0200
[PATCH v2 08/25] mtd: nand: qcom: reorganize nand page write Abhishek Sahu <absahu@codeaurora.org> - 2017-07-19 14:00 +0200
[PATCH v2 18/25] mtd: nand: qcom: support for passing flags in transfer functions Abhishek Sahu <absahu@codeaurora.org> - 2017-07-19 14:00 +0200
[PATCH v2 25/25] mtd: nand: qcom: support for QPIC version 1.5.0 Abhishek Sahu <absahu@codeaurora.org> - 2017-07-19 14:00 +0200
[PATCH v2 22/25] mtd: nand: qcom: QPIC raw write support Abhishek Sahu <absahu@codeaurora.org> - 2017-07-19 14:00 +0200
[PATCH v2 12/25] dt-bindings: qcom_nandc: QPIC NAND documentation Abhishek Sahu <absahu@codeaurora.org> - 2017-07-19 14:00 +0200
Re: [PATCH v2 12/25] dt-bindings: qcom_nandc: QPIC NAND documentation Boris Brezillon <boris.brezillon@free-electrons.com> - 2017-07-19 21:40 +0200
Re: [PATCH v2 12/25] dt-bindings: qcom_nandc: QPIC NAND documentation Abhishek Sahu <absahu@codeaurora.org> - 2017-07-20 07:40 +0200
Re: [PATCH v2 12/25] dt-bindings: qcom_nandc: QPIC NAND documentation Rob Herring <robh@kernel.org> - 2017-07-24 21:20 +0200
Re: [PATCH v2 12/25] dt-bindings: qcom_nandc: QPIC NAND documentation Abhishek Sahu <absahu@codeaurora.org> - 2017-07-25 20:50 +0200
[PATCH v2 21/25] mtd: nand: qcom: support for QPIC page read/write Abhishek Sahu <absahu@codeaurora.org> - 2017-07-19 14:00 +0200
[PATCH v2 15/25] mtd: nand: qcom: DMA mapping support for register read buffer Abhishek Sahu <absahu@codeaurora.org> - 2017-07-19 14:00 +0200
[PATCH v2 19/25] mtd: nand: qcom: support for read location registers Abhishek Sahu <absahu@codeaurora.org> - 2017-07-19 14:00 +0200
[PATCH v2 24/25] dt-bindings: qcom_nandc: compatible string for version 1.5.0 Abhishek Sahu <absahu@codeaurora.org> - 2017-07-19 14:00 +0200
[PATCH v2 11/25] mtd: nand: qcom: support for NAND controller properties Abhishek Sahu <absahu@codeaurora.org> - 2017-07-19 14:00 +0200
[PATCH v2 13/25] mtd: nand: qcom: add QPIC NAND compatible string Abhishek Sahu <absahu@codeaurora.org> - 2017-07-19 14:00 +0200
[PATCH v2 17/25] mtd: nand: qcom: add BAM DMA descriptor handling Abhishek Sahu <absahu@codeaurora.org> - 2017-07-19 14:00 +0200
[PATCH v2 16/25] mtd: nand: qcom: allocate BAM transaction Abhishek Sahu <absahu@codeaurora.org> - 2017-07-19 14:00 +0200
[PATCH v2 07/25] mtd: nand: qcom: reorganize nand page read Abhishek Sahu <absahu@codeaurora.org> - 2017-07-19 14:00 +0200
[PATCH v2 14/25] mtd: nand: qcom: add and initialize QPIC DMA resources Abhishek Sahu <absahu@codeaurora.org> - 2017-07-19 14:00 +0200
Page 1 of 2 [1] 2 Next page →
| From | Abhishek Sahu <absahu@codeaurora.org> |
|---|---|
| Date | 2017-07-19 13:50 +0200 |
| Subject | [PATCH v2 00/25] Add QCOM QPIC NAND support |
| Message-ID | <u4VEl-7Z9-9@gated-at.bofh.it> |
v2: 1. Addressed the review comments given in v1 2. Removed the DMA coherent buffer for register read and used streaming DMA API’s 3. Reorganized the NAND read and write functions 4. Separated patch for driver and documentation changes 5. Changed the compatible string for EBI2 v1: http://www.spinics.net/lists/devicetree/msg183706.html Abhishek Sahu (25): mtd: nand: qcom: fix config error for BCH mtd: nand: qcom: program NAND_DEV_CMD_VLD register mtd: nand: qcom: change compatible string for EBI2 NANDC dt-bindings: qcom_nandc: change compatible string for EBI2 NANDC mtd: nand: qcom: remove redundant chip select compatible string dt-bindings: qcom_nandc: remove chip select compatible string mtd: nand: qcom: reorganize nand page read mtd: nand: qcom: reorganize nand page write mtd: nand: qcom: remove memset for clearing read register buffer mtd: nand: qcom: reorganize nand devices probing mtd: nand: qcom: support for NAND controller properties dt-bindings: qcom_nandc: QPIC NAND documentation mtd: nand: qcom: add QPIC NAND compatible string mtd: nand: qcom: add and initialize QPIC DMA resources mtd: nand: qcom: DMA mapping support for register read buffer mtd: nand: qcom: allocate BAM transaction mtd: nand: qcom: add BAM DMA descriptor handling mtd: nand: qcom: support for passing flags in transfer functions mtd: nand: qcom: support for read location registers mtd: nand: qcom: erased codeword detection configuration mtd: nand: qcom: support for QPIC page read/write mtd: nand: qcom: QPIC raw write support mtd: nand: qcom: change register offset defines with enums dt-bindings: qcom_nandc: compatible string for version 1.5.0 mtd: nand: qcom: support for QPIC version 1.5.0 .../devicetree/bindings/mtd/qcom_nandc.txt | 56 +- drivers/mtd/nand/qcom_nandc.c | 1157 ++++++++++++++++---- 2 files changed, 1010 insertions(+), 203 deletions(-) -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
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| From | Abhishek Sahu <absahu@codeaurora.org> |
|---|---|
| Date | 2017-07-19 14:00 +0200 |
| Subject | [PATCH v2 09/25] mtd: nand: qcom: remove memset for clearing read register buffer |
| Message-ID | <u4VO1-85k-1@gated-at.bofh.it> |
| In reply to | #1691591 |
The memset in clear_read_regs is overhead. All the register data
will be filled by DMA during NAND operation so making these
register variables zero is not required.
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
---
drivers/mtd/nand/qcom_nandc.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
index 5b71478..7ecd0f8 100644
--- a/drivers/mtd/nand/qcom_nandc.c
+++ b/drivers/mtd/nand/qcom_nandc.c
@@ -826,8 +826,6 @@ static void free_descs(struct qcom_nand_controller *nandc)
static void clear_read_regs(struct qcom_nand_controller *nandc)
{
nandc->reg_read_pos = 0;
- memset(nandc->reg_read_buf, 0,
- MAX_REG_RD * sizeof(*nandc->reg_read_buf));
}
static void pre_command(struct qcom_nand_host *host, int command)
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
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| From | Abhishek Sahu <absahu@codeaurora.org> |
|---|---|
| Date | 2017-07-19 14:00 +0200 |
| Subject | [PATCH v2 10/25] mtd: nand: qcom: reorganize nand devices probing |
| Message-ID | <u4VO1-85k-3@gated-at.bofh.it> |
| In reply to | #1691591 |
This is reorganization of exiting code and will not change any
functionality. The NAND controller supports multiple NAND device
with different page size. The subsequent patch allocate memory
which depends upon the maximum number of codewords so this patch
reorganizes the NAND device probing. First the ONFI parameter
page will be read from each connected device followed by MTD
device registration.
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
---
drivers/mtd/nand/qcom_nandc.c | 88 +++++++++++++++++++++++++++++--------------
1 file changed, 59 insertions(+), 29 deletions(-)
diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
index 7ecd0f8..8f9e86c 100644
--- a/drivers/mtd/nand/qcom_nandc.c
+++ b/drivers/mtd/nand/qcom_nandc.c
@@ -2059,14 +2059,67 @@ static int qcom_nand_host_init(struct qcom_nand_controller *nandc,
return ret;
ret = qcom_nand_host_setup(host);
- if (ret)
- return ret;
+
+ return ret;
+}
+
+static int qcom_nand_mtd_register(struct qcom_nand_controller *nandc,
+ struct qcom_nand_host *host,
+ struct device_node *dn)
+{
+ struct nand_chip *chip = &host->chip;
+ struct mtd_info *mtd = nand_to_mtd(chip);
+ int ret;
ret = nand_scan_tail(mtd);
if (ret)
return ret;
- return mtd_device_register(mtd, NULL, 0);
+ ret = mtd_device_register(mtd, NULL, 0);
+ if (ret)
+ nand_cleanup(mtd_to_nand(mtd));
+
+ return ret;
+}
+
+static int qcom_probe_nand_devices(struct qcom_nand_controller *nandc)
+{
+ struct device *dev = nandc->dev;
+ struct device_node *dn = dev->of_node, *child;
+ struct qcom_nand_host *host, *tmp;
+ int ret;
+
+ for_each_available_child_of_node(dn, child) {
+ host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
+ if (!host) {
+ of_node_put(child);
+ return -ENOMEM;
+ }
+
+ ret = qcom_nand_host_init(nandc, host, child);
+ if (ret) {
+ devm_kfree(dev, host);
+ continue;
+ }
+
+ list_add_tail(&host->node, &nandc->host_list);
+ }
+
+ if (list_empty(&nandc->host_list))
+ return -ENODEV;
+
+ list_for_each_entry_safe(host, tmp, &nandc->host_list, node) {
+ ret = qcom_nand_mtd_register(nandc, host, child);
+ if (ret) {
+ list_del(&host->node);
+ devm_kfree(dev, host);
+ }
+ }
+
+ if (list_empty(&nandc->host_list))
+ return -ENODEV;
+
+ return 0;
}
/* parse custom DT properties here */
@@ -2094,10 +2147,8 @@ static int qcom_nandc_parse_dt(struct platform_device *pdev)
static int qcom_nandc_probe(struct platform_device *pdev)
{
struct qcom_nand_controller *nandc;
- struct qcom_nand_host *host;
const void *dev_data;
struct device *dev = &pdev->dev;
- struct device_node *dn = dev->of_node, *child;
struct resource *res;
int ret;
@@ -2151,33 +2202,12 @@ static int qcom_nandc_probe(struct platform_device *pdev)
if (ret)
goto err_setup;
- for_each_available_child_of_node(dn, child) {
- host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
- if (!host) {
- of_node_put(child);
- ret = -ENOMEM;
- goto err_cs_init;
- }
-
- ret = qcom_nand_host_init(nandc, host, child);
- if (ret) {
- devm_kfree(dev, host);
- continue;
- }
-
- list_add_tail(&host->node, &nandc->host_list);
- }
-
- if (list_empty(&nandc->host_list)) {
- ret = -ENODEV;
- goto err_cs_init;
- }
+ ret = qcom_probe_nand_devices(nandc);
+ if (ret)
+ goto err_setup;
return 0;
-err_cs_init:
- list_for_each_entry(host, &nandc->host_list, node)
- nand_release(nand_to_mtd(&host->chip));
err_setup:
clk_disable_unprepare(nandc->aon_clk);
err_aon_clk:
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
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| From | Abhishek Sahu <absahu@codeaurora.org> |
|---|---|
| Date | 2017-07-19 14:00 +0200 |
| Subject | [PATCH v2 23/25] mtd: nand: qcom: change register offset defines with enums |
| Message-ID | <u4VO1-85k-5@gated-at.bofh.it> |
| In reply to | #1691591 |
The current driver defines the register offset with preprocessor
macro which is defined crossponding to NAND controller version
1.4.0. This patch changes these macro with enumeration. It also
adds mapping array which contains controller register offsets for
each register offset enumeration. This mapping array will be
referenced before each register read and writes, where the register
offset enumeration is being replaced with actual register offsets.
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
---
drivers/mtd/nand/qcom_nandc.c | 154 +++++++++++++++++++++++++++---------------
1 file changed, 100 insertions(+), 54 deletions(-)
diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
index 7a7db6b..0896e56 100644
--- a/drivers/mtd/nand/qcom_nandc.c
+++ b/drivers/mtd/nand/qcom_nandc.c
@@ -24,43 +24,6 @@
#include <linux/delay.h>
#include <linux/dma/qcom_bam_dma.h>
-/* NANDc reg offsets */
-#define NAND_FLASH_CMD 0x00
-#define NAND_ADDR0 0x04
-#define NAND_ADDR1 0x08
-#define NAND_FLASH_CHIP_SELECT 0x0c
-#define NAND_EXEC_CMD 0x10
-#define NAND_FLASH_STATUS 0x14
-#define NAND_BUFFER_STATUS 0x18
-#define NAND_DEV0_CFG0 0x20
-#define NAND_DEV0_CFG1 0x24
-#define NAND_DEV0_ECC_CFG 0x28
-#define NAND_DEV1_ECC_CFG 0x2c
-#define NAND_DEV1_CFG0 0x30
-#define NAND_DEV1_CFG1 0x34
-#define NAND_READ_ID 0x40
-#define NAND_READ_STATUS 0x44
-#define NAND_DEV_CMD0 0xa0
-#define NAND_DEV_CMD1 0xa4
-#define NAND_DEV_CMD2 0xa8
-#define NAND_DEV_CMD_VLD 0xac
-#define SFLASHC_BURST_CFG 0xe0
-#define NAND_ERASED_CW_DETECT_CFG 0xe8
-#define NAND_ERASED_CW_DETECT_STATUS 0xec
-#define NAND_EBI2_ECC_BUF_CFG 0xf0
-#define FLASH_BUF_ACC 0x100
-
-#define NAND_CTRL 0xf00
-#define NAND_VERSION 0xf08
-#define NAND_READ_LOCATION_0 0xf20
-#define NAND_READ_LOCATION_1 0xf24
-#define NAND_READ_LOCATION_2 0xf28
-#define NAND_READ_LOCATION_3 0xf2c
-
-/* dummy register offsets, used by write_reg_dma */
-#define NAND_DEV_CMD1_RESTORE 0xdead
-#define NAND_DEV_CMD_VLD_RESTORE 0xbeef
-
/* NAND_FLASH_CMD bits */
#define PAGE_ACC BIT(4)
#define LAST_PAGE BIT(5)
@@ -196,6 +159,8 @@
/* Returns the NAND register physical address */
#define NAND_REG_PHYS(chip, offset) ((chip)->base_phys + (offset))
+#define NANDC_FLASH_BUF(nandc) nandc->props->reg_offsets[FLASH_BUF_ACC]
+
#define QPIC_PER_CW_CMD_ELEMENTS 32
#define QPIC_PER_CW_CMD_SGL 32
#define QPIC_PER_CW_DATA_SGL 8
@@ -213,6 +178,44 @@
*/
#define NAND_ERASED_CW_SET BIT(4)
+/* NANDc reg offsets enumeration */
+enum {
+ NAND_FLASH_CMD,
+ NAND_ADDR0,
+ NAND_ADDR1,
+ NAND_FLASH_CHIP_SELECT,
+ NAND_EXEC_CMD,
+ NAND_FLASH_STATUS,
+ NAND_BUFFER_STATUS,
+ NAND_DEV0_CFG0,
+ NAND_DEV0_CFG1,
+ NAND_DEV0_ECC_CFG,
+ NAND_DEV1_ECC_CFG,
+ NAND_DEV1_CFG0,
+ NAND_DEV1_CFG1,
+ NAND_READ_ID,
+ NAND_READ_STATUS,
+ NAND_DEV_CMD0,
+ NAND_DEV_CMD1,
+ NAND_DEV_CMD2,
+ NAND_DEV_CMD_VLD,
+ SFLASHC_BURST_CFG,
+ NAND_ERASED_CW_DETECT_CFG,
+ NAND_ERASED_CW_DETECT_STATUS,
+ NAND_EBI2_ECC_BUF_CFG,
+ FLASH_BUF_ACC,
+ NAND_CTRL,
+ NAND_VERSION,
+ NAND_READ_LOCATION_0,
+ NAND_READ_LOCATION_1,
+ NAND_READ_LOCATION_2,
+ NAND_READ_LOCATION_3,
+
+ /* dummy register offsets, used by write_reg_dma */
+ NAND_DEV_CMD1_RESTORE,
+ NAND_DEV_CMD_VLD_RESTORE,
+};
+
/*
* This data type corresponds to the BAM transaction which will be used for all
* NAND transfers.
@@ -434,10 +437,46 @@ struct qcom_nand_host {
* among different NAND controller IP's.
* @ecc_modes - ecc mode for NAND
* @is_bam - whether NAND controller is using bam
+ * @reg_offsets: register offset mapping array
*/
struct qcom_props {
u32 ecc_modes;
bool is_bam;
+ const u32 *reg_offsets;
+};
+
+/* Mapping table which contains the actual register offsets */
+static const u32 nandc_reg_offsets[] = {
+ [NAND_FLASH_CMD] = 0x00,
+ [NAND_ADDR0] = 0x04,
+ [NAND_ADDR1] = 0x08,
+ [NAND_FLASH_CHIP_SELECT] = 0x0c,
+ [NAND_EXEC_CMD] = 0x10,
+ [NAND_FLASH_STATUS] = 0x14,
+ [NAND_BUFFER_STATUS] = 0x18,
+ [NAND_DEV0_CFG0] = 0x20,
+ [NAND_DEV0_CFG1] = 0x24,
+ [NAND_DEV0_ECC_CFG] = 0x28,
+ [NAND_DEV1_ECC_CFG] = 0x2c,
+ [NAND_DEV1_CFG0] = 0x30,
+ [NAND_DEV1_CFG1] = 0x34,
+ [NAND_READ_ID] = 0x40,
+ [NAND_READ_STATUS] = 0x44,
+ [NAND_DEV_CMD0] = 0xa0,
+ [NAND_DEV_CMD1] = 0xa4,
+ [NAND_DEV_CMD2] = 0xa8,
+ [NAND_DEV_CMD_VLD] = 0xac,
+ [SFLASHC_BURST_CFG] = 0xe0,
+ [NAND_ERASED_CW_DETECT_CFG] = 0xe8,
+ [NAND_ERASED_CW_DETECT_STATUS] = 0xec,
+ [NAND_EBI2_ECC_BUF_CFG] = 0xf0,
+ [FLASH_BUF_ACC] = 0x100,
+ [NAND_CTRL] = 0xf00,
+ [NAND_VERSION] = 0xf08,
+ [NAND_READ_LOCATION_0] = 0xf20,
+ [NAND_READ_LOCATION_1] = 0xf24,
+ [NAND_READ_LOCATION_2] = 0xf28,
+ [NAND_READ_LOCATION_3] = 0xf2c,
};
/* Frees the BAM transaction memory */
@@ -521,13 +560,13 @@ static inline struct qcom_nand_host *to_qcom_nand_host(struct nand_chip *chip)
static inline u32 nandc_read(struct qcom_nand_controller *nandc, int offset)
{
- return ioread32(nandc->base + offset);
+ return ioread32(nandc->base + nandc->props->reg_offsets[offset]);
}
static inline void nandc_write(struct qcom_nand_controller *nandc, int offset,
u32 val)
{
- iowrite32(val, nandc->base + offset);
+ iowrite32(val, nandc->base + nandc->props->reg_offsets[offset]);
}
static inline void nandc_read_buffer_sync(struct qcom_nand_controller *nandc,
@@ -920,19 +959,20 @@ static int read_reg_dma(struct qcom_nand_controller *nandc, int first,
int num_regs, unsigned int flags)
{
bool flow_control = false;
+ u32 reg_offset = nandc->props->reg_offsets[first];
void *vaddr;
vaddr = nandc->reg_read_buf + nandc->reg_read_pos;
nandc->reg_read_pos += num_regs;
if (nandc->props->is_bam)
- return prep_bam_dma_desc_cmd(nandc, true, first, vaddr,
+ return prep_bam_dma_desc_cmd(nandc, true, reg_offset, vaddr,
num_regs, flags);
if (first == NAND_READ_ID || first == NAND_FLASH_STATUS)
flow_control = true;
- return prep_adm_dma_desc(nandc, true, first, vaddr,
+ return prep_adm_dma_desc(nandc, true, reg_offset, vaddr,
num_regs * sizeof(u32), flow_control);
}
@@ -948,6 +988,7 @@ static int write_reg_dma(struct qcom_nand_controller *nandc, int first,
{
bool flow_control = false;
struct nandc_regs *regs = nandc->regs;
+ u32 reg_offset;
void *vaddr;
vaddr = offset_to_nandc_reg(regs, first);
@@ -968,14 +1009,15 @@ static int write_reg_dma(struct qcom_nand_controller *nandc, int first,
if (first == NAND_DEV_CMD_VLD_RESTORE)
first = NAND_DEV_CMD_VLD;
+ reg_offset = nandc->props->reg_offsets[first];
if (nandc->props->is_bam)
- return prep_bam_dma_desc_cmd(nandc, false, first, vaddr,
+ return prep_bam_dma_desc_cmd(nandc, false, reg_offset, vaddr,
num_regs, flags);
if (first == NAND_FLASH_CMD)
flow_control = true;
- return prep_adm_dma_desc(nandc, false, first, vaddr,
+ return prep_adm_dma_desc(nandc, false, reg_offset, vaddr,
num_regs * sizeof(u32), flow_control);
}
@@ -1136,7 +1178,7 @@ static int nandc_param(struct qcom_nand_host *host)
config_nand_single_cw_page_read(nandc);
- read_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer,
+ read_data_dma(nandc, NANDC_FLASH_BUF(nandc), nandc->data_buffer,
nandc->buf_count, 0);
/* restore CMD1 and VLD regs */
@@ -1623,7 +1665,7 @@ static int read_page_ecc(struct qcom_nand_host *host, u8 *data_buf,
config_nand_cw_read(nandc);
if (data_buf)
- read_data_dma(nandc, FLASH_BUF_ACC, data_buf,
+ read_data_dma(nandc, NANDC_FLASH_BUF(nandc), data_buf,
data_size, 0);
/*
@@ -1639,7 +1681,7 @@ static int read_page_ecc(struct qcom_nand_host *host, u8 *data_buf,
for (j = 0; j < host->bbm_size; j++)
*oob_buf++ = 0xff;
- read_data_dma(nandc, FLASH_BUF_ACC + data_size,
+ read_data_dma(nandc, NANDC_FLASH_BUF(nandc) + data_size,
oob_buf, oob_size, 0);
}
@@ -1683,7 +1725,8 @@ static int copy_last_cw(struct qcom_nand_host *host, int page)
config_nand_single_cw_page_read(nandc);
- read_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer, size, 0);
+ read_data_dma(nandc, NANDC_FLASH_BUF(nandc), nandc->data_buffer,
+ size, 0);
ret = submit_descs(nandc);
if (ret)
@@ -1739,7 +1782,7 @@ static int qcom_nandc_read_page_raw(struct mtd_info *mtd,
for (i = 0; i < ecc->steps; i++) {
int data_size1, data_size2, oob_size1, oob_size2;
- int reg_off = FLASH_BUF_ACC;
+ int reg_off = NANDC_FLASH_BUF(nandc);
data_size1 = mtd->writesize - host->cw_size * (ecc->steps - 1);
oob_size1 = host->bbm_size;
@@ -1851,7 +1894,8 @@ static int qcom_nandc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
}
- write_data_dma(nandc, FLASH_BUF_ACC, data_buf, data_size,
+ write_data_dma(nandc, NANDC_FLASH_BUF(nandc), data_buf,
+ data_size,
i == (ecc->steps - 1) ? NAND_BAM_NO_EOT : 0);
/*
@@ -1864,8 +1908,8 @@ static int qcom_nandc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
if (i == (ecc->steps - 1)) {
oob_buf += host->bbm_size;
- write_data_dma(nandc, FLASH_BUF_ACC + data_size,
- oob_buf, oob_size, 0);
+ write_data_dma(nandc, NANDC_FLASH_BUF(nandc) +
+ data_size, oob_buf, oob_size, 0);
}
config_nand_cw_write(nandc);
@@ -1906,7 +1950,7 @@ static int qcom_nandc_write_page_raw(struct mtd_info *mtd,
for (i = 0; i < ecc->steps; i++) {
int data_size1, data_size2, oob_size1, oob_size2;
- int reg_off = FLASH_BUF_ACC;
+ int reg_off = NANDC_FLASH_BUF(nandc);
data_size1 = mtd->writesize - host->cw_size * (ecc->steps - 1);
oob_size1 = host->bbm_size;
@@ -1992,7 +2036,7 @@ static int qcom_nandc_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
update_rw_regs(host, 1, false);
config_nand_page_write(nandc);
- write_data_dma(nandc, FLASH_BUF_ACC,
+ write_data_dma(nandc, NANDC_FLASH_BUF(nandc),
nandc->data_buffer, data_size + oob_size, 0);
config_nand_cw_write(nandc);
@@ -2079,7 +2123,7 @@ static int qcom_nandc_block_markbad(struct mtd_info *mtd, loff_t ofs)
update_rw_regs(host, 1, false);
config_nand_page_write(nandc);
- write_data_dma(nandc, FLASH_BUF_ACC,
+ write_data_dma(nandc, NANDC_FLASH_BUF(nandc),
nandc->data_buffer, host->cw_size, 0);
config_nand_cw_write(nandc);
@@ -2838,11 +2882,13 @@ static int qcom_nandc_remove(struct platform_device *pdev)
static const struct qcom_props ebi2_nandc_data = {
.ecc_modes = (ECC_RS_4BIT | ECC_BCH_8BIT),
.is_bam = false,
+ .reg_offsets = nandc_reg_offsets,
};
static const struct qcom_props qpic_nandc_v1_4_0_data = {
.ecc_modes = (ECC_BCH_4BIT | ECC_BCH_8BIT),
.is_bam = true,
+ .reg_offsets = nandc_reg_offsets,
};
/*
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
[toc] | [prev] | [next] | [standalone]
| From | Abhishek Sahu <absahu@codeaurora.org> |
|---|---|
| Date | 2017-07-19 14:00 +0200 |
| Subject | [PATCH v2 20/25] mtd: nand: qcom: erased codeword detection configuration |
| Message-ID | <u4VO1-85k-9@gated-at.bofh.it> |
| In reply to | #1691591 |
The NAND controller returns ECC failure during read of completely
erased codeword. The NAND controller has hardware functionality
to detect erased codeword in case of BCH ECC algorithm. The
NAND_ERASED_CW_DETECT_CFG register controls the Erased
Codeword/Page detection controller. This register should be reset
before every page read by setting and clearing bit 0 of
NAND_ERASED_CW_DETECT_CFG.
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
---
drivers/mtd/nand/qcom_nandc.c | 23 ++++++++++++++++++++++-
1 file changed, 22 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
index b9e0eec..89f6a89 100644
--- a/drivers/mtd/nand/qcom_nandc.c
+++ b/drivers/mtd/nand/qcom_nandc.c
@@ -196,6 +196,11 @@
#define NAND_BAM_NWD BIT(1)
/* Finish writing in the current sgl and start writing in another sgl */
#define NAND_BAM_NEXT_SGL BIT(2)
+/*
+ * Erased codeword status is being used two times in single transfer so this
+ * flag will determine the current value of erased codeword status register
+ */
+#define NAND_ERASED_CW_SET BIT(4)
/*
* This data type corresponds to the BAM transaction which will be used for all
@@ -279,6 +284,8 @@ struct nandc_regs {
__le32 read_location2;
__le32 read_location3;
+ __le32 erased_cw_detect_cfg_clr;
+ __le32 erased_cw_detect_cfg_set;
};
/*
@@ -815,6 +822,13 @@ static int write_reg_dma(struct qcom_nand_controller *nandc, int first,
if (first == NAND_FLASH_CMD)
flow_control = true;
+ if (first == NAND_ERASED_CW_DETECT_CFG) {
+ if (flags & NAND_ERASED_CW_SET)
+ vaddr = ®s->erased_cw_detect_cfg_set;
+ else
+ vaddr = ®s->erased_cw_detect_cfg_clr;
+ }
+
if (first == NAND_EXEC_CMD)
flags |= NAND_BAM_NWD;
@@ -867,6 +881,9 @@ static void config_nand_page_read(struct qcom_nand_controller *nandc)
write_reg_dma(nandc, NAND_ADDR0, 2, 0);
write_reg_dma(nandc, NAND_DEV0_CFG0, 3, 0);
write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1, 0);
+ write_reg_dma(nandc, NAND_ERASED_CW_DETECT_CFG, 1, 0);
+ write_reg_dma(nandc, NAND_ERASED_CW_DETECT_CFG, 1,
+ NAND_ERASED_CW_SET | NAND_BAM_NEXT_SGL);
}
/*
@@ -2268,9 +2285,13 @@ static int qcom_nand_host_setup(struct qcom_nand_host *host)
host->clrflashstatus = FS_READY_BSY_N;
host->clrreadstatus = 0xc0;
+ nandc->regs->erased_cw_detect_cfg_clr =
+ cpu_to_le32(CLR_ERASED_PAGE_DET);
+ nandc->regs->erased_cw_detect_cfg_set =
+ cpu_to_le32(SET_ERASED_PAGE_DET);
dev_dbg(nandc->dev,
- "cfg0 %x cfg1 %x ecc_buf_cfg %x ecc_bch cfg %x cw_size %d cw_data %d strength %d parity_bytes %d steps %d\n",
+ "cfg0 %x cfg1 %x ecc_buf_cfg %x ecc_bch cfg %x cw_size %d cw_data %d strength %d parity_bytes %d steps %d\n",
host->cfg0, host->cfg1, host->ecc_buf_cfg, host->ecc_bch_cfg,
host->cw_size, host->cw_data, ecc->strength, ecc->bytes,
cwperpage);
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
[toc] | [prev] | [next] | [standalone]
| From | Abhishek Sahu <absahu@codeaurora.org> |
|---|---|
| Date | 2017-07-19 14:00 +0200 |
| Subject | [PATCH v2 08/25] mtd: nand: qcom: reorganize nand page write |
| Message-ID | <u4VO2-85k-13@gated-at.bofh.it> |
| In reply to | #1691591 |
Each NAND page consist of multiple codewords. Following is
sequence for NAND page write according to hardware guide.
1. Program Power-up configuration, page row, page column
address and flash configuration registers.
2. Write NAND_FLASH_CMD followed by NANC_EXEC_CMD for each
codeword.
3. Read NAND_FLASH_STATUS for each codeword.
The step 1 should be done once for each page and step 2,3 should
be done for each codeword.
Currently, all the 3 steps are being done for each codeword which
is wrong. Now this patch reorganizes page write functions to
configure page specific register once and per codeword specific
registers for each NAND ECC step.
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
---
drivers/mtd/nand/qcom_nandc.c | 32 ++++++++++++++++++++------------
1 file changed, 20 insertions(+), 12 deletions(-)
diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
index 27ea594..5b71478 100644
--- a/drivers/mtd/nand/qcom_nandc.c
+++ b/drivers/mtd/nand/qcom_nandc.c
@@ -638,15 +638,24 @@ static void config_nand_single_cw_page_read(struct qcom_nand_controller *nandc)
config_nand_cw_read(nandc);
}
-static void config_cw_write_pre(struct qcom_nand_controller *nandc)
+/*
+ * Helper to prepare DMA descriptors used to configure registers needed for
+ * before writing a NAND page.
+ */
+static void config_nand_page_write(struct qcom_nand_controller *nandc)
{
- write_reg_dma(nandc, NAND_FLASH_CMD, 3);
+ write_reg_dma(nandc, NAND_ADDR0, 2);
write_reg_dma(nandc, NAND_DEV0_CFG0, 3);
write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1);
}
-static void config_cw_write_post(struct qcom_nand_controller *nandc)
+/*
+ * Helper to prepare DMA descriptors for configuring registers
+ * before writing each codeword in NAND page.
+ */
+static void config_nand_cw_write(struct qcom_nand_controller *nandc)
{
+ write_reg_dma(nandc, NAND_FLASH_CMD, 1);
write_reg_dma(nandc, NAND_EXEC_CMD, 1);
read_reg_dma(nandc, NAND_FLASH_STATUS, 1);
@@ -1329,6 +1338,7 @@ static int qcom_nandc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
host->use_ecc = true;
update_rw_regs(host, ecc->steps, false);
+ config_nand_page_write(nandc);
for (i = 0; i < ecc->steps; i++) {
int data_size, oob_size;
@@ -1342,7 +1352,6 @@ static int qcom_nandc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
oob_size = ecc->bytes;
}
- config_cw_write_pre(nandc);
write_data_dma(nandc, FLASH_BUF_ACC, data_buf, data_size);
@@ -1360,7 +1369,7 @@ static int qcom_nandc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
oob_buf, oob_size);
}
- config_cw_write_post(nandc);
+ config_nand_cw_write(nandc);
data_buf += data_size;
oob_buf += oob_size;
@@ -1393,6 +1402,7 @@ static int qcom_nandc_write_page_raw(struct mtd_info *mtd,
host->use_ecc = false;
update_rw_regs(host, ecc->steps, false);
+ config_nand_page_write(nandc);
for (i = 0; i < ecc->steps; i++) {
int data_size1, data_size2, oob_size1, oob_size2;
@@ -1411,8 +1421,6 @@ static int qcom_nandc_write_page_raw(struct mtd_info *mtd,
oob_size2 = host->ecc_bytes_hw + host->spare_bytes;
}
- config_cw_write_pre(nandc);
-
write_data_dma(nandc, reg_off, data_buf, data_size1);
reg_off += data_size1;
data_buf += data_size1;
@@ -1428,7 +1436,7 @@ static int qcom_nandc_write_page_raw(struct mtd_info *mtd,
write_data_dma(nandc, reg_off, oob_buf, oob_size2);
oob_buf += oob_size2;
- config_cw_write_post(nandc);
+ config_nand_cw_write(nandc);
}
ret = submit_descs(nandc);
@@ -1478,10 +1486,10 @@ static int qcom_nandc_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
set_address(host, host->cw_size * (ecc->steps - 1), page);
update_rw_regs(host, 1, false);
- config_cw_write_pre(nandc);
+ config_nand_page_write(nandc);
write_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer,
data_size + oob_size);
- config_cw_write_post(nandc);
+ config_nand_cw_write(nandc);
ret = submit_descs(nandc);
@@ -1563,9 +1571,9 @@ static int qcom_nandc_block_markbad(struct mtd_info *mtd, loff_t ofs)
set_address(host, host->cw_size * (ecc->steps - 1), page);
update_rw_regs(host, 1, false);
- config_cw_write_pre(nandc);
+ config_nand_page_write(nandc);
write_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer, host->cw_size);
- config_cw_write_post(nandc);
+ config_nand_cw_write(nandc);
ret = submit_descs(nandc);
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
[toc] | [prev] | [next] | [standalone]
| From | Abhishek Sahu <absahu@codeaurora.org> |
|---|---|
| Date | 2017-07-19 14:00 +0200 |
| Subject | [PATCH v2 18/25] mtd: nand: qcom: support for passing flags in transfer functions |
| Message-ID | <u4VO1-85k-11@gated-at.bofh.it> |
| In reply to | #1691591 |
The BAM has multiple flags to control the transfer. This patch
adds flags parameter in register and data transfer functions and
modifies all these function call with appropriate flags.
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
---
drivers/mtd/nand/qcom_nandc.c | 120 ++++++++++++++++++++++++------------------
1 file changed, 68 insertions(+), 52 deletions(-)
diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
index 589108b..8a6034f 100644
--- a/drivers/mtd/nand/qcom_nandc.c
+++ b/drivers/mtd/nand/qcom_nandc.c
@@ -177,6 +177,14 @@
#define QPIC_PER_CW_CMD_SGL 32
#define QPIC_PER_CW_DATA_SGL 8
+/* Flags used for BAM DMA desc preparation*/
+/* Don't set the EOT in current tx sgl */
+#define NAND_BAM_NO_EOT BIT(0)
+/* Set the NWD flag in current sgl */
+#define NAND_BAM_NWD BIT(1)
+/* Finish writing in the current sgl and start writing in another sgl */
+#define NAND_BAM_NEXT_SGL BIT(2)
+
/*
* This data type corresponds to the BAM transaction which will be used for all
* NAND transfers.
@@ -735,7 +743,7 @@ static int prep_adm_dma_desc(struct qcom_nand_controller *nandc, bool read,
* @num_regs: number of registers to read
*/
static int read_reg_dma(struct qcom_nand_controller *nandc, int first,
- int num_regs)
+ int num_regs, unsigned int flags)
{
bool flow_control = false;
void *vaddr;
@@ -759,7 +767,7 @@ static int read_reg_dma(struct qcom_nand_controller *nandc, int first,
* @num_regs: number of registers to write
*/
static int write_reg_dma(struct qcom_nand_controller *nandc, int first,
- int num_regs)
+ int num_regs, unsigned int flags)
{
bool flow_control = false;
struct nandc_regs *regs = nandc->regs;
@@ -771,6 +779,9 @@ static int write_reg_dma(struct qcom_nand_controller *nandc, int first,
if (first == NAND_FLASH_CMD)
flow_control = true;
+ if (first == NAND_EXEC_CMD)
+ flags |= NAND_BAM_NWD;
+
if (first == NAND_DEV_CMD1_RESTORE)
first = NAND_DEV_CMD1;
@@ -792,7 +803,7 @@ static int write_reg_dma(struct qcom_nand_controller *nandc, int first,
* @size: DMA transaction size in bytes
*/
static int read_data_dma(struct qcom_nand_controller *nandc, int reg_off,
- const u8 *vaddr, int size)
+ const u8 *vaddr, int size, unsigned int flags)
{
return prep_adm_dma_desc(nandc, true, reg_off, vaddr, size, false);
}
@@ -806,7 +817,7 @@ static int read_data_dma(struct qcom_nand_controller *nandc, int reg_off,
* @size: DMA transaction size in bytes
*/
static int write_data_dma(struct qcom_nand_controller *nandc, int reg_off,
- const u8 *vaddr, int size)
+ const u8 *vaddr, int size, unsigned int flags)
{
return prep_adm_dma_desc(nandc, false, reg_off, vaddr, size, false);
}
@@ -817,9 +828,9 @@ static int write_data_dma(struct qcom_nand_controller *nandc, int reg_off,
*/
static void config_nand_page_read(struct qcom_nand_controller *nandc)
{
- write_reg_dma(nandc, NAND_ADDR0, 2);
- write_reg_dma(nandc, NAND_DEV0_CFG0, 3);
- write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1);
+ write_reg_dma(nandc, NAND_ADDR0, 2, 0);
+ write_reg_dma(nandc, NAND_DEV0_CFG0, 3, 0);
+ write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1, 0);
}
/*
@@ -828,11 +839,12 @@ static void config_nand_page_read(struct qcom_nand_controller *nandc)
*/
static void config_nand_cw_read(struct qcom_nand_controller *nandc)
{
- write_reg_dma(nandc, NAND_FLASH_CMD, 1);
- write_reg_dma(nandc, NAND_EXEC_CMD, 1);
+ write_reg_dma(nandc, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL);
+ write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
- read_reg_dma(nandc, NAND_FLASH_STATUS, 2);
- read_reg_dma(nandc, NAND_ERASED_CW_DETECT_STATUS, 1);
+ read_reg_dma(nandc, NAND_FLASH_STATUS, 2, 0);
+ read_reg_dma(nandc, NAND_ERASED_CW_DETECT_STATUS, 1,
+ NAND_BAM_NEXT_SGL);
}
/*
@@ -851,9 +863,10 @@ static void config_nand_single_cw_page_read(struct qcom_nand_controller *nandc)
*/
static void config_nand_page_write(struct qcom_nand_controller *nandc)
{
- write_reg_dma(nandc, NAND_ADDR0, 2);
- write_reg_dma(nandc, NAND_DEV0_CFG0, 3);
- write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1);
+ write_reg_dma(nandc, NAND_ADDR0, 2, 0);
+ write_reg_dma(nandc, NAND_DEV0_CFG0, 3, 0);
+ write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1,
+ NAND_BAM_NEXT_SGL);
}
/*
@@ -862,13 +875,13 @@ static void config_nand_page_write(struct qcom_nand_controller *nandc)
*/
static void config_nand_cw_write(struct qcom_nand_controller *nandc)
{
- write_reg_dma(nandc, NAND_FLASH_CMD, 1);
- write_reg_dma(nandc, NAND_EXEC_CMD, 1);
+ write_reg_dma(nandc, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL);
+ write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
- read_reg_dma(nandc, NAND_FLASH_STATUS, 1);
+ read_reg_dma(nandc, NAND_FLASH_STATUS, 1, NAND_BAM_NEXT_SGL);
- write_reg_dma(nandc, NAND_FLASH_STATUS, 1);
- write_reg_dma(nandc, NAND_READ_STATUS, 1);
+ write_reg_dma(nandc, NAND_FLASH_STATUS, 1, 0);
+ write_reg_dma(nandc, NAND_READ_STATUS, 1, NAND_BAM_NEXT_SGL);
}
/*
@@ -916,8 +929,8 @@ static int nandc_param(struct qcom_nand_host *host)
nandc_set_reg(nandc, NAND_DEV_CMD1_RESTORE, nandc->cmd1);
nandc_set_reg(nandc, NAND_DEV_CMD_VLD_RESTORE, nandc->vld);
- write_reg_dma(nandc, NAND_DEV_CMD_VLD, 1);
- write_reg_dma(nandc, NAND_DEV_CMD1, 1);
+ write_reg_dma(nandc, NAND_DEV_CMD_VLD, 1, 0);
+ write_reg_dma(nandc, NAND_DEV_CMD1, 1, NAND_BAM_NEXT_SGL);
nandc->buf_count = 512;
memset(nandc->data_buffer, 0xff, nandc->buf_count);
@@ -925,11 +938,11 @@ static int nandc_param(struct qcom_nand_host *host)
config_nand_single_cw_page_read(nandc);
read_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer,
- nandc->buf_count);
+ nandc->buf_count, 0);
/* restore CMD1 and VLD regs */
- write_reg_dma(nandc, NAND_DEV_CMD1_RESTORE, 1);
- write_reg_dma(nandc, NAND_DEV_CMD_VLD_RESTORE, 1);
+ write_reg_dma(nandc, NAND_DEV_CMD1_RESTORE, 1, 0);
+ write_reg_dma(nandc, NAND_DEV_CMD_VLD_RESTORE, 1, NAND_BAM_NEXT_SGL);
return 0;
}
@@ -951,14 +964,14 @@ static int erase_block(struct qcom_nand_host *host, int page_addr)
nandc_set_reg(nandc, NAND_FLASH_STATUS, host->clrflashstatus);
nandc_set_reg(nandc, NAND_READ_STATUS, host->clrreadstatus);
- write_reg_dma(nandc, NAND_FLASH_CMD, 3);
- write_reg_dma(nandc, NAND_DEV0_CFG0, 2);
- write_reg_dma(nandc, NAND_EXEC_CMD, 1);
+ write_reg_dma(nandc, NAND_FLASH_CMD, 3, NAND_BAM_NEXT_SGL);
+ write_reg_dma(nandc, NAND_DEV0_CFG0, 2, NAND_BAM_NEXT_SGL);
+ write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
- read_reg_dma(nandc, NAND_FLASH_STATUS, 1);
+ read_reg_dma(nandc, NAND_FLASH_STATUS, 1, NAND_BAM_NEXT_SGL);
- write_reg_dma(nandc, NAND_FLASH_STATUS, 1);
- write_reg_dma(nandc, NAND_READ_STATUS, 1);
+ write_reg_dma(nandc, NAND_FLASH_STATUS, 1, 0);
+ write_reg_dma(nandc, NAND_READ_STATUS, 1, NAND_BAM_NEXT_SGL);
return 0;
}
@@ -978,10 +991,10 @@ static int read_id(struct qcom_nand_host *host, int column)
nandc_set_reg(nandc, NAND_FLASH_CHIP_SELECT, DM_EN);
nandc_set_reg(nandc, NAND_EXEC_CMD, 1);
- write_reg_dma(nandc, NAND_FLASH_CMD, 4);
- write_reg_dma(nandc, NAND_EXEC_CMD, 1);
+ write_reg_dma(nandc, NAND_FLASH_CMD, 4, NAND_BAM_NEXT_SGL);
+ write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
- read_reg_dma(nandc, NAND_READ_ID, 1);
+ read_reg_dma(nandc, NAND_READ_ID, 1, NAND_BAM_NEXT_SGL);
return 0;
}
@@ -995,10 +1008,10 @@ static int reset(struct qcom_nand_host *host)
nandc_set_reg(nandc, NAND_FLASH_CMD, RESET_DEVICE);
nandc_set_reg(nandc, NAND_EXEC_CMD, 1);
- write_reg_dma(nandc, NAND_FLASH_CMD, 1);
- write_reg_dma(nandc, NAND_EXEC_CMD, 1);
+ write_reg_dma(nandc, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL);
+ write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
- read_reg_dma(nandc, NAND_FLASH_STATUS, 1);
+ read_reg_dma(nandc, NAND_FLASH_STATUS, 1, NAND_BAM_NEXT_SGL);
return 0;
}
@@ -1395,7 +1408,7 @@ static int read_page_ecc(struct qcom_nand_host *host, u8 *data_buf,
if (data_buf)
read_data_dma(nandc, FLASH_BUF_ACC, data_buf,
- data_size);
+ data_size, 0);
/*
* when ecc is enabled, the controller doesn't read the real
@@ -1411,7 +1424,7 @@ static int read_page_ecc(struct qcom_nand_host *host, u8 *data_buf,
*oob_buf++ = 0xff;
read_data_dma(nandc, FLASH_BUF_ACC + data_size,
- oob_buf, oob_size);
+ oob_buf, oob_size, 0);
}
if (data_buf)
@@ -1453,7 +1466,7 @@ static int copy_last_cw(struct qcom_nand_host *host, int page)
config_nand_single_cw_page_read(nandc);
- read_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer, size);
+ read_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer, size, 0);
ret = submit_descs(nandc);
if (ret)
@@ -1522,19 +1535,19 @@ static int qcom_nandc_read_page_raw(struct mtd_info *mtd,
config_nand_cw_read(nandc);
- read_data_dma(nandc, reg_off, data_buf, data_size1);
+ read_data_dma(nandc, reg_off, data_buf, data_size1, 0);
reg_off += data_size1;
data_buf += data_size1;
- read_data_dma(nandc, reg_off, oob_buf, oob_size1);
+ read_data_dma(nandc, reg_off, oob_buf, oob_size1, 0);
reg_off += oob_size1;
oob_buf += oob_size1;
- read_data_dma(nandc, reg_off, data_buf, data_size2);
+ read_data_dma(nandc, reg_off, data_buf, data_size2, 0);
reg_off += data_size2;
data_buf += data_size2;
- read_data_dma(nandc, reg_off, oob_buf, oob_size2);
+ read_data_dma(nandc, reg_off, oob_buf, oob_size2, 0);
oob_buf += oob_size2;
}
@@ -1601,7 +1614,8 @@ static int qcom_nandc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
}
- write_data_dma(nandc, FLASH_BUF_ACC, data_buf, data_size);
+ write_data_dma(nandc, FLASH_BUF_ACC, data_buf, data_size,
+ i == (ecc->steps - 1) ? NAND_BAM_NO_EOT : 0);
/*
* when ECC is enabled, we don't really need to write anything
@@ -1614,7 +1628,7 @@ static int qcom_nandc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
oob_buf += host->bbm_size;
write_data_dma(nandc, FLASH_BUF_ACC + data_size,
- oob_buf, oob_size);
+ oob_buf, oob_size, 0);
}
config_nand_cw_write(nandc);
@@ -1669,19 +1683,20 @@ static int qcom_nandc_write_page_raw(struct mtd_info *mtd,
oob_size2 = host->ecc_bytes_hw + host->spare_bytes;
}
- write_data_dma(nandc, reg_off, data_buf, data_size1);
+ write_data_dma(nandc, reg_off, data_buf, data_size1,
+ NAND_BAM_NO_EOT);
reg_off += data_size1;
data_buf += data_size1;
- write_data_dma(nandc, reg_off, oob_buf, oob_size1);
+ write_data_dma(nandc, reg_off, oob_buf, oob_size1, 0);
reg_off += oob_size1;
oob_buf += oob_size1;
- write_data_dma(nandc, reg_off, data_buf, data_size2);
+ write_data_dma(nandc, reg_off, data_buf, data_size2, 0);
reg_off += data_size2;
data_buf += data_size2;
- write_data_dma(nandc, reg_off, oob_buf, oob_size2);
+ write_data_dma(nandc, reg_off, oob_buf, oob_size2, 0);
oob_buf += oob_size2;
config_nand_cw_write(nandc);
@@ -1735,8 +1750,8 @@ static int qcom_nandc_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
update_rw_regs(host, 1, false);
config_nand_page_write(nandc);
- write_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer,
- data_size + oob_size);
+ write_data_dma(nandc, FLASH_BUF_ACC,
+ nandc->data_buffer, data_size + oob_size, 0);
config_nand_cw_write(nandc);
ret = submit_descs(nandc);
@@ -1820,7 +1835,8 @@ static int qcom_nandc_block_markbad(struct mtd_info *mtd, loff_t ofs)
update_rw_regs(host, 1, false);
config_nand_page_write(nandc);
- write_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer, host->cw_size);
+ write_data_dma(nandc, FLASH_BUF_ACC,
+ nandc->data_buffer, host->cw_size, 0);
config_nand_cw_write(nandc);
ret = submit_descs(nandc);
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
[toc] | [prev] | [next] | [standalone]
| From | Abhishek Sahu <absahu@codeaurora.org> |
|---|---|
| Date | 2017-07-19 14:00 +0200 |
| Subject | [PATCH v2 25/25] mtd: nand: qcom: support for QPIC version 1.5.0 |
| Message-ID | <u4VO2-85k-15@gated-at.bofh.it> |
| In reply to | #1691591 |
The current QCOM NAND driver only supports version 1.4.0
QCOM QPIC NAND controller. This patch adds the support for
version 1.5.0 which contains some of the registers at
different offsets. The driver data contains the register offset
field which is being initialized with its corresponding register
offsets array. A new compatible string has been added for
version 1.5.0 in BAM mode which uses version 1.5.0 register
offsets.
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
---
drivers/mtd/nand/qcom_nandc.c | 52 +++++++++++++++++++++++++++++++++++++++----
1 file changed, 48 insertions(+), 4 deletions(-)
diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
index 0896e56..52173f1 100644
--- a/drivers/mtd/nand/qcom_nandc.c
+++ b/drivers/mtd/nand/qcom_nandc.c
@@ -445,8 +445,9 @@ struct qcom_props {
const u32 *reg_offsets;
};
-/* Mapping table which contains the actual register offsets */
-static const u32 nandc_reg_offsets[] = {
+/* Mapping tables which contains the actual register offsets */
+/* NAND controller Version 1.4.0 mapping table */
+static const u32 reg_offsets_v1_4_0[] = {
[NAND_FLASH_CMD] = 0x00,
[NAND_ADDR0] = 0x04,
[NAND_ADDR1] = 0x08,
@@ -479,6 +480,40 @@ struct qcom_props {
[NAND_READ_LOCATION_3] = 0xf2c,
};
+/* NAND controller Version 1.5.0 mapping table */
+static const u32 reg_offsets_v1_5_0[] = {
+ [NAND_FLASH_CMD] = 0x00,
+ [NAND_ADDR0] = 0x04,
+ [NAND_ADDR1] = 0x08,
+ [NAND_FLASH_CHIP_SELECT] = 0x0c,
+ [NAND_EXEC_CMD] = 0x10,
+ [NAND_FLASH_STATUS] = 0x14,
+ [NAND_BUFFER_STATUS] = 0x18,
+ [NAND_DEV0_CFG0] = 0x20,
+ [NAND_DEV0_CFG1] = 0x24,
+ [NAND_DEV0_ECC_CFG] = 0x28,
+ [NAND_DEV1_ECC_CFG] = 0x2c,
+ [NAND_DEV1_CFG0] = 0x30,
+ [NAND_DEV1_CFG1] = 0x34,
+ [NAND_READ_ID] = 0x40,
+ [NAND_READ_STATUS] = 0x44,
+ [NAND_DEV_CMD0] = 0x70a0,
+ [NAND_DEV_CMD1] = 0x70a4,
+ [NAND_DEV_CMD2] = 0x70a8,
+ [NAND_DEV_CMD_VLD] = 0x70ac,
+ [SFLASHC_BURST_CFG] = 0xe0,
+ [NAND_ERASED_CW_DETECT_CFG] = 0xe8,
+ [NAND_ERASED_CW_DETECT_STATUS] = 0xec,
+ [NAND_EBI2_ECC_BUF_CFG] = 0xf0,
+ [FLASH_BUF_ACC] = 0x100,
+ [NAND_CTRL] = 0xf00,
+ [NAND_VERSION] = 0x4f08,
+ [NAND_READ_LOCATION_0] = 0xf20,
+ [NAND_READ_LOCATION_1] = 0xf24,
+ [NAND_READ_LOCATION_2] = 0xf28,
+ [NAND_READ_LOCATION_3] = 0xf2c,
+};
+
/* Frees the BAM transaction memory */
static void free_bam_transaction(struct qcom_nand_controller *nandc)
{
@@ -2882,13 +2917,19 @@ static int qcom_nandc_remove(struct platform_device *pdev)
static const struct qcom_props ebi2_nandc_data = {
.ecc_modes = (ECC_RS_4BIT | ECC_BCH_8BIT),
.is_bam = false,
- .reg_offsets = nandc_reg_offsets,
+ .reg_offsets = reg_offsets_v1_4_0,
};
static const struct qcom_props qpic_nandc_v1_4_0_data = {
.ecc_modes = (ECC_BCH_4BIT | ECC_BCH_8BIT),
.is_bam = true,
- .reg_offsets = nandc_reg_offsets,
+ .reg_offsets = reg_offsets_v1_4_0,
+};
+
+static const struct qcom_props qpic_nandc_v1_5_0_data = {
+ .ecc_modes = (ECC_BCH_4BIT | ECC_BCH_8BIT),
+ .is_bam = true,
+ .reg_offsets = reg_offsets_v1_5_0,
};
/*
@@ -2902,6 +2943,9 @@ static int qcom_nandc_remove(struct platform_device *pdev)
{ .compatible = "qcom,qpic-nandc-v1.4.0",
.data = &qpic_nandc_v1_4_0_data,
},
+ { .compatible = "qcom,qpic-nandc-v1.5.0",
+ .data = (void *)&qpic_nandc_v1_5_0_data,
+ },
{}
};
MODULE_DEVICE_TABLE(of, qcom_nandc_of_match);
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
[toc] | [prev] | [next] | [standalone]
| From | Abhishek Sahu <absahu@codeaurora.org> |
|---|---|
| Date | 2017-07-19 14:00 +0200 |
| Subject | [PATCH v2 22/25] mtd: nand: qcom: QPIC raw write support |
| Message-ID | <u4VO2-85k-21@gated-at.bofh.it> |
| In reply to | #1691591 |
BAM requires EOT flag should be set only for the last data write in a codeword. Signed-off-by: Abhishek Sahu <absahu@codeaurora.org> --- drivers/mtd/nand/qcom_nandc.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c index d0e7b9f..7a7db6b 100644 --- a/drivers/mtd/nand/qcom_nandc.c +++ b/drivers/mtd/nand/qcom_nandc.c @@ -1926,11 +1926,13 @@ static int qcom_nandc_write_page_raw(struct mtd_info *mtd, reg_off += data_size1; data_buf += data_size1; - write_data_dma(nandc, reg_off, oob_buf, oob_size1, 0); + write_data_dma(nandc, reg_off, oob_buf, oob_size1, + NAND_BAM_NO_EOT); reg_off += oob_size1; oob_buf += oob_size1; - write_data_dma(nandc, reg_off, data_buf, data_size2, 0); + write_data_dma(nandc, reg_off, data_buf, data_size2, + NAND_BAM_NO_EOT); reg_off += data_size2; data_buf += data_size2; -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
[toc] | [prev] | [next] | [standalone]
| From | Abhishek Sahu <absahu@codeaurora.org> |
|---|---|
| Date | 2017-07-19 14:00 +0200 |
| Subject | [PATCH v2 12/25] dt-bindings: qcom_nandc: QPIC NAND documentation |
| Message-ID | <u4VO2-85k-23@gated-at.bofh.it> |
| In reply to | #1691591 |
1. QPIC NAND will use compatible string "qcom,qpic-nandc-v1.4.0"
2. QPIC NAND will 3 BAM channels: command, data tx and data rx
while EBI2 NAND uses only single ADM channel.
3. CRCI is only required for ADM DMA and its not required for
QPIC NAND.
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
---
.../devicetree/bindings/mtd/qcom_nandc.txt | 54 ++++++++++++++++++++--
1 file changed, 51 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
index b24adfe..8efaeb0 100644
--- a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
+++ b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
@@ -1,13 +1,15 @@
* Qualcomm NAND controller
Required properties:
-- compatible: should be "qcom,ebi2-nandc" - EBI2 NAND which uses ADM
- DMA like IPQ8064.
-
+- compatible: must be one of the following:
+ * "qcom,ebi2-nandc" - EBI2 NAND which uses ADM DMA like IPQ8064.
+ * "qcom,qpic-nandc-v1.4.0" - QPIC NAND v1.4.0 which uses BAM DMA like IPQ4019.
- reg: MMIO address range
- clocks: must contain core clock and always on clock
- clock-names: must contain "core" for the core clock and "aon" for the
always on clock
+
+EBI2 specific properties:
- dmas: DMA specifier, consisting of a phandle to the ADM DMA
controller node and the channel number to be used for
NAND. Refer to dma.txt and qcom_adm.txt for more details
@@ -18,6 +20,12 @@ Required properties:
- qcom,data-crci: must contain the ADM data type CRCI block instance
number specified for the NAND controller on the given
platform
+
+QPIC specific properties:
+- dmas: DMA specifier, consisting of a phandle to the BAM DMA
+ and the channel number to be used for NAND. Refer to
+ dma.txt, qcom_bam_dma.txt for more details
+- dma-names: must contain all 3 channel names : "tx", "rx", "cmd"
- #address-cells: <1> - subnodes give the chip-select number
- #size-cells: <0>
@@ -84,3 +92,43 @@ nand@1ac00000 {
};
};
};
+
+nand@79b0000 {
+ compatible = "qcom,qpic-nandc-v1.4.0";
+ reg = <0x79b0000 0x1000>;
+
+ clocks = <&gcc GCC_QPIC_CLK>,
+ <&gcc GCC_QPIC_AHB_CLK>;
+ clock-names = "core", "aon";
+
+ dmas = <&qpicbam 0>,
+ <&qpicbam 1>,
+ <&qpicbam 2>;
+ dma-names = "tx", "rx", "cmd";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ nandcs@0 {
+ reg = <0>;
+ nand-ecc-strength = <4>;
+ nand-ecc-step-size = <512>;
+ nand-bus-width = <8>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "boot-nand";
+ reg = <0 0x58a0000>;
+ };
+
+ partition@58a0000 {
+ label = "fs-nand";
+ reg = <0x58a0000 0x4000000>;
+ };
+ };
+ };
+};
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
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| From | Boris Brezillon <boris.brezillon@free-electrons.com> |
|---|---|
| Date | 2017-07-19 21:40 +0200 |
| Subject | Re: [PATCH v2 12/25] dt-bindings: qcom_nandc: QPIC NAND documentation |
| Message-ID | <u52Zc-4Fq-5@gated-at.bofh.it> |
| In reply to | #1691603 |
On Wed, 19 Jul 2017 17:18:00 +0530
Abhishek Sahu <absahu@codeaurora.org> wrote:
> 1. QPIC NAND will use compatible string "qcom,qpic-nandc-v1.4.0"
> 2. QPIC NAND will 3 BAM channels: command, data tx and data rx
> while EBI2 NAND uses only single ADM channel.
> 3. CRCI is only required for ADM DMA and its not required for
> QPIC NAND.
>
> Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
> ---
> .../devicetree/bindings/mtd/qcom_nandc.txt | 54 ++++++++++++++++++++--
> 1 file changed, 51 insertions(+), 3 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
> index b24adfe..8efaeb0 100644
> --- a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
> +++ b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
> @@ -1,13 +1,15 @@
> * Qualcomm NAND controller
>
> Required properties:
> -- compatible: should be "qcom,ebi2-nandc" - EBI2 NAND which uses ADM
> - DMA like IPQ8064.
> -
> +- compatible: must be one of the following:
> + * "qcom,ebi2-nandc" - EBI2 NAND which uses ADM DMA like IPQ8064.
> + * "qcom,qpic-nandc-v1.4.0" - QPIC NAND v1.4.0 which uses BAM DMA like IPQ4019.
> - reg: MMIO address range
> - clocks: must contain core clock and always on clock
> - clock-names: must contain "core" for the core clock and "aon" for the
> always on clock
> +
> +EBI2 specific properties:
> - dmas: DMA specifier, consisting of a phandle to the ADM DMA
> controller node and the channel number to be used for
> NAND. Refer to dma.txt and qcom_adm.txt for more details
> @@ -18,6 +20,12 @@ Required properties:
> - qcom,data-crci: must contain the ADM data type CRCI block instance
> number specified for the NAND controller on the given
> platform
> +
> +QPIC specific properties:
> +- dmas: DMA specifier, consisting of a phandle to the BAM DMA
> + and the channel number to be used for NAND. Refer to
> + dma.txt, qcom_bam_dma.txt for more details
> +- dma-names: must contain all 3 channel names : "tx", "rx", "cmd"
> - #address-cells: <1> - subnodes give the chip-select number
> - #size-cells: <0>
>
> @@ -84,3 +92,43 @@ nand@1ac00000 {
> };
> };
> };
> +
> +nand@79b0000 {
I think I already mentioned I'd prefer to have
nand-controller@xxxx {
> + compatible = "qcom,qpic-nandc-v1.4.0";
> + reg = <0x79b0000 0x1000>;
> +
> + clocks = <&gcc GCC_QPIC_CLK>,
> + <&gcc GCC_QPIC_AHB_CLK>;
> + clock-names = "core", "aon";
> +
> + dmas = <&qpicbam 0>,
> + <&qpicbam 1>,
> + <&qpicbam 2>;
> + dma-names = "tx", "rx", "cmd";
> +
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + nandcs@0 {
and
nand@x {
here.
> + reg = <0>;
> + nand-ecc-strength = <4>;
> + nand-ecc-step-size = <512>;
> + nand-bus-width = <8>;
> +
> + partitions {
> + compatible = "fixed-partitions";
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + partition@0 {
> + label = "boot-nand";
> + reg = <0 0x58a0000>;
> + };
> +
> + partition@58a0000 {
> + label = "fs-nand";
> + reg = <0x58a0000 0x4000000>;
> + };
> + };
> + };
> +};
[toc] | [prev] | [next] | [standalone]
| From | Abhishek Sahu <absahu@codeaurora.org> |
|---|---|
| Date | 2017-07-20 07:40 +0200 |
| Subject | Re: [PATCH v2 12/25] dt-bindings: qcom_nandc: QPIC NAND documentation |
| Message-ID | <u5clR-2N9-19@gated-at.bofh.it> |
| In reply to | #1692142 |
On 2017-07-20 01:09, Boris Brezillon wrote:
> On Wed, 19 Jul 2017 17:18:00 +0530
> Abhishek Sahu <absahu@codeaurora.org> wrote:
>
>> 1. QPIC NAND will use compatible string "qcom,qpic-nandc-v1.4.0"
>> 2. QPIC NAND will 3 BAM channels: command, data tx and data rx
>> while EBI2 NAND uses only single ADM channel.
>> 3. CRCI is only required for ADM DMA and its not required for
>> QPIC NAND.
>>
>> Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
>> ---
>> .../devicetree/bindings/mtd/qcom_nandc.txt | 54
>> ++++++++++++++++++++--
>> 1 file changed, 51 insertions(+), 3 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
>> b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
>> index b24adfe..8efaeb0 100644
>> --- a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
>> +++ b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
>> @@ -1,13 +1,15 @@
>> * Qualcomm NAND controller
>>
>> Required properties:
>> -- compatible: should be "qcom,ebi2-nandc" - EBI2 NAND which uses ADM
>> - DMA like IPQ8064.
>> -
>> +- compatible: must be one of the following:
>> + * "qcom,ebi2-nandc" - EBI2 NAND which uses ADM DMA like IPQ8064.
>> + * "qcom,qpic-nandc-v1.4.0" - QPIC NAND v1.4.0 which uses BAM DMA
>> like IPQ4019.
>> - reg: MMIO address range
>> - clocks: must contain core clock and always on clock
>> - clock-names: must contain "core" for the core clock and "aon" for
>> the
>> always on clock
>> +
>> +EBI2 specific properties:
>> - dmas: DMA specifier, consisting of a phandle to the ADM DMA
>> controller node and the channel number to be used for
>> NAND. Refer to dma.txt and qcom_adm.txt for more details
>> @@ -18,6 +20,12 @@ Required properties:
>> - qcom,data-crci: must contain the ADM data type CRCI block instance
>> number specified for the NAND controller on the given
>> platform
>> +
>> +QPIC specific properties:
>> +- dmas: DMA specifier, consisting of a phandle to the BAM DMA
>> + and the channel number to be used for NAND. Refer to
>> + dma.txt, qcom_bam_dma.txt for more details
>> +- dma-names: must contain all 3 channel names : "tx", "rx", "cmd"
>> - #address-cells: <1> - subnodes give the chip-select number
>> - #size-cells: <0>
>>
>> @@ -84,3 +92,43 @@ nand@1ac00000 {
>> };
>> };
>> };
>> +
>> +nand@79b0000 {
>
> I think I already mentioned I'd prefer to have
>
> nand-controller@xxxx {
>
Sorry. I Missed that part. I will change it in v3.
>> + compatible = "qcom,qpic-nandc-v1.4.0";
>> + reg = <0x79b0000 0x1000>;
>> +
>> + clocks = <&gcc GCC_QPIC_CLK>,
>> + <&gcc GCC_QPIC_AHB_CLK>;
>> + clock-names = "core", "aon";
>> +
>> + dmas = <&qpicbam 0>,
>> + <&qpicbam 1>,
>> + <&qpicbam 2>;
>> + dma-names = "tx", "rx", "cmd";
>> +
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + nandcs@0 {
>
> and
> nand@x {
>
> here.
>
Will change this also.
>> + reg = <0>;
>> + nand-ecc-strength = <4>;
>> + nand-ecc-step-size = <512>;
>> + nand-bus-width = <8>;
>> +
>> + partitions {
>> + compatible = "fixed-partitions";
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> +
>> + partition@0 {
>> + label = "boot-nand";
>> + reg = <0 0x58a0000>;
>> + };
>> +
>> + partition@58a0000 {
>> + label = "fs-nand";
>> + reg = <0x58a0000 0x4000000>;
>> + };
>> + };
>> + };
>> +};
--
Abhishek Sahu
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| From | Rob Herring <robh@kernel.org> |
|---|---|
| Date | 2017-07-24 21:20 +0200 |
| Subject | Re: [PATCH v2 12/25] dt-bindings: qcom_nandc: QPIC NAND documentation |
| Message-ID | <u6R3z-KM-5@gated-at.bofh.it> |
| In reply to | #1691603 |
On Wed, Jul 19, 2017 at 05:18:00PM +0530, Abhishek Sahu wrote: > 1. QPIC NAND will use compatible string "qcom,qpic-nandc-v1.4.0" > 2. QPIC NAND will 3 BAM channels: command, data tx and data rx > while EBI2 NAND uses only single ADM channel. > 3. CRCI is only required for ADM DMA and its not required for > QPIC NAND. > > Signed-off-by: Abhishek Sahu <absahu@codeaurora.org> > --- > .../devicetree/bindings/mtd/qcom_nandc.txt | 54 ++++++++++++++++++++-- > 1 file changed, 51 insertions(+), 3 deletions(-) > > diff --git a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt > index b24adfe..8efaeb0 100644 > --- a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt > +++ b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt > @@ -1,13 +1,15 @@ > * Qualcomm NAND controller > > Required properties: > -- compatible: should be "qcom,ebi2-nandc" - EBI2 NAND which uses ADM > - DMA like IPQ8064. > - > +- compatible: must be one of the following: > + * "qcom,ebi2-nandc" - EBI2 NAND which uses ADM DMA like IPQ8064. > + * "qcom,qpic-nandc-v1.4.0" - QPIC NAND v1.4.0 which uses BAM DMA like IPQ4019. Looks like you have 2 SoCs and 2 versions of h/w. Use SoC specific compatible strings. Rob
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| From | Abhishek Sahu <absahu@codeaurora.org> |
|---|---|
| Date | 2017-07-25 20:50 +0200 |
| Subject | Re: [PATCH v2 12/25] dt-bindings: qcom_nandc: QPIC NAND documentation |
| Message-ID | <u7d45-6px-1@gated-at.bofh.it> |
| In reply to | #1695013 |
On 2017-07-25 00:47, Rob Herring wrote: > On Wed, Jul 19, 2017 at 05:18:00PM +0530, Abhishek Sahu wrote: >> 1. QPIC NAND will use compatible string "qcom,qpic-nandc-v1.4.0" >> 2. QPIC NAND will 3 BAM channels: command, data tx and data rx >> while EBI2 NAND uses only single ADM channel. >> 3. CRCI is only required for ADM DMA and its not required for >> QPIC NAND. >> >> Signed-off-by: Abhishek Sahu <absahu@codeaurora.org> >> --- >> .../devicetree/bindings/mtd/qcom_nandc.txt | 54 >> ++++++++++++++++++++-- >> 1 file changed, 51 insertions(+), 3 deletions(-) >> >> diff --git a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt >> b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt >> index b24adfe..8efaeb0 100644 >> --- a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt >> +++ b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt >> @@ -1,13 +1,15 @@ >> * Qualcomm NAND controller >> >> Required properties: >> -- compatible: should be "qcom,ebi2-nandc" - EBI2 NAND which uses ADM >> - DMA like IPQ8064. >> - >> +- compatible: must be one of the following: >> + * "qcom,ebi2-nandc" - EBI2 NAND which uses ADM DMA like IPQ8064. >> + * "qcom,qpic-nandc-v1.4.0" - QPIC NAND v1.4.0 which uses BAM DMA >> like IPQ4019. > > Looks like you have 2 SoCs and 2 versions of h/w. Use SoC specific > compatible strings. We have 3 versions of NAND HW currently. EBI2, QPIC version 1.4.0 QPIC version 1.5.0 and multiple Qualcomm SoCs which use any one of these. The original plan was to have compatible string for NAND version since same NAND hardware is being in different SoC and SoC dtsi will simply use its NAND version compatible string like other Qualcomm hardwares http://elixir.free-electrons.com/linux/latest/source/Documentation/devicetree/bindings/dma/qcom_bam_dma.txt http://elixir.free-electrons.com/linux/latest/source/Documentation/devicetree/bindings/spi/qcom,spi-qup.txt > > Rob -- Abhishek Sahu
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| From | Abhishek Sahu <absahu@codeaurora.org> |
|---|---|
| Date | 2017-07-19 14:00 +0200 |
| Subject | [PATCH v2 21/25] mtd: nand: qcom: support for QPIC page read/write |
| Message-ID | <u4VO2-85k-25@gated-at.bofh.it> |
| In reply to | #1691591 |
1. Add the function for command descriptor preparation which
will be used only by BAM DMA and it will form the DMA descriptors
containing command elements.
2. Add the data descriptor preparation function which will be used
only by BAM DMA for forming the data SGL’s.
3. Add clear BAM transaction and call it before every new request
4. Check DMA mode for ADM or BAM and call the appropriate
descriptor formation function.
5. Enable the BAM in NAND_CTRL.
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
---
drivers/mtd/nand/qcom_nandc.c | 197 ++++++++++++++++++++++++++++++++++++++----
1 file changed, 180 insertions(+), 17 deletions(-)
diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
index 89f6a89..d0e7b9f 100644
--- a/drivers/mtd/nand/qcom_nandc.c
+++ b/drivers/mtd/nand/qcom_nandc.c
@@ -156,6 +156,9 @@
#define FETCH_ID 0xb
#define RESET_DEVICE 0xd
+/* NAND_CTRL bits */
+#define BAM_MODE_EN BIT(0)
+
/* Value for NAND_DEV_CMD_VLD */
#define NAND_DEV_CMD_VLD_VAL 0x1d
@@ -185,6 +188,14 @@
(offset << READ_LOCATION_OFFSET) | (size << READ_LOCATION_SIZE) |\
(is_last << READ_LOCATION_LAST))
+/* Returns the dma address for reg read buffer */
+#define REG_BUF_DMA_ADDR(chip, vaddr) \
+ ((chip)->reg_read_buf_phys + \
+ ((uint8_t *)(vaddr) - (uint8_t *)(chip)->reg_read_buf))
+
+/* Returns the NAND register physical address */
+#define NAND_REG_PHYS(chip, offset) ((chip)->base_phys + (offset))
+
#define QPIC_PER_CW_CMD_ELEMENTS 32
#define QPIC_PER_CW_CMD_SGL 32
#define QPIC_PER_CW_DATA_SGL 8
@@ -296,7 +307,8 @@ struct nandc_regs {
* controller
* @dev: parent device
* @base: MMIO base
- * @base_dma: physical base address of controller registers
+ * @base_phys: physical base address of controller registers
+ * @base_dma: dma base address of controller registers
* @core_clk: controller clock
* @aon_clk: another controller clock
*
@@ -329,6 +341,7 @@ struct qcom_nand_controller {
struct device *dev;
void __iomem *base;
+ phys_addr_t base_phys;
dma_addr_t base_dma;
struct clk *core_clk;
@@ -471,6 +484,29 @@ static void free_bam_transaction(struct qcom_nand_controller *nandc)
return bam_txn;
}
+/* Clears the BAM transaction indexes */
+static void clear_bam_transaction(struct qcom_nand_controller *nandc)
+{
+ struct bam_transaction *bam_txn = nandc->bam_txn;
+
+ if (!nandc->props->is_bam)
+ return;
+
+ bam_txn->bam_ce_pos = 0;
+ bam_txn->bam_ce_start = 0;
+ bam_txn->cmd_sgl_pos = 0;
+ bam_txn->cmd_sgl_start = 0;
+ bam_txn->tx_sgl_pos = 0;
+ bam_txn->tx_sgl_start = 0;
+ bam_txn->rx_sgl_pos = 0;
+ bam_txn->rx_sgl_start = 0;
+
+ sg_init_table(bam_txn->cmd_sgl, nandc->max_cwperpage *
+ QPIC_PER_CW_CMD_SGL);
+ sg_init_table(bam_txn->data_sgl, nandc->max_cwperpage *
+ QPIC_PER_CW_DATA_SGL);
+}
+
static inline struct qcom_nand_host *to_qcom_nand_host(struct nand_chip *chip)
{
return container_of(chip, struct qcom_nand_host, chip);
@@ -708,6 +744,101 @@ static int prepare_bam_async_desc(struct qcom_nand_controller *nandc,
return 0;
}
+/*
+ * Prepares the command descriptor for BAM DMA which will be used for NAND
+ * register reads and writes. The command descriptor requires the command
+ * to be formed in command element type so this function uses the command
+ * element from bam transaction ce array and fills the same with required
+ * data. A single SGL can contain multiple command elements so
+ * NAND_BAM_NEXT_SGL will be used for starting the separate SGL
+ * after the current command element.
+ */
+static int prep_bam_dma_desc_cmd(struct qcom_nand_controller *nandc, bool read,
+ int reg_off, const void *vaddr,
+ int size, unsigned int flags)
+{
+ int bam_ce_size;
+ int i, ret;
+ struct bam_cmd_element *bam_ce_buffer;
+ struct bam_transaction *bam_txn = nandc->bam_txn;
+
+ bam_ce_buffer = &bam_txn->bam_ce[bam_txn->bam_ce_pos];
+
+ /* fill the command desc */
+ for (i = 0; i < size; i++) {
+ if (read)
+ bam_prep_ce(&bam_ce_buffer[i],
+ NAND_REG_PHYS(nandc, reg_off + 4 * i),
+ BAM_READ_COMMAND,
+ REG_BUF_DMA_ADDR(nandc,
+ (__le32 *)vaddr + i));
+ else
+ bam_prep_ce_le32(&bam_ce_buffer[i],
+ NAND_REG_PHYS(nandc, reg_off + 4 * i),
+ BAM_WRITE_COMMAND,
+ *((__le32 *)vaddr + i));
+ }
+
+ bam_txn->bam_ce_pos += size;
+
+ /* use the separate sgl after this command */
+ if (flags & NAND_BAM_NEXT_SGL) {
+ bam_ce_buffer = &bam_txn->bam_ce[bam_txn->bam_ce_start];
+ bam_ce_size = (bam_txn->bam_ce_pos -
+ bam_txn->bam_ce_start) *
+ sizeof(struct bam_cmd_element);
+ sg_set_buf(&bam_txn->cmd_sgl[bam_txn->cmd_sgl_pos],
+ bam_ce_buffer, bam_ce_size);
+ bam_txn->cmd_sgl_pos++;
+ bam_txn->bam_ce_start = bam_txn->bam_ce_pos;
+
+ if (flags & NAND_BAM_NWD) {
+ ret = prepare_bam_async_desc(nandc, nandc->cmd_chan,
+ DMA_PREP_FENCE |
+ DMA_PREP_CMD);
+ if (ret)
+ return ret;
+ }
+ }
+
+ return 0;
+}
+
+/*
+ * Prepares the data descriptor for BAM DMA which will be used for NAND
+ * data reads and writes.
+ */
+static int prep_bam_dma_desc_data(struct qcom_nand_controller *nandc, bool read,
+ const void *vaddr,
+ int size, unsigned int flags)
+{
+ int ret;
+ struct bam_transaction *bam_txn = nandc->bam_txn;
+
+ if (read) {
+ sg_set_buf(&bam_txn->data_sgl[bam_txn->rx_sgl_pos],
+ vaddr, size);
+ bam_txn->rx_sgl_pos++;
+ } else {
+ sg_set_buf(&bam_txn->data_sgl[bam_txn->tx_sgl_pos],
+ vaddr, size);
+ bam_txn->tx_sgl_pos++;
+
+ /*
+ * BAM will only set EOT for DMA_PREP_INTERRUPT so if this flag
+ * is not set, form the DMA descriptor
+ */
+ if (!(flags & NAND_BAM_NO_EOT)) {
+ ret = prepare_bam_async_desc(nandc, nandc->tx_chan,
+ DMA_PREP_INTERRUPT);
+ if (ret)
+ return ret;
+ }
+ }
+
+ return 0;
+}
+
static int prep_adm_dma_desc(struct qcom_nand_controller *nandc, bool read,
int reg_off, const void *vaddr, int size,
bool flow_control)
@@ -790,16 +921,19 @@ static int read_reg_dma(struct qcom_nand_controller *nandc, int first,
{
bool flow_control = false;
void *vaddr;
- int size;
- if (first == NAND_READ_ID || first == NAND_FLASH_STATUS)
- flow_control = true;
-
- size = num_regs * sizeof(u32);
vaddr = nandc->reg_read_buf + nandc->reg_read_pos;
nandc->reg_read_pos += num_regs;
- return prep_adm_dma_desc(nandc, true, first, vaddr, size, flow_control);
+ if (nandc->props->is_bam)
+ return prep_bam_dma_desc_cmd(nandc, true, first, vaddr,
+ num_regs, flags);
+
+ if (first == NAND_READ_ID || first == NAND_FLASH_STATUS)
+ flow_control = true;
+
+ return prep_adm_dma_desc(nandc, true, first, vaddr,
+ num_regs * sizeof(u32), flow_control);
}
/*
@@ -815,13 +949,9 @@ static int write_reg_dma(struct qcom_nand_controller *nandc, int first,
bool flow_control = false;
struct nandc_regs *regs = nandc->regs;
void *vaddr;
- int size;
vaddr = offset_to_nandc_reg(regs, first);
- if (first == NAND_FLASH_CMD)
- flow_control = true;
-
if (first == NAND_ERASED_CW_DETECT_CFG) {
if (flags & NAND_ERASED_CW_SET)
vaddr = ®s->erased_cw_detect_cfg_set;
@@ -838,10 +968,15 @@ static int write_reg_dma(struct qcom_nand_controller *nandc, int first,
if (first == NAND_DEV_CMD_VLD_RESTORE)
first = NAND_DEV_CMD_VLD;
- size = num_regs * sizeof(u32);
+ if (nandc->props->is_bam)
+ return prep_bam_dma_desc_cmd(nandc, false, first, vaddr,
+ num_regs, flags);
- return prep_adm_dma_desc(nandc, false, first, vaddr, size,
- flow_control);
+ if (first == NAND_FLASH_CMD)
+ flow_control = true;
+
+ return prep_adm_dma_desc(nandc, false, first, vaddr,
+ num_regs * sizeof(u32), flow_control);
}
/*
@@ -855,6 +990,9 @@ static int write_reg_dma(struct qcom_nand_controller *nandc, int first,
static int read_data_dma(struct qcom_nand_controller *nandc, int reg_off,
const u8 *vaddr, int size, unsigned int flags)
{
+ if (nandc->props->is_bam)
+ return prep_bam_dma_desc_data(nandc, true, vaddr, size, flags);
+
return prep_adm_dma_desc(nandc, true, reg_off, vaddr, size, false);
}
@@ -869,6 +1007,9 @@ static int read_data_dma(struct qcom_nand_controller *nandc, int reg_off,
static int write_data_dma(struct qcom_nand_controller *nandc, int reg_off,
const u8 *vaddr, int size, unsigned int flags)
{
+ if (nandc->props->is_bam)
+ return prep_bam_dma_desc_data(nandc, false, vaddr, size, flags);
+
return prep_adm_dma_desc(nandc, false, reg_off, vaddr, size, false);
}
@@ -1046,7 +1187,8 @@ static int read_id(struct qcom_nand_host *host, int column)
nandc_set_reg(nandc, NAND_FLASH_CMD, FETCH_ID);
nandc_set_reg(nandc, NAND_ADDR0, column);
nandc_set_reg(nandc, NAND_ADDR1, 0);
- nandc_set_reg(nandc, NAND_FLASH_CHIP_SELECT, DM_EN);
+ nandc_set_reg(nandc, NAND_FLASH_CHIP_SELECT,
+ nandc->props->is_bam ? 0 : DM_EN);
nandc_set_reg(nandc, NAND_EXEC_CMD, 1);
write_reg_dma(nandc, NAND_FLASH_CMD, 4, NAND_BAM_NEXT_SGL);
@@ -1157,6 +1299,9 @@ static void pre_command(struct qcom_nand_host *host, int command)
host->last_command = command;
clear_read_regs(nandc);
+ if (command == NAND_CMD_RESET || command == NAND_CMD_READID ||
+ command == NAND_CMD_PARAM || command == NAND_CMD_ERASE1)
+ clear_bam_transaction(nandc);
}
/*
@@ -1561,6 +1706,7 @@ static int qcom_nandc_read_page(struct mtd_info *mtd, struct nand_chip *chip,
data_buf = buf;
oob_buf = oob_required ? chip->oob_poi : NULL;
+ clear_bam_transaction(nandc);
ret = read_page_ecc(host, data_buf, oob_buf);
if (ret) {
dev_err(nandc->dev, "failure to read page\n");
@@ -1586,6 +1732,8 @@ static int qcom_nandc_read_page_raw(struct mtd_info *mtd,
oob_buf = chip->oob_poi;
host->use_ecc = false;
+
+ clear_bam_transaction(nandc);
update_rw_regs(host, ecc->steps, true);
config_nand_page_read(nandc);
@@ -1657,6 +1805,7 @@ static int qcom_nandc_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
int ret;
clear_read_regs(nandc);
+ clear_bam_transaction(nandc);
host->use_ecc = true;
set_address(host, 0, page);
@@ -1680,6 +1829,7 @@ static int qcom_nandc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
int i, ret;
clear_read_regs(nandc);
+ clear_bam_transaction(nandc);
data_buf = (u8 *)buf;
oob_buf = chip->oob_poi;
@@ -1745,6 +1895,7 @@ static int qcom_nandc_write_page_raw(struct mtd_info *mtd,
int i, ret;
clear_read_regs(nandc);
+ clear_bam_transaction(nandc);
data_buf = (u8 *)buf;
oob_buf = chip->oob_poi;
@@ -1819,11 +1970,13 @@ static int qcom_nandc_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
host->use_ecc = true;
+ clear_bam_transaction(nandc);
ret = copy_last_cw(host, page);
if (ret)
return ret;
clear_read_regs(nandc);
+ clear_bam_transaction(nandc);
/* calculate the data and oob size for the last codeword/step */
data_size = ecc->size - ((ecc->steps - 1) << 2);
@@ -1876,6 +2029,7 @@ static int qcom_nandc_block_bad(struct mtd_info *mtd, loff_t ofs)
*/
host->use_ecc = false;
+ clear_bam_transaction(nandc);
ret = copy_last_cw(host, page);
if (ret)
goto err;
@@ -1906,6 +2060,7 @@ static int qcom_nandc_block_markbad(struct mtd_info *mtd, loff_t ofs)
int page, ret, status = 0;
clear_read_regs(nandc);
+ clear_bam_transaction(nandc);
/*
* to mark the BBM as bad, we flash the entire last codeword with 0s.
@@ -2418,12 +2573,19 @@ static void qcom_nandc_unalloc(struct qcom_nand_controller *nandc)
/* one time setup of a few nand controller registers */
static int qcom_nandc_setup(struct qcom_nand_controller *nandc)
{
+ u32 nand_ctrl;
+
/* kill onenand */
nandc_write(nandc, SFLASHC_BURST_CFG, 0);
nandc_write(nandc, NAND_DEV_CMD_VLD, NAND_DEV_CMD_VLD_VAL);
- /* enable ADM DMA */
- nandc_write(nandc, NAND_FLASH_CHIP_SELECT, DM_EN);
+ /* enable ADM or BAM DMA */
+ if (nandc->props->is_bam) {
+ nand_ctrl = nandc_read(nandc, NAND_CTRL);
+ nandc_write(nandc, NAND_CTRL, nand_ctrl | BAM_MODE_EN);
+ } else {
+ nandc_write(nandc, NAND_FLASH_CHIP_SELECT, DM_EN);
+ }
/* save the original values of these registers */
nandc->cmd1 = nandc_read(nandc, NAND_DEV_CMD1);
@@ -2608,6 +2770,7 @@ static int qcom_nandc_probe(struct platform_device *pdev)
if (IS_ERR(nandc->base))
return PTR_ERR(nandc->base);
+ nandc->base_phys = res->start;
nandc->base_dma = phys_to_dma(dev, (phys_addr_t)res->start);
nandc->core_clk = devm_clk_get(dev, "core");
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
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| From | Abhishek Sahu <absahu@codeaurora.org> |
|---|---|
| Date | 2017-07-19 14:00 +0200 |
| Subject | [PATCH v2 15/25] mtd: nand: qcom: DMA mapping support for register read buffer |
| Message-ID | <u4VO3-85k-39@gated-at.bofh.it> |
| In reply to | #1691591 |
The EBI2 NAND directly remaps register read buffer with
dma_map_sg. The QPIC NAND will give register read buffer in its
command descriptor and the command descriptor will be mapped with
dma_map_sg instead of register read buffer. This command
descriptor will contain the dma address of the register read
buffer.
This patch adds the DMA mapping support for register read buffer.
This buffer will be DMA mapped during allocation time. Before
starting of any operation, this buffer will be synced for device
operation and after operation completion, it will be synced for
CPU.
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
---
drivers/mtd/nand/qcom_nandc.c | 40 ++++++++++++++++++++++++++++++++++++++++
1 file changed, 40 insertions(+)
diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
index cb2b245..f49c3da 100644
--- a/drivers/mtd/nand/qcom_nandc.c
+++ b/drivers/mtd/nand/qcom_nandc.c
@@ -229,6 +229,7 @@ struct nandc_regs {
* by upper layers directly
* @buf_size/count/start: markers for chip->read_buf/write_buf functions
* @reg_read_buf: local buffer for reading back registers via DMA
+ * @reg_read_buf_phys: contains dma address for register read buffer
* @reg_read_pos: marker for data read in reg_read_buf
*
* @regs: a contiguous chunk of memory for DMA register
@@ -271,6 +272,7 @@ struct qcom_nand_controller {
int buf_start;
__le32 *reg_read_buf;
+ dma_addr_t reg_read_buf_phys;
int reg_read_pos;
struct nandc_regs *regs;
@@ -363,6 +365,24 @@ static inline void nandc_write(struct qcom_nand_controller *nandc, int offset,
iowrite32(val, nandc->base + offset);
}
+static inline void nandc_read_buffer_sync(struct qcom_nand_controller *nandc,
+ bool is_cpu)
+{
+ if (!nandc->props->is_bam)
+ return;
+
+ if (is_cpu)
+ dma_sync_single_for_cpu(nandc->dev, nandc->reg_read_buf_phys,
+ MAX_REG_RD *
+ sizeof(*nandc->reg_read_buf),
+ DMA_FROM_DEVICE);
+ else
+ dma_sync_single_for_device(nandc->dev, nandc->reg_read_buf_phys,
+ MAX_REG_RD *
+ sizeof(*nandc->reg_read_buf),
+ DMA_FROM_DEVICE);
+}
+
static __le32 *offset_to_nandc_reg(struct nandc_regs *regs, int offset)
{
switch (offset) {
@@ -847,6 +867,7 @@ static void free_descs(struct qcom_nand_controller *nandc)
static void clear_read_regs(struct qcom_nand_controller *nandc)
{
nandc->reg_read_pos = 0;
+ nandc_read_buffer_sync(nandc, false);
}
static void pre_command(struct qcom_nand_host *host, int command)
@@ -876,6 +897,7 @@ static void parse_erase_write_errors(struct qcom_nand_host *host, int command)
int i;
num_cw = command == NAND_CMD_PAGEPROG ? ecc->steps : 1;
+ nandc_read_buffer_sync(nandc, true);
for (i = 0; i < num_cw; i++) {
u32 flash_status = le32_to_cpu(nandc->reg_read_buf[i]);
@@ -897,6 +919,7 @@ static void post_command(struct qcom_nand_host *host, int command)
switch (command) {
case NAND_CMD_READID:
+ nandc_read_buffer_sync(nandc, true);
memcpy(nandc->data_buffer, nandc->reg_read_buf,
nandc->buf_count);
break;
@@ -1060,6 +1083,7 @@ static int parse_read_errors(struct qcom_nand_host *host, u8 *data_buf,
int i;
buf = (struct read_stats *)nandc->reg_read_buf;
+ nandc_read_buffer_sync(nandc, true);
for (i = 0; i < ecc->steps; i++, buf++) {
u32 flash, buffer, erased_cw;
@@ -1996,6 +2020,16 @@ static int qcom_nandc_alloc(struct qcom_nand_controller *nandc)
return -ENOMEM;
if (nandc->props->is_bam) {
+ nandc->reg_read_buf_phys =
+ dma_map_single(nandc->dev, nandc->reg_read_buf,
+ MAX_REG_RD *
+ sizeof(*nandc->reg_read_buf),
+ DMA_FROM_DEVICE);
+ if (dma_mapping_error(nandc->dev, nandc->reg_read_buf_phys)) {
+ dev_err(nandc->dev, "failed to DMA MAP reg buffer\n");
+ return -EIO;
+ }
+
nandc->tx_chan = dma_request_slave_channel(nandc->dev, "tx");
if (!nandc->tx_chan) {
dev_err(nandc->dev, "failed to request tx channel\n");
@@ -2033,6 +2067,12 @@ static int qcom_nandc_alloc(struct qcom_nand_controller *nandc)
static void qcom_nandc_unalloc(struct qcom_nand_controller *nandc)
{
if (nandc->props->is_bam) {
+ if (!dma_mapping_error(nandc->dev, nandc->reg_read_buf_phys))
+ dma_unmap_single(nandc->dev, nandc->reg_read_buf_phys,
+ MAX_REG_RD *
+ sizeof(*nandc->reg_read_buf),
+ DMA_FROM_DEVICE);
+
if (nandc->tx_chan)
dma_release_channel(nandc->tx_chan);
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
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| From | Abhishek Sahu <absahu@codeaurora.org> |
|---|---|
| Date | 2017-07-19 14:00 +0200 |
| Subject | [PATCH v2 19/25] mtd: nand: qcom: support for read location registers |
| Message-ID | <u4VO3-85k-41@gated-at.bofh.it> |
| In reply to | #1691591 |
In EBI2, all codeword data will be read in FLASH_BUF_ACC buffer
and ADM will copy the data from source (FLASH_BUF_ACC) to
destination (memory for data read).
In QPIC, there is no FLASH_BUF_ACC and all the codeword data will
held in QPIC BAM FIFO buffers. It provides multiple READ_LOCATION
registers which will be used for copying the data from FIFO to
memory. The READ_LOCATION register will be used to read a
specific amount of data from a specific offset within the flash
buffer. It supports sequential offset requests. Each request is
composed of the following fields:
a. Offset within the flash buffer from which data should be
read
b. Amount of data to be read
c. Flag bit specifying the last read request from the flash
buffer. Following the last read request the NANDc refers to the
buffer as empty.
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
---
drivers/mtd/nand/qcom_nandc.c | 72 ++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 71 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
index 8a6034f..b9e0eec 100644
--- a/drivers/mtd/nand/qcom_nandc.c
+++ b/drivers/mtd/nand/qcom_nandc.c
@@ -54,6 +54,8 @@
#define NAND_VERSION 0xf08
#define NAND_READ_LOCATION_0 0xf20
#define NAND_READ_LOCATION_1 0xf24
+#define NAND_READ_LOCATION_2 0xf28
+#define NAND_READ_LOCATION_3 0xf2c
/* dummy register offsets, used by write_reg_dma */
#define NAND_DEV_CMD1_RESTORE 0xdead
@@ -132,6 +134,11 @@
#define ERASED_PAGE (PAGE_ALL_ERASED | PAGE_ERASED)
#define ERASED_CW (CODEWORD_ALL_ERASED | CODEWORD_ERASED)
+/* NAND_READ_LOCATION_n bits */
+#define READ_LOCATION_OFFSET 0
+#define READ_LOCATION_SIZE 16
+#define READ_LOCATION_LAST 31
+
/* Version Mask */
#define NAND_VERSION_MAJOR_MASK 0xf0000000
#define NAND_VERSION_MAJOR_SHIFT 28
@@ -173,6 +180,11 @@
#define ECC_BCH_4BIT BIT(2)
#define ECC_BCH_8BIT BIT(3)
+#define NANDC_SET_READL(nandc, reg, offset, size, is_last) \
+nandc_set_reg(nandc, NAND_READ_LOCATION_##reg, \
+ (offset << READ_LOCATION_OFFSET) | (size << READ_LOCATION_SIZE) |\
+ (is_last << READ_LOCATION_LAST))
+
#define QPIC_PER_CW_CMD_ELEMENTS 32
#define QPIC_PER_CW_CMD_SGL 32
#define QPIC_PER_CW_DATA_SGL 8
@@ -262,6 +274,11 @@ struct nandc_regs {
__le32 orig_vld;
__le32 ecc_buf_cfg;
+ __le32 read_location0;
+ __le32 read_location1;
+ __le32 read_location2;
+ __le32 read_location3;
+
};
/*
@@ -521,6 +538,14 @@ static __le32 *offset_to_nandc_reg(struct nandc_regs *regs, int offset)
return ®s->orig_vld;
case NAND_EBI2_ECC_BUF_CFG:
return ®s->ecc_buf_cfg;
+ case NAND_READ_LOCATION_0:
+ return ®s->read_location0;
+ case NAND_READ_LOCATION_1:
+ return ®s->read_location1;
+ case NAND_READ_LOCATION_2:
+ return ®s->read_location2;
+ case NAND_READ_LOCATION_3:
+ return ®s->read_location3;
default:
return NULL;
}
@@ -562,7 +587,7 @@ static void update_rw_regs(struct qcom_nand_host *host, int num_cw, bool read)
{
struct nand_chip *chip = &host->chip;
struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
- u32 cmd, cfg0, cfg1, ecc_bch_cfg;
+ u32 cmd, cfg0, cfg1, ecc_bch_cfg, read_location0;
if (read) {
if (host->use_ecc)
@@ -579,12 +604,20 @@ static void update_rw_regs(struct qcom_nand_host *host, int num_cw, bool read)
cfg1 = host->cfg1;
ecc_bch_cfg = host->ecc_bch_cfg;
+ if (read)
+ read_location0 = (0 << READ_LOCATION_OFFSET) |
+ (host->cw_data << READ_LOCATION_SIZE) |
+ (1 << READ_LOCATION_LAST);
} else {
cfg0 = (host->cfg0_raw & ~(7U << CW_PER_PAGE)) |
(num_cw - 1) << CW_PER_PAGE;
cfg1 = host->cfg1_raw;
ecc_bch_cfg = 1 << ECC_CFG_ECC_DISABLE;
+ if (read)
+ read_location0 = (0 << READ_LOCATION_OFFSET) |
+ (host->cw_size << READ_LOCATION_SIZE) |
+ (1 << READ_LOCATION_LAST);
}
nandc_set_reg(nandc, NAND_FLASH_CMD, cmd);
@@ -595,6 +628,9 @@ static void update_rw_regs(struct qcom_nand_host *host, int num_cw, bool read)
nandc_set_reg(nandc, NAND_FLASH_STATUS, host->clrflashstatus);
nandc_set_reg(nandc, NAND_READ_STATUS, host->clrreadstatus);
nandc_set_reg(nandc, NAND_EXEC_CMD, 1);
+
+ if (read)
+ nandc_set_reg(nandc, NAND_READ_LOCATION_0, read_location0);
}
/*
@@ -839,6 +875,10 @@ static void config_nand_page_read(struct qcom_nand_controller *nandc)
*/
static void config_nand_cw_read(struct qcom_nand_controller *nandc)
{
+ if (nandc->props->is_bam)
+ write_reg_dma(nandc, NAND_READ_LOCATION_0, 4,
+ NAND_BAM_NEXT_SGL);
+
write_reg_dma(nandc, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL);
write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
@@ -928,6 +968,7 @@ static int nandc_param(struct qcom_nand_host *host)
nandc_set_reg(nandc, NAND_DEV_CMD1_RESTORE, nandc->cmd1);
nandc_set_reg(nandc, NAND_DEV_CMD_VLD_RESTORE, nandc->vld);
+ NANDC_SET_READL(nandc, 0, 0, 512, 1);
write_reg_dma(nandc, NAND_DEV_CMD_VLD, 1, 0);
write_reg_dma(nandc, NAND_DEV_CMD1, 1, NAND_BAM_NEXT_SGL);
@@ -1404,6 +1445,19 @@ static int read_page_ecc(struct qcom_nand_host *host, u8 *data_buf,
oob_size = host->ecc_bytes_hw + host->spare_bytes;
}
+ if (nandc->props->is_bam) {
+ if (data_buf && oob_buf) {
+ NANDC_SET_READL(nandc, 0, 0, data_size, 0);
+ NANDC_SET_READL(nandc, 1, data_size,
+ oob_size, 1);
+ } else if (data_buf) {
+ NANDC_SET_READL(nandc, 0, 0, data_size, 1);
+ } else {
+ NANDC_SET_READL(nandc, 0, data_size,
+ oob_size, 1);
+ }
+ }
+
config_nand_cw_read(nandc);
if (data_buf)
@@ -1463,6 +1517,7 @@ static int copy_last_cw(struct qcom_nand_host *host, int page)
set_address(host, host->cw_size * (ecc->steps - 1), page);
update_rw_regs(host, 1, true);
+ NANDC_SET_READL(nandc, 0, 0, size, 1);
config_nand_single_cw_page_read(nandc);
@@ -1508,6 +1563,7 @@ static int qcom_nandc_read_page_raw(struct mtd_info *mtd,
u8 *data_buf, *oob_buf;
struct nand_ecc_ctrl *ecc = &chip->ecc;
int i, ret;
+ int read_loc;
data_buf = buf;
oob_buf = chip->oob_poi;
@@ -1533,6 +1589,20 @@ static int qcom_nandc_read_page_raw(struct mtd_info *mtd,
oob_size2 = host->ecc_bytes_hw + host->spare_bytes;
}
+ if (nandc->props->is_bam) {
+ read_loc = 0;
+ NANDC_SET_READL(nandc, 0, read_loc, data_size1, 0);
+ read_loc += data_size1;
+
+ NANDC_SET_READL(nandc, 1, read_loc, oob_size1, 0);
+ read_loc += oob_size1;
+
+ NANDC_SET_READL(nandc, 2, read_loc, data_size2, 0);
+ read_loc += data_size2;
+
+ NANDC_SET_READL(nandc, 3, read_loc, oob_size2, 1);
+ }
+
config_nand_cw_read(nandc);
read_data_dma(nandc, reg_off, data_buf, data_size1, 0);
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
[toc] | [prev] | [next] | [standalone]
| From | Abhishek Sahu <absahu@codeaurora.org> |
|---|---|
| Date | 2017-07-19 14:00 +0200 |
| Subject | [PATCH v2 24/25] dt-bindings: qcom_nandc: compatible string for version 1.5.0 |
| Message-ID | <u4VO3-85k-45@gated-at.bofh.it> |
| In reply to | #1691591 |
A new compatible string has been added for QPIC NAND version 1.5.0.
Since only register offsets are diffferent in version 1.5.0 so no
new dts property is required for QPIC NAND version 1.5.0.
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
---
Documentation/devicetree/bindings/mtd/qcom_nandc.txt | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
index 8efaeb0..23bbb79 100644
--- a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
+++ b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
@@ -4,6 +4,8 @@ Required properties:
- compatible: must be one of the following:
* "qcom,ebi2-nandc" - EBI2 NAND which uses ADM DMA like IPQ8064.
* "qcom,qpic-nandc-v1.4.0" - QPIC NAND v1.4.0 which uses BAM DMA like IPQ4019.
+ * "qcom,qpic-nandc-v1.5.0" - QPIC NAND v1.5.0 which uses BAM DMA like IPQ8074.
+
- reg: MMIO address range
- clocks: must contain core clock and always on clock
- clock-names: must contain "core" for the core clock and "aon" for the
@@ -94,7 +96,7 @@ nand@1ac00000 {
};
nand@79b0000 {
- compatible = "qcom,qpic-nandc-v1.4.0";
+ compatible = "qcom,qpic-nandc-v1.4.0", "qcom,qpic-nandc-v1.5.0";
reg = <0x79b0000 0x1000>;
clocks = <&gcc GCC_QPIC_CLK>,
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
[toc] | [prev] | [next] | [standalone]
| From | Abhishek Sahu <absahu@codeaurora.org> |
|---|---|
| Date | 2017-07-19 14:00 +0200 |
| Subject | [PATCH v2 11/25] mtd: nand: qcom: support for NAND controller properties |
| Message-ID | <u4VO3-85k-51@gated-at.bofh.it> |
| In reply to | #1691591 |
Currently driver data is being assigned directly with ECC modes.
Now, the plan is to add more NAND controller versions, so
reorganized the current driver data assignment by creating NAND
controller properties structure. This will contain all
properties specific to NAND controller.
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
---
drivers/mtd/nand/qcom_nandc.c | 23 +++++++++++++++++------
1 file changed, 17 insertions(+), 6 deletions(-)
diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
index 8f9e86c..3b0ae91 100644
--- a/drivers/mtd/nand/qcom_nandc.c
+++ b/drivers/mtd/nand/qcom_nandc.c
@@ -235,7 +235,7 @@ struct nandc_regs {
* writes. contains the register values to be
* written to controller
* @cmd1/vld: some fixed controller register values
- * @ecc_modes: supported ECC modes by the current controller,
+ * @props: properties of current NAND controller IP,
* initialized via DT match data
*/
struct qcom_nand_controller {
@@ -266,7 +266,7 @@ struct qcom_nand_controller {
struct nandc_regs *regs;
u32 cmd1, vld;
- u32 ecc_modes;
+ const struct qcom_props *props;
};
/*
@@ -319,6 +319,15 @@ struct qcom_nand_host {
u32 clrreadstatus;
};
+/*
+ * This data type corresponds to the nand controller properties which varies
+ * among different NAND controller IP's.
+ * @ecc_modes - ecc mode for NAND
+ */
+struct qcom_props {
+ u32 ecc_modes;
+};
+
static inline struct qcom_nand_host *to_qcom_nand_host(struct nand_chip *chip)
{
return container_of(chip, struct qcom_nand_host, chip);
@@ -1820,7 +1829,7 @@ static int qcom_nand_host_setup(struct qcom_nand_host *host)
* uses lesser bytes for ECC. If RS is used, the ECC bytes is
* always 10 bytes
*/
- if (nandc->ecc_modes & ECC_BCH_4BIT) {
+ if (nandc->props->ecc_modes & ECC_BCH_4BIT) {
/* BCH */
host->bch_enabled = true;
ecc_mode = 0;
@@ -2165,7 +2174,7 @@ static int qcom_nandc_probe(struct platform_device *pdev)
return -ENODEV;
}
- nandc->ecc_modes = (unsigned long)dev_data;
+ nandc->props = dev_data;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
nandc->base = devm_ioremap_resource(dev, res);
@@ -2234,7 +2243,9 @@ static int qcom_nandc_remove(struct platform_device *pdev)
return 0;
}
-#define EBI2_NANDC_ECC_MODES (ECC_RS_4BIT | ECC_BCH_8BIT)
+static const struct qcom_props ebi2_nandc_data = {
+ .ecc_modes = (ECC_RS_4BIT | ECC_BCH_8BIT),
+};
/*
* data will hold a struct pointer containing more differences once we support
@@ -2242,7 +2253,7 @@ static int qcom_nandc_remove(struct platform_device *pdev)
*/
static const struct of_device_id qcom_nandc_of_match[] = {
{ .compatible = "qcom,ebi2-nandc",
- .data = (void *)EBI2_NANDC_ECC_MODES,
+ .data = &ebi2_nandc_data,
},
{}
};
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
[toc] | [prev] | [next] | [standalone]
| From | Abhishek Sahu <absahu@codeaurora.org> |
|---|---|
| Date | 2017-07-19 14:00 +0200 |
| Subject | [PATCH v2 13/25] mtd: nand: qcom: add QPIC NAND compatible string |
| Message-ID | <u4VO3-85k-47@gated-at.bofh.it> |
| In reply to | #1691591 |
The current driver only support EBI2 NAND which uses ADM DMA. The
latest QCOM controller supports QPIC NAND which uses BAM DMA. NAND
registers and programming sequence are same for EBI2 and QPIC
NAND so the same driver can support QPIC NAND also by adding the
BAM DMA support. This patch adds the QPIC NAND support in current
NAND driver with compatible string "qcom,qpic-nandc-v1.4.0" and
maps it with different configuration parameter in driver data.
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
---
drivers/mtd/nand/qcom_nandc.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
index 3b0ae91..6d24630 100644
--- a/drivers/mtd/nand/qcom_nandc.c
+++ b/drivers/mtd/nand/qcom_nandc.c
@@ -323,9 +323,11 @@ struct qcom_nand_host {
* This data type corresponds to the nand controller properties which varies
* among different NAND controller IP's.
* @ecc_modes - ecc mode for NAND
+ * @is_bam - whether NAND controller is using bam
*/
struct qcom_props {
u32 ecc_modes;
+ bool is_bam;
};
static inline struct qcom_nand_host *to_qcom_nand_host(struct nand_chip *chip)
@@ -2245,6 +2247,12 @@ static int qcom_nandc_remove(struct platform_device *pdev)
static const struct qcom_props ebi2_nandc_data = {
.ecc_modes = (ECC_RS_4BIT | ECC_BCH_8BIT),
+ .is_bam = false,
+};
+
+static const struct qcom_props qpic_nandc_v1_4_0_data = {
+ .ecc_modes = (ECC_BCH_4BIT | ECC_BCH_8BIT),
+ .is_bam = true,
};
/*
@@ -2255,6 +2263,9 @@ static int qcom_nandc_remove(struct platform_device *pdev)
{ .compatible = "qcom,ebi2-nandc",
.data = &ebi2_nandc_data,
},
+ { .compatible = "qcom,qpic-nandc-v1.4.0",
+ .data = &qpic_nandc_v1_4_0_data,
+ },
{}
};
MODULE_DEVICE_TABLE(of, qcom_nandc_of_match);
--
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