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Groups > linux.kernel > #1691598
| From | Abhishek Sahu <absahu@codeaurora.org> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | [PATCH v2 08/25] mtd: nand: qcom: reorganize nand page write |
| Date | 2017-07-19 14:00 +0200 |
| Message-ID | <u4VO2-85k-13@gated-at.bofh.it> (permalink) |
| References | <u4VEl-7Z9-9@gated-at.bofh.it> |
| Organization | linux.* mail to news gateway |
Each NAND page consist of multiple codewords. Following is
sequence for NAND page write according to hardware guide.
1. Program Power-up configuration, page row, page column
address and flash configuration registers.
2. Write NAND_FLASH_CMD followed by NANC_EXEC_CMD for each
codeword.
3. Read NAND_FLASH_STATUS for each codeword.
The step 1 should be done once for each page and step 2,3 should
be done for each codeword.
Currently, all the 3 steps are being done for each codeword which
is wrong. Now this patch reorganizes page write functions to
configure page specific register once and per codeword specific
registers for each NAND ECC step.
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
---
drivers/mtd/nand/qcom_nandc.c | 32 ++++++++++++++++++++------------
1 file changed, 20 insertions(+), 12 deletions(-)
diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
index 27ea594..5b71478 100644
--- a/drivers/mtd/nand/qcom_nandc.c
+++ b/drivers/mtd/nand/qcom_nandc.c
@@ -638,15 +638,24 @@ static void config_nand_single_cw_page_read(struct qcom_nand_controller *nandc)
config_nand_cw_read(nandc);
}
-static void config_cw_write_pre(struct qcom_nand_controller *nandc)
+/*
+ * Helper to prepare DMA descriptors used to configure registers needed for
+ * before writing a NAND page.
+ */
+static void config_nand_page_write(struct qcom_nand_controller *nandc)
{
- write_reg_dma(nandc, NAND_FLASH_CMD, 3);
+ write_reg_dma(nandc, NAND_ADDR0, 2);
write_reg_dma(nandc, NAND_DEV0_CFG0, 3);
write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1);
}
-static void config_cw_write_post(struct qcom_nand_controller *nandc)
+/*
+ * Helper to prepare DMA descriptors for configuring registers
+ * before writing each codeword in NAND page.
+ */
+static void config_nand_cw_write(struct qcom_nand_controller *nandc)
{
+ write_reg_dma(nandc, NAND_FLASH_CMD, 1);
write_reg_dma(nandc, NAND_EXEC_CMD, 1);
read_reg_dma(nandc, NAND_FLASH_STATUS, 1);
@@ -1329,6 +1338,7 @@ static int qcom_nandc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
host->use_ecc = true;
update_rw_regs(host, ecc->steps, false);
+ config_nand_page_write(nandc);
for (i = 0; i < ecc->steps; i++) {
int data_size, oob_size;
@@ -1342,7 +1352,6 @@ static int qcom_nandc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
oob_size = ecc->bytes;
}
- config_cw_write_pre(nandc);
write_data_dma(nandc, FLASH_BUF_ACC, data_buf, data_size);
@@ -1360,7 +1369,7 @@ static int qcom_nandc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
oob_buf, oob_size);
}
- config_cw_write_post(nandc);
+ config_nand_cw_write(nandc);
data_buf += data_size;
oob_buf += oob_size;
@@ -1393,6 +1402,7 @@ static int qcom_nandc_write_page_raw(struct mtd_info *mtd,
host->use_ecc = false;
update_rw_regs(host, ecc->steps, false);
+ config_nand_page_write(nandc);
for (i = 0; i < ecc->steps; i++) {
int data_size1, data_size2, oob_size1, oob_size2;
@@ -1411,8 +1421,6 @@ static int qcom_nandc_write_page_raw(struct mtd_info *mtd,
oob_size2 = host->ecc_bytes_hw + host->spare_bytes;
}
- config_cw_write_pre(nandc);
-
write_data_dma(nandc, reg_off, data_buf, data_size1);
reg_off += data_size1;
data_buf += data_size1;
@@ -1428,7 +1436,7 @@ static int qcom_nandc_write_page_raw(struct mtd_info *mtd,
write_data_dma(nandc, reg_off, oob_buf, oob_size2);
oob_buf += oob_size2;
- config_cw_write_post(nandc);
+ config_nand_cw_write(nandc);
}
ret = submit_descs(nandc);
@@ -1478,10 +1486,10 @@ static int qcom_nandc_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
set_address(host, host->cw_size * (ecc->steps - 1), page);
update_rw_regs(host, 1, false);
- config_cw_write_pre(nandc);
+ config_nand_page_write(nandc);
write_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer,
data_size + oob_size);
- config_cw_write_post(nandc);
+ config_nand_cw_write(nandc);
ret = submit_descs(nandc);
@@ -1563,9 +1571,9 @@ static int qcom_nandc_block_markbad(struct mtd_info *mtd, loff_t ofs)
set_address(host, host->cw_size * (ecc->steps - 1), page);
update_rw_regs(host, 1, false);
- config_cw_write_pre(nandc);
+ config_nand_page_write(nandc);
write_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer, host->cw_size);
- config_cw_write_post(nandc);
+ config_nand_cw_write(nandc);
ret = submit_descs(nandc);
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
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[PATCH v2 00/25] Add QCOM QPIC NAND support Abhishek Sahu <absahu@codeaurora.org> - 2017-07-19 13:50 +0200
[PATCH v2 09/25] mtd: nand: qcom: remove memset for clearing read register buffer Abhishek Sahu <absahu@codeaurora.org> - 2017-07-19 14:00 +0200
[PATCH v2 10/25] mtd: nand: qcom: reorganize nand devices probing Abhishek Sahu <absahu@codeaurora.org> - 2017-07-19 14:00 +0200
[PATCH v2 23/25] mtd: nand: qcom: change register offset defines with enums Abhishek Sahu <absahu@codeaurora.org> - 2017-07-19 14:00 +0200
[PATCH v2 20/25] mtd: nand: qcom: erased codeword detection configuration Abhishek Sahu <absahu@codeaurora.org> - 2017-07-19 14:00 +0200
[PATCH v2 08/25] mtd: nand: qcom: reorganize nand page write Abhishek Sahu <absahu@codeaurora.org> - 2017-07-19 14:00 +0200
[PATCH v2 18/25] mtd: nand: qcom: support for passing flags in transfer functions Abhishek Sahu <absahu@codeaurora.org> - 2017-07-19 14:00 +0200
[PATCH v2 25/25] mtd: nand: qcom: support for QPIC version 1.5.0 Abhishek Sahu <absahu@codeaurora.org> - 2017-07-19 14:00 +0200
[PATCH v2 22/25] mtd: nand: qcom: QPIC raw write support Abhishek Sahu <absahu@codeaurora.org> - 2017-07-19 14:00 +0200
[PATCH v2 12/25] dt-bindings: qcom_nandc: QPIC NAND documentation Abhishek Sahu <absahu@codeaurora.org> - 2017-07-19 14:00 +0200
Re: [PATCH v2 12/25] dt-bindings: qcom_nandc: QPIC NAND documentation Boris Brezillon <boris.brezillon@free-electrons.com> - 2017-07-19 21:40 +0200
Re: [PATCH v2 12/25] dt-bindings: qcom_nandc: QPIC NAND documentation Abhishek Sahu <absahu@codeaurora.org> - 2017-07-20 07:40 +0200
Re: [PATCH v2 12/25] dt-bindings: qcom_nandc: QPIC NAND documentation Rob Herring <robh@kernel.org> - 2017-07-24 21:20 +0200
Re: [PATCH v2 12/25] dt-bindings: qcom_nandc: QPIC NAND documentation Abhishek Sahu <absahu@codeaurora.org> - 2017-07-25 20:50 +0200
[PATCH v2 21/25] mtd: nand: qcom: support for QPIC page read/write Abhishek Sahu <absahu@codeaurora.org> - 2017-07-19 14:00 +0200
[PATCH v2 15/25] mtd: nand: qcom: DMA mapping support for register read buffer Abhishek Sahu <absahu@codeaurora.org> - 2017-07-19 14:00 +0200
[PATCH v2 19/25] mtd: nand: qcom: support for read location registers Abhishek Sahu <absahu@codeaurora.org> - 2017-07-19 14:00 +0200
[PATCH v2 24/25] dt-bindings: qcom_nandc: compatible string for version 1.5.0 Abhishek Sahu <absahu@codeaurora.org> - 2017-07-19 14:00 +0200
[PATCH v2 11/25] mtd: nand: qcom: support for NAND controller properties Abhishek Sahu <absahu@codeaurora.org> - 2017-07-19 14:00 +0200
[PATCH v2 13/25] mtd: nand: qcom: add QPIC NAND compatible string Abhishek Sahu <absahu@codeaurora.org> - 2017-07-19 14:00 +0200
[PATCH v2 17/25] mtd: nand: qcom: add BAM DMA descriptor handling Abhishek Sahu <absahu@codeaurora.org> - 2017-07-19 14:00 +0200
[PATCH v2 16/25] mtd: nand: qcom: allocate BAM transaction Abhishek Sahu <absahu@codeaurora.org> - 2017-07-19 14:00 +0200
[PATCH v2 07/25] mtd: nand: qcom: reorganize nand page read Abhishek Sahu <absahu@codeaurora.org> - 2017-07-19 14:00 +0200
[PATCH v2 14/25] mtd: nand: qcom: add and initialize QPIC DMA resources Abhishek Sahu <absahu@codeaurora.org> - 2017-07-19 14:00 +0200
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