Groups | Search | Server Info | Keyboard shortcuts | Login | Register [http] [https] [nntp] [nntps]

Groups > linux.kernel > #1690295 > unrolled thread

[PATCHv2 08/10] x86/mm: Replace compile-time checks for 5-level with runtime-time

Started by"Kirill A. Shutemov" <kirill.shutemov@linux.intel.com>
First post2017-07-18 16:20 +0200
Last post2017-07-27 10:30 +0200
Articles 7 — 3 participants

Back to article view | Back to linux.kernel

This discussion starts older than the indexed window; earlier articles aren't shown. The article labeled Started by below is the oldest one visible, not the original post.

Contents

  [PATCHv2 08/10] x86/mm: Replace compile-time checks for 5-level with runtime-time "Kirill A. Shutemov" <kirill.shutemov@linux.intel.com> - 2017-07-18 16:20 +0200
    Re: [PATCHv2 08/10] x86/mm: Replace compile-time checks for 5-level  with runtime-time Juergen Gross <jgross@suse.com> - 2017-07-18 16:30 +0200
      Re: [PATCHv2 08/10] x86/mm: Replace compile-time checks for 5-level  with runtime-time "Kirill A. Shutemov" <kirill@shutemov.name> - 2017-07-18 17:20 +0200
      Re: [PATCHv2 08/10] x86/mm: Replace compile-time checks for 5-level  with runtime-time "Kirill A. Shutemov" <kirill.shutemov@linux.intel.com> - 2017-07-25 11:10 +0200
        Re: [PATCHv2 08/10] x86/mm: Replace compile-time checks for 5-level  with runtime-time Juergen Gross <jgross@suse.com> - 2017-07-26 09:30 +0200
          Re: [PATCHv2 08/10] x86/mm: Replace compile-time checks for 5-level  with runtime-time "Kirill A. Shutemov" <kirill@shutemov.name> - 2017-07-26 18:50 +0200
            Re: [PATCHv2 08/10] x86/mm: Replace compile-time checks for 5-level  with runtime-time Juergen Gross <jgross@suse.com> - 2017-07-27 10:30 +0200

#1690295 — [PATCHv2 08/10] x86/mm: Replace compile-time checks for 5-level with runtime-time

From"Kirill A. Shutemov" <kirill.shutemov@linux.intel.com>
Date2017-07-18 16:20 +0200
Subject[PATCHv2 08/10] x86/mm: Replace compile-time checks for 5-level with runtime-time
Message-ID<u4BvY-3ta-19@gated-at.bofh.it>
This patch converts the of CONFIG_X86_5LEVEL check to runtime checks for
p4d folding.

Signed-off-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com>
---
 arch/x86/mm/fault.c            |  2 +-
 arch/x86/mm/ident_map.c        |  2 +-
 arch/x86/mm/init_64.c          | 30 ++++++++++++++++++------------
 arch/x86/mm/kasan_init_64.c    |  8 ++++----
 arch/x86/mm/kaslr.c            |  6 +++---
 arch/x86/platform/efi/efi_64.c |  2 +-
 arch/x86/power/hibernate_64.c  |  6 +++---
 arch/x86/xen/mmu_pv.c          |  2 +-
 8 files changed, 32 insertions(+), 26 deletions(-)

diff --git a/arch/x86/mm/fault.c b/arch/x86/mm/fault.c
index 2a1fa10c6a98..d3d8f10f0c10 100644
--- a/arch/x86/mm/fault.c
+++ b/arch/x86/mm/fault.c
@@ -459,7 +459,7 @@ static noinline int vmalloc_fault(unsigned long address)
 	if (pgd_none(*pgd)) {
 		set_pgd(pgd, *pgd_ref);
 		arch_flush_lazy_mmu_mode();
-	} else if (CONFIG_PGTABLE_LEVELS > 4) {
+	} else if (!p4d_folded) {
 		/*
 		 * With folded p4d, pgd_none() is always false, so the pgd may
 		 * point to an empty page table entry and pgd_page_vaddr()
diff --git a/arch/x86/mm/ident_map.c b/arch/x86/mm/ident_map.c
index adab1595f4bd..d2df33a2cbfb 100644
--- a/arch/x86/mm/ident_map.c
+++ b/arch/x86/mm/ident_map.c
@@ -115,7 +115,7 @@ int kernel_ident_mapping_init(struct x86_mapping_info *info, pgd_t *pgd_page,
 		result = ident_p4d_init(info, p4d, addr, next);
 		if (result)
 			return result;
-		if (IS_ENABLED(CONFIG_X86_5LEVEL)) {
+		if (!p4d_folded) {
 			set_pgd(pgd, __pgd(__pa(p4d) | _KERNPG_TABLE));
 		} else {
 			/*
diff --git a/arch/x86/mm/init_64.c b/arch/x86/mm/init_64.c
index 649b8df485ad..6b97f6c1bf77 100644
--- a/arch/x86/mm/init_64.c
+++ b/arch/x86/mm/init_64.c
@@ -88,12 +88,7 @@ static int __init nonx32_setup(char *str)
 }
 __setup("noexec32=", nonx32_setup);
 
-/*
- * When memory was added make sure all the processes MM have
- * suitable PGD entries in the local PGD level page.
- */
-#ifdef CONFIG_X86_5LEVEL
-void sync_global_pgds(unsigned long start, unsigned long end)
+static void sync_global_pgds_57(unsigned long start, unsigned long end)
 {
 	unsigned long addr;
 
@@ -129,8 +124,8 @@ void sync_global_pgds(unsigned long start, unsigned long end)
 		spin_unlock(&pgd_lock);
 	}
 }
-#else
-void sync_global_pgds(unsigned long start, unsigned long end)
+
+static void sync_global_pgds_48(unsigned long start, unsigned long end)
 {
 	unsigned long addr;
 
@@ -173,7 +168,18 @@ void sync_global_pgds(unsigned long start, unsigned long end)
 		spin_unlock(&pgd_lock);
 	}
 }
-#endif
+
+/*
+ * When memory was added make sure all the processes MM have
+ * suitable PGD entries in the local PGD level page.
+ */
+void sync_global_pgds(unsigned long start, unsigned long end)
+{
+	if (!p4d_folded)
+		sync_global_pgds_57(start, end);
+	else
+		sync_global_pgds_48(start, end);
+}
 
 /*
  * NOTE: This function is marked __ref because it calls __init function
@@ -632,7 +638,7 @@ phys_p4d_init(p4d_t *p4d_page, unsigned long paddr, unsigned long paddr_end,
 	unsigned long vaddr = (unsigned long)__va(paddr);
 	int i = p4d_index(vaddr);
 
-	if (!IS_ENABLED(CONFIG_X86_5LEVEL))
+	if (p4d_folded)
 		return phys_pud_init((pud_t *) p4d_page, paddr, paddr_end, page_size_mask);
 
 	for (; i < PTRS_PER_P4D; i++, paddr = paddr_next) {
@@ -712,7 +718,7 @@ kernel_physical_mapping_init(unsigned long paddr_start,
 					   page_size_mask);
 
 		spin_lock(&init_mm.page_table_lock);
-		if (IS_ENABLED(CONFIG_X86_5LEVEL))
+		if (!p4d_folded)
 			pgd_populate(&init_mm, pgd, p4d);
 		else
 			p4d_populate(&init_mm, p4d_offset(pgd, vaddr), (pud_t *) p4d);
@@ -1078,7 +1084,7 @@ remove_p4d_table(p4d_t *p4d_start, unsigned long addr, unsigned long end,
 		 * 5-level case we should free them. This code will have to change
 		 * to adapt for boot-time switching between 4 and 5 level page tables.
 		 */
-		if (CONFIG_PGTABLE_LEVELS == 5)
+		if (!p4d_folded)
 			free_pud_table(pud_base, p4d);
 	}
 
diff --git a/arch/x86/mm/kasan_init_64.c b/arch/x86/mm/kasan_init_64.c
index cff8d85fef7b..ee12861e0609 100644
--- a/arch/x86/mm/kasan_init_64.c
+++ b/arch/x86/mm/kasan_init_64.c
@@ -40,7 +40,7 @@ static void __init clear_pgds(unsigned long start,
 		 * With folded p4d, pgd_clear() is nop, use p4d_clear()
 		 * instead.
 		 */
-		if (CONFIG_PGTABLE_LEVELS < 5)
+		if (p4d_folded)
 			p4d_clear(p4d_offset(pgd, start));
 		else
 			pgd_clear(pgd);
@@ -55,7 +55,7 @@ static inline p4d_t *early_p4d_offset(pgd_t *pgd, unsigned long addr)
 {
 	unsigned long p4d;
 
-	if (!IS_ENABLED(CONFIG_X86_5LEVEL))
+	if (p4d_folded)
 		return (p4d_t *)pgd;
 
 	p4d = __pa_nodebug(pgd_val(*pgd)) & PTE_PFN_MASK;
@@ -135,7 +135,7 @@ void __init kasan_early_init(void)
 	for (i = 0; i < PTRS_PER_PUD; i++)
 		kasan_zero_pud[i] = __pud(pud_val);
 
-	for (i = 0; IS_ENABLED(CONFIG_X86_5LEVEL) && i < PTRS_PER_P4D; i++)
+	for (i = 0; !p4d_folded && i < PTRS_PER_P4D; i++)
 		kasan_zero_p4d[i] = __p4d(p4d_val);
 
 	kasan_map_early_shadow(early_top_pgt);
@@ -152,7 +152,7 @@ void __init kasan_init(void)
 
 	memcpy(early_top_pgt, init_top_pgt, sizeof(early_top_pgt));
 
-	if (IS_ENABLED(CONFIG_X86_5LEVEL)) {
+	if (!p4d_folded) {
 		void *ptr;
 
 		ptr = (void *)pgd_page_vaddr(*pgd_offset_k(KASAN_SHADOW_END));
diff --git a/arch/x86/mm/kaslr.c b/arch/x86/mm/kaslr.c
index 2f6ba5c72905..b70f86a2ce6a 100644
--- a/arch/x86/mm/kaslr.c
+++ b/arch/x86/mm/kaslr.c
@@ -139,7 +139,7 @@ void __init kernel_randomize_memory(void)
 		 */
 		entropy = remain_entropy / (ARRAY_SIZE(kaslr_regions) - i);
 		prandom_bytes_state(&rand_state, &rand, sizeof(rand));
-		if (IS_ENABLED(CONFIG_X86_5LEVEL))
+		if (!p4d_folded)
 			entropy = (rand % (entropy + 1)) & P4D_MASK;
 		else
 			entropy = (rand % (entropy + 1)) & PUD_MASK;
@@ -151,7 +151,7 @@ void __init kernel_randomize_memory(void)
 		 * randomization alignment.
 		 */
 		vaddr += get_padding(&kaslr_regions[i]);
-		if (IS_ENABLED(CONFIG_X86_5LEVEL))
+		if (!p4d_folded)
 			vaddr = round_up(vaddr + 1, P4D_SIZE);
 		else
 			vaddr = round_up(vaddr + 1, PUD_SIZE);
@@ -227,7 +227,7 @@ void __meminit init_trampoline(void)
 		return;
 	}
 
-	if (IS_ENABLED(CONFIG_X86_5LEVEL))
+	if (!p4d_folded)
 		init_trampoline_p4d();
 	else
 		init_trampoline_pud();
diff --git a/arch/x86/platform/efi/efi_64.c b/arch/x86/platform/efi/efi_64.c
index 3cda4fd8ed2b..91d9076ee216 100644
--- a/arch/x86/platform/efi/efi_64.c
+++ b/arch/x86/platform/efi/efi_64.c
@@ -219,7 +219,7 @@ int __init efi_alloc_page_tables(void)
 
 	pud = pud_alloc(&init_mm, p4d, EFI_VA_END);
 	if (!pud) {
-		if (CONFIG_PGTABLE_LEVELS > 4)
+		if (!p4d_folded)
 			free_page((unsigned long) pgd_page_vaddr(*pgd));
 		free_page((unsigned long)efi_pgd);
 		return -ENOMEM;
diff --git a/arch/x86/power/hibernate_64.c b/arch/x86/power/hibernate_64.c
index f2598d81cd55..9b9bc2ef4321 100644
--- a/arch/x86/power/hibernate_64.c
+++ b/arch/x86/power/hibernate_64.c
@@ -50,7 +50,7 @@ static int set_up_temporary_text_mapping(pgd_t *pgd)
 {
 	pmd_t *pmd;
 	pud_t *pud;
-	p4d_t *p4d;
+	p4d_t *p4d = NULL;
 
 	/*
 	 * The new mapping only has to cover the page containing the image
@@ -66,7 +66,7 @@ static int set_up_temporary_text_mapping(pgd_t *pgd)
 	 * tables used by the image kernel.
 	 */
 
-	if (IS_ENABLED(CONFIG_X86_5LEVEL)) {
+	if (!p4d_folded) {
 		p4d = (p4d_t *)get_safe_page(GFP_ATOMIC);
 		if (!p4d)
 			return -ENOMEM;
@@ -84,7 +84,7 @@ static int set_up_temporary_text_mapping(pgd_t *pgd)
 		__pmd((jump_address_phys & PMD_MASK) | __PAGE_KERNEL_LARGE_EXEC));
 	set_pud(pud + pud_index(restore_jump_address),
 		__pud(__pa(pmd) | _KERNPG_TABLE));
-	if (IS_ENABLED(CONFIG_X86_5LEVEL)) {
+	if (p4d) {
 		set_p4d(p4d + p4d_index(restore_jump_address), __p4d(__pa(pud) | _KERNPG_TABLE));
 		set_pgd(pgd + pgd_index(restore_jump_address), __pgd(__pa(p4d) | _KERNPG_TABLE));
 	} else {
diff --git a/arch/x86/xen/mmu_pv.c b/arch/x86/xen/mmu_pv.c
index cab28cf2cffb..b0530184c637 100644
--- a/arch/x86/xen/mmu_pv.c
+++ b/arch/x86/xen/mmu_pv.c
@@ -1209,7 +1209,7 @@ static void __init xen_cleanmfnmap(unsigned long vaddr)
 			continue;
 		xen_cleanmfnmap_p4d(p4d + i, unpin);
 	}
-	if (IS_ENABLED(CONFIG_X86_5LEVEL)) {
+	if (!p4d_folded) {
 		set_pgd(pgd, __pgd(0));
 		xen_cleanmfnmap_free_pgtbl(p4d, unpin);
 	}
-- 
2.11.0

[toc] | [next] | [standalone]

#1690306 — Re: [PATCHv2 08/10] x86/mm: Replace compile-time checks for 5-level with runtime-time

FromJuergen Gross <jgross@suse.com>
Date2017-07-18 16:30 +0200
SubjectRe: [PATCHv2 08/10] x86/mm: Replace compile-time checks for 5-level with runtime-time
Message-ID<u4BFD-3wF-1@gated-at.bofh.it>
In reply to#1690295
On 18/07/17 16:15, Kirill A. Shutemov wrote:
> This patch converts the of CONFIG_X86_5LEVEL check to runtime checks for
> p4d folding.
> 
> Signed-off-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com>
> ---
>  arch/x86/mm/fault.c            |  2 +-
>  arch/x86/mm/ident_map.c        |  2 +-
>  arch/x86/mm/init_64.c          | 30 ++++++++++++++++++------------
>  arch/x86/mm/kasan_init_64.c    |  8 ++++----
>  arch/x86/mm/kaslr.c            |  6 +++---
>  arch/x86/platform/efi/efi_64.c |  2 +-
>  arch/x86/power/hibernate_64.c  |  6 +++---
>  arch/x86/xen/mmu_pv.c          |  2 +-
>  8 files changed, 32 insertions(+), 26 deletions(-)
> 
> diff --git a/arch/x86/mm/fault.c b/arch/x86/mm/fault.c
> index 2a1fa10c6a98..d3d8f10f0c10 100644
> --- a/arch/x86/mm/fault.c
> +++ b/arch/x86/mm/fault.c
> @@ -459,7 +459,7 @@ static noinline int vmalloc_fault(unsigned long address)
>  	if (pgd_none(*pgd)) {
>  		set_pgd(pgd, *pgd_ref);
>  		arch_flush_lazy_mmu_mode();
> -	} else if (CONFIG_PGTABLE_LEVELS > 4) {
> +	} else if (!p4d_folded) {
>  		/*
>  		 * With folded p4d, pgd_none() is always false, so the pgd may
>  		 * point to an empty page table entry and pgd_page_vaddr()
> diff --git a/arch/x86/mm/ident_map.c b/arch/x86/mm/ident_map.c
> index adab1595f4bd..d2df33a2cbfb 100644
> --- a/arch/x86/mm/ident_map.c
> +++ b/arch/x86/mm/ident_map.c
> @@ -115,7 +115,7 @@ int kernel_ident_mapping_init(struct x86_mapping_info *info, pgd_t *pgd_page,
>  		result = ident_p4d_init(info, p4d, addr, next);
>  		if (result)
>  			return result;
> -		if (IS_ENABLED(CONFIG_X86_5LEVEL)) {
> +		if (!p4d_folded) {
>  			set_pgd(pgd, __pgd(__pa(p4d) | _KERNPG_TABLE));
>  		} else {
>  			/*
> diff --git a/arch/x86/mm/init_64.c b/arch/x86/mm/init_64.c
> index 649b8df485ad..6b97f6c1bf77 100644
> --- a/arch/x86/mm/init_64.c
> +++ b/arch/x86/mm/init_64.c
> @@ -88,12 +88,7 @@ static int __init nonx32_setup(char *str)
>  }
>  __setup("noexec32=", nonx32_setup);
>  
> -/*
> - * When memory was added make sure all the processes MM have
> - * suitable PGD entries in the local PGD level page.
> - */
> -#ifdef CONFIG_X86_5LEVEL
> -void sync_global_pgds(unsigned long start, unsigned long end)
> +static void sync_global_pgds_57(unsigned long start, unsigned long end)
>  {
>  	unsigned long addr;
>  
> @@ -129,8 +124,8 @@ void sync_global_pgds(unsigned long start, unsigned long end)
>  		spin_unlock(&pgd_lock);
>  	}
>  }
> -#else
> -void sync_global_pgds(unsigned long start, unsigned long end)
> +
> +static void sync_global_pgds_48(unsigned long start, unsigned long end)
>  {
>  	unsigned long addr;
>  
> @@ -173,7 +168,18 @@ void sync_global_pgds(unsigned long start, unsigned long end)
>  		spin_unlock(&pgd_lock);
>  	}
>  }
> -#endif
> +
> +/*
> + * When memory was added make sure all the processes MM have
> + * suitable PGD entries in the local PGD level page.
> + */
> +void sync_global_pgds(unsigned long start, unsigned long end)
> +{
> +	if (!p4d_folded)
> +		sync_global_pgds_57(start, end);
> +	else
> +		sync_global_pgds_48(start, end);
> +}
>  
>  /*
>   * NOTE: This function is marked __ref because it calls __init function
> @@ -632,7 +638,7 @@ phys_p4d_init(p4d_t *p4d_page, unsigned long paddr, unsigned long paddr_end,
>  	unsigned long vaddr = (unsigned long)__va(paddr);
>  	int i = p4d_index(vaddr);
>  
> -	if (!IS_ENABLED(CONFIG_X86_5LEVEL))
> +	if (p4d_folded)
>  		return phys_pud_init((pud_t *) p4d_page, paddr, paddr_end, page_size_mask);
>  
>  	for (; i < PTRS_PER_P4D; i++, paddr = paddr_next) {
> @@ -712,7 +718,7 @@ kernel_physical_mapping_init(unsigned long paddr_start,
>  					   page_size_mask);
>  
>  		spin_lock(&init_mm.page_table_lock);
> -		if (IS_ENABLED(CONFIG_X86_5LEVEL))
> +		if (!p4d_folded)
>  			pgd_populate(&init_mm, pgd, p4d);
>  		else
>  			p4d_populate(&init_mm, p4d_offset(pgd, vaddr), (pud_t *) p4d);
> @@ -1078,7 +1084,7 @@ remove_p4d_table(p4d_t *p4d_start, unsigned long addr, unsigned long end,
>  		 * 5-level case we should free them. This code will have to change
>  		 * to adapt for boot-time switching between 4 and 5 level page tables.
>  		 */
> -		if (CONFIG_PGTABLE_LEVELS == 5)
> +		if (!p4d_folded)
>  			free_pud_table(pud_base, p4d);
>  	}
>  
> diff --git a/arch/x86/mm/kasan_init_64.c b/arch/x86/mm/kasan_init_64.c
> index cff8d85fef7b..ee12861e0609 100644
> --- a/arch/x86/mm/kasan_init_64.c
> +++ b/arch/x86/mm/kasan_init_64.c
> @@ -40,7 +40,7 @@ static void __init clear_pgds(unsigned long start,
>  		 * With folded p4d, pgd_clear() is nop, use p4d_clear()
>  		 * instead.
>  		 */
> -		if (CONFIG_PGTABLE_LEVELS < 5)
> +		if (p4d_folded)
>  			p4d_clear(p4d_offset(pgd, start));
>  		else
>  			pgd_clear(pgd);
> @@ -55,7 +55,7 @@ static inline p4d_t *early_p4d_offset(pgd_t *pgd, unsigned long addr)
>  {
>  	unsigned long p4d;
>  
> -	if (!IS_ENABLED(CONFIG_X86_5LEVEL))
> +	if (p4d_folded)
>  		return (p4d_t *)pgd;
>  
>  	p4d = __pa_nodebug(pgd_val(*pgd)) & PTE_PFN_MASK;
> @@ -135,7 +135,7 @@ void __init kasan_early_init(void)
>  	for (i = 0; i < PTRS_PER_PUD; i++)
>  		kasan_zero_pud[i] = __pud(pud_val);
>  
> -	for (i = 0; IS_ENABLED(CONFIG_X86_5LEVEL) && i < PTRS_PER_P4D; i++)
> +	for (i = 0; !p4d_folded && i < PTRS_PER_P4D; i++)
>  		kasan_zero_p4d[i] = __p4d(p4d_val);
>  
>  	kasan_map_early_shadow(early_top_pgt);
> @@ -152,7 +152,7 @@ void __init kasan_init(void)
>  
>  	memcpy(early_top_pgt, init_top_pgt, sizeof(early_top_pgt));
>  
> -	if (IS_ENABLED(CONFIG_X86_5LEVEL)) {
> +	if (!p4d_folded) {
>  		void *ptr;
>  
>  		ptr = (void *)pgd_page_vaddr(*pgd_offset_k(KASAN_SHADOW_END));
> diff --git a/arch/x86/mm/kaslr.c b/arch/x86/mm/kaslr.c
> index 2f6ba5c72905..b70f86a2ce6a 100644
> --- a/arch/x86/mm/kaslr.c
> +++ b/arch/x86/mm/kaslr.c
> @@ -139,7 +139,7 @@ void __init kernel_randomize_memory(void)
>  		 */
>  		entropy = remain_entropy / (ARRAY_SIZE(kaslr_regions) - i);
>  		prandom_bytes_state(&rand_state, &rand, sizeof(rand));
> -		if (IS_ENABLED(CONFIG_X86_5LEVEL))
> +		if (!p4d_folded)
>  			entropy = (rand % (entropy + 1)) & P4D_MASK;
>  		else
>  			entropy = (rand % (entropy + 1)) & PUD_MASK;
> @@ -151,7 +151,7 @@ void __init kernel_randomize_memory(void)
>  		 * randomization alignment.
>  		 */
>  		vaddr += get_padding(&kaslr_regions[i]);
> -		if (IS_ENABLED(CONFIG_X86_5LEVEL))
> +		if (!p4d_folded)
>  			vaddr = round_up(vaddr + 1, P4D_SIZE);
>  		else
>  			vaddr = round_up(vaddr + 1, PUD_SIZE);
> @@ -227,7 +227,7 @@ void __meminit init_trampoline(void)
>  		return;
>  	}
>  
> -	if (IS_ENABLED(CONFIG_X86_5LEVEL))
> +	if (!p4d_folded)
>  		init_trampoline_p4d();
>  	else
>  		init_trampoline_pud();
> diff --git a/arch/x86/platform/efi/efi_64.c b/arch/x86/platform/efi/efi_64.c
> index 3cda4fd8ed2b..91d9076ee216 100644
> --- a/arch/x86/platform/efi/efi_64.c
> +++ b/arch/x86/platform/efi/efi_64.c
> @@ -219,7 +219,7 @@ int __init efi_alloc_page_tables(void)
>  
>  	pud = pud_alloc(&init_mm, p4d, EFI_VA_END);
>  	if (!pud) {
> -		if (CONFIG_PGTABLE_LEVELS > 4)
> +		if (!p4d_folded)
>  			free_page((unsigned long) pgd_page_vaddr(*pgd));
>  		free_page((unsigned long)efi_pgd);
>  		return -ENOMEM;
> diff --git a/arch/x86/power/hibernate_64.c b/arch/x86/power/hibernate_64.c
> index f2598d81cd55..9b9bc2ef4321 100644
> --- a/arch/x86/power/hibernate_64.c
> +++ b/arch/x86/power/hibernate_64.c
> @@ -50,7 +50,7 @@ static int set_up_temporary_text_mapping(pgd_t *pgd)
>  {
>  	pmd_t *pmd;
>  	pud_t *pud;
> -	p4d_t *p4d;
> +	p4d_t *p4d = NULL;
>  
>  	/*
>  	 * The new mapping only has to cover the page containing the image
> @@ -66,7 +66,7 @@ static int set_up_temporary_text_mapping(pgd_t *pgd)
>  	 * tables used by the image kernel.
>  	 */
>  
> -	if (IS_ENABLED(CONFIG_X86_5LEVEL)) {
> +	if (!p4d_folded) {
>  		p4d = (p4d_t *)get_safe_page(GFP_ATOMIC);
>  		if (!p4d)
>  			return -ENOMEM;
> @@ -84,7 +84,7 @@ static int set_up_temporary_text_mapping(pgd_t *pgd)
>  		__pmd((jump_address_phys & PMD_MASK) | __PAGE_KERNEL_LARGE_EXEC));
>  	set_pud(pud + pud_index(restore_jump_address),
>  		__pud(__pa(pmd) | _KERNPG_TABLE));
> -	if (IS_ENABLED(CONFIG_X86_5LEVEL)) {
> +	if (p4d) {
>  		set_p4d(p4d + p4d_index(restore_jump_address), __p4d(__pa(pud) | _KERNPG_TABLE));
>  		set_pgd(pgd + pgd_index(restore_jump_address), __pgd(__pa(p4d) | _KERNPG_TABLE));
>  	} else {
> diff --git a/arch/x86/xen/mmu_pv.c b/arch/x86/xen/mmu_pv.c
> index cab28cf2cffb..b0530184c637 100644
> --- a/arch/x86/xen/mmu_pv.c
> +++ b/arch/x86/xen/mmu_pv.c
> @@ -1209,7 +1209,7 @@ static void __init xen_cleanmfnmap(unsigned long vaddr)
>  			continue;
>  		xen_cleanmfnmap_p4d(p4d + i, unpin);
>  	}
> -	if (IS_ENABLED(CONFIG_X86_5LEVEL)) {
> +	if (!p4d_folded) {
>  		set_pgd(pgd, __pgd(0));
>  		xen_cleanmfnmap_free_pgtbl(p4d, unpin);
>  	}

Xen PV guests will never run with 5-level-paging enabled. So I guess you
can drop the complete if (IS_ENABLED(CONFIG_X86_5LEVEL)) {} block.


Juergen

[toc] | [prev] | [next] | [standalone]

#1690365 — Re: [PATCHv2 08/10] x86/mm: Replace compile-time checks for 5-level with runtime-time

From"Kirill A. Shutemov" <kirill@shutemov.name>
Date2017-07-18 17:20 +0200
SubjectRe: [PATCHv2 08/10] x86/mm: Replace compile-time checks for 5-level with runtime-time
Message-ID<u4Cs1-41M-11@gated-at.bofh.it>
In reply to#1690306
On Tue, Jul 18, 2017 at 04:24:06PM +0200, Juergen Gross wrote:
> On 18/07/17 16:15, Kirill A. Shutemov wrote:
> > diff --git a/arch/x86/xen/mmu_pv.c b/arch/x86/xen/mmu_pv.c
> > index cab28cf2cffb..b0530184c637 100644
> > --- a/arch/x86/xen/mmu_pv.c
> > +++ b/arch/x86/xen/mmu_pv.c
> > @@ -1209,7 +1209,7 @@ static void __init xen_cleanmfnmap(unsigned long vaddr)
> >  			continue;
> >  		xen_cleanmfnmap_p4d(p4d + i, unpin);
> >  	}
> > -	if (IS_ENABLED(CONFIG_X86_5LEVEL)) {
> > +	if (!p4d_folded) {
> >  		set_pgd(pgd, __pgd(0));
> >  		xen_cleanmfnmap_free_pgtbl(p4d, unpin);
> >  	}
> 
> Xen PV guests will never run with 5-level-paging enabled. So I guess you
> can drop the complete if (IS_ENABLED(CONFIG_X86_5LEVEL)) {} block.

Thanks.

I'll do a sparate cleanup patch for this.

-- 
 Kirill A. Shutemov

[toc] | [prev] | [next] | [standalone]

#1695517 — Re: [PATCHv2 08/10] x86/mm: Replace compile-time checks for 5-level with runtime-time

From"Kirill A. Shutemov" <kirill.shutemov@linux.intel.com>
Date2017-07-25 11:10 +0200
SubjectRe: [PATCHv2 08/10] x86/mm: Replace compile-time checks for 5-level with runtime-time
Message-ID<u740O-So-27@gated-at.bofh.it>
In reply to#1690306
On Tue, Jul 18, 2017 at 04:24:06PM +0200, Juergen Gross wrote:
> Xen PV guests will never run with 5-level-paging enabled. So I guess you
> can drop the complete if (IS_ENABLED(CONFIG_X86_5LEVEL)) {} block.

There is more code to drop from mmu_pv.c.

But while there, I thought if with boot-time 5-level paging switching we
can allow kernel to compile with XEN_PV and XEN_PVH, so the kernel image
can be used in these XEN modes with 4-level paging.

Could you check if with the patch below we can boot in XEN_PV and XEN_PVH
modes?

diff --git a/arch/x86/kernel/head_64.S b/arch/x86/kernel/head_64.S
index 7ebb56e99389..6d67d3530698 100644
--- a/arch/x86/kernel/head_64.S
+++ b/arch/x86/kernel/head_64.S
@@ -37,12 +37,12 @@
  *
  */
 
+#define l4_index(x)	(((x) >> P4D_SHIFT) & 511)
 #define pud_index(x)	(((x) >> PUD_SHIFT) & (PTRS_PER_PUD-1))
 
-#if defined(CONFIG_XEN_PV) || defined(CONFIG_XEN_PVH)
-PGD_PAGE_OFFSET = pgd_index(__PAGE_OFFSET_BASE48)
-PGD_START_KERNEL = pgd_index(__START_KERNEL_map)
-#endif
+L4_PAGE_OFFSET = l4_index(__PAGE_OFFSET_BASE48)
+L4_START_KERNEL = l4_index(__START_KERNEL_map)
+
 L3_START_KERNEL = pud_index(__START_KERNEL_map)
 
 	.text
@@ -347,9 +347,9 @@ NEXT_PAGE(early_dynamic_pgts)
 #if defined(CONFIG_XEN_PV) || defined(CONFIG_XEN_PVH)
 NEXT_PAGE(init_top_pgt)
 	.quad   level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE
-	.org    init_top_pgt + PGD_PAGE_OFFSET*8, 0
+	.org    init_top_pgt + L4_PAGE_OFFSET*8, 0
 	.quad   level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE
-	.org    init_top_pgt + PGD_START_KERNEL*8, 0
+	.org    init_top_pgt + L4_START_KERNEL*8, 0
 	/* (2^48-(2*1024*1024*1024))/(2^39) = 511 */
 	.quad   level3_kernel_pgt - __START_KERNEL_map + _PAGE_TABLE
 
diff --git a/arch/x86/xen/Kconfig b/arch/x86/xen/Kconfig
index 1ecd419811a2..027987638e98 100644
--- a/arch/x86/xen/Kconfig
+++ b/arch/x86/xen/Kconfig
@@ -17,9 +17,6 @@ config XEN_PV
 	bool "Xen PV guest support"
 	default y
 	depends on XEN
-	# XEN_PV is not ready to work with 5-level paging.
-	# Changes to hypervisor are also required.
-	depends on !X86_5LEVEL
 	select XEN_HAVE_PVMMU
 	select XEN_HAVE_VPMU
 	help
@@ -78,6 +75,4 @@ config XEN_DEBUG_FS
 config XEN_PVH
 	bool "Support for running as a PVH guest"
 	depends on XEN && XEN_PVHVM && ACPI
-	# Pre-built page tables are not ready to handle 5-level paging.
-	depends on !X86_5LEVEL
 	def_bool n
diff --git a/arch/x86/xen/mmu_pv.c b/arch/x86/xen/mmu_pv.c
index b0530184c637..3116649302f2 100644
--- a/arch/x86/xen/mmu_pv.c
+++ b/arch/x86/xen/mmu_pv.c
@@ -469,7 +469,7 @@ __visible pmd_t xen_make_pmd(pmdval_t pmd)
 }
 PV_CALLEE_SAVE_REGS_THUNK(xen_make_pmd);
 
-#if CONFIG_PGTABLE_LEVELS == 4
+#ifdef CONFIG_X86_64
 __visible pudval_t xen_pud_val(pud_t pud)
 {
 	return pte_mfn_to_pfn(pud.pud);
@@ -558,7 +558,7 @@ static void xen_set_p4d(p4d_t *ptr, p4d_t val)
 
 	xen_mc_issue(PARAVIRT_LAZY_MMU);
 }
-#endif	/* CONFIG_PGTABLE_LEVELS == 4 */
+#endif	/* CONFIG_X86_64 */
 
 static int xen_pmd_walk(struct mm_struct *mm, pmd_t *pmd,
 		int (*func)(struct mm_struct *mm, struct page *, enum pt_level),
@@ -600,21 +600,17 @@ static int xen_p4d_walk(struct mm_struct *mm, p4d_t *p4d,
 		int (*func)(struct mm_struct *mm, struct page *, enum pt_level),
 		bool last, unsigned long limit)
 {
-	int i, nr, flush = 0;
+	int flush = 0;
+	pud_t *pud;
 
-	nr = last ? p4d_index(limit) + 1 : PTRS_PER_P4D;
-	for (i = 0; i < nr; i++) {
-		pud_t *pud;
 
-		if (p4d_none(p4d[i]))
-			continue;
+	if (p4d_none(*p4d))
+		return flush;
 
-		pud = pud_offset(&p4d[i], 0);
-		if (PTRS_PER_PUD > 1)
-			flush |= (*func)(mm, virt_to_page(pud), PT_PUD);
-		flush |= xen_pud_walk(mm, pud, func,
-				last && i == nr - 1, limit);
-	}
+	pud = pud_offset(p4d, 0);
+	if (PTRS_PER_PUD > 1)
+		flush |= (*func)(mm, virt_to_page(pud), PT_PUD);
+	flush |= xen_pud_walk(mm, pud, func, last, limit);
 	return flush;
 }
 
@@ -664,8 +660,6 @@ static int __xen_pgd_walk(struct mm_struct *mm, pgd_t *pgd,
 			continue;
 
 		p4d = p4d_offset(&pgd[i], 0);
-		if (PTRS_PER_P4D > 1)
-			flush |= (*func)(mm, virt_to_page(p4d), PT_P4D);
 		flush |= xen_p4d_walk(mm, p4d, func, i == nr - 1, limit);
 	}
 
@@ -1197,22 +1191,14 @@ static void __init xen_cleanmfnmap(unsigned long vaddr)
 {
 	pgd_t *pgd;
 	p4d_t *p4d;
-	unsigned int i;
 	bool unpin;
 
 	unpin = (vaddr == 2 * PGDIR_SIZE);
 	vaddr &= PMD_MASK;
 	pgd = pgd_offset_k(vaddr);
 	p4d = p4d_offset(pgd, 0);
-	for (i = 0; i < PTRS_PER_P4D; i++) {
-		if (p4d_none(p4d[i]))
-			continue;
-		xen_cleanmfnmap_p4d(p4d + i, unpin);
-	}
-	if (!p4d_folded) {
-		set_pgd(pgd, __pgd(0));
-		xen_cleanmfnmap_free_pgtbl(p4d, unpin);
-	}
+	if (!p4d_none(*p4d))
+		xen_cleanmfnmap_p4d(p4d, unpin);
 }
 
 static void __init xen_pagetable_p2m_free(void)
@@ -1718,7 +1704,7 @@ static void xen_release_pmd(unsigned long pfn)
 	xen_release_ptpage(pfn, PT_PMD);
 }
 
-#if CONFIG_PGTABLE_LEVELS >= 4
+#ifdef CONFIG_X86_64
 static void xen_alloc_pud(struct mm_struct *mm, unsigned long pfn)
 {
 	xen_alloc_ptpage(mm, pfn, PT_PUD);
@@ -2055,13 +2041,12 @@ static phys_addr_t __init xen_early_virt_to_phys(unsigned long vaddr)
  */
 void __init xen_relocate_p2m(void)
 {
-	phys_addr_t size, new_area, pt_phys, pmd_phys, pud_phys, p4d_phys;
+	phys_addr_t size, new_area, pt_phys, pmd_phys, pud_phys;
 	unsigned long p2m_pfn, p2m_pfn_end, n_frames, pfn, pfn_end;
-	int n_pte, n_pt, n_pmd, n_pud, n_p4d, idx_pte, idx_pt, idx_pmd, idx_pud, idx_p4d;
+	int n_pte, n_pt, n_pmd, n_pud, idx_pte, idx_pt, idx_pmd, idx_pud;
 	pte_t *pt;
 	pmd_t *pmd;
 	pud_t *pud;
-	p4d_t *p4d = NULL;
 	pgd_t *pgd;
 	unsigned long *new_p2m;
 	int save_pud;
@@ -2071,11 +2056,7 @@ void __init xen_relocate_p2m(void)
 	n_pt = roundup(size, PMD_SIZE) >> PMD_SHIFT;
 	n_pmd = roundup(size, PUD_SIZE) >> PUD_SHIFT;
 	n_pud = roundup(size, P4D_SIZE) >> P4D_SHIFT;
-	if (PTRS_PER_P4D > 1)
-		n_p4d = roundup(size, PGDIR_SIZE) >> PGDIR_SHIFT;
-	else
-		n_p4d = 0;
-	n_frames = n_pte + n_pt + n_pmd + n_pud + n_p4d;
+	n_frames = n_pte + n_pt + n_pmd + n_pud;
 
 	new_area = xen_find_free_area(PFN_PHYS(n_frames));
 	if (!new_area) {
@@ -2091,76 +2072,56 @@ void __init xen_relocate_p2m(void)
 	 * To avoid any possible virtual address collision, just use
 	 * 2 * PUD_SIZE for the new area.
 	 */
-	p4d_phys = new_area;
-	pud_phys = p4d_phys + PFN_PHYS(n_p4d);
+	pud_phys = new_area;
 	pmd_phys = pud_phys + PFN_PHYS(n_pud);
 	pt_phys = pmd_phys + PFN_PHYS(n_pmd);
 	p2m_pfn = PFN_DOWN(pt_phys) + n_pt;
 
 	pgd = __va(read_cr3_pa());
 	new_p2m = (unsigned long *)(2 * PGDIR_SIZE);
-	idx_p4d = 0;
 	save_pud = n_pud;
-	do {
-		if (n_p4d > 0) {
-			p4d = early_memremap(p4d_phys, PAGE_SIZE);
-			clear_page(p4d);
-			n_pud = min(save_pud, PTRS_PER_P4D);
-		}
-		for (idx_pud = 0; idx_pud < n_pud; idx_pud++) {
-			pud = early_memremap(pud_phys, PAGE_SIZE);
-			clear_page(pud);
-			for (idx_pmd = 0; idx_pmd < min(n_pmd, PTRS_PER_PUD);
-				 idx_pmd++) {
-				pmd = early_memremap(pmd_phys, PAGE_SIZE);
-				clear_page(pmd);
-				for (idx_pt = 0; idx_pt < min(n_pt, PTRS_PER_PMD);
-					 idx_pt++) {
-					pt = early_memremap(pt_phys, PAGE_SIZE);
-					clear_page(pt);
-					for (idx_pte = 0;
-						 idx_pte < min(n_pte, PTRS_PER_PTE);
-						 idx_pte++) {
-						set_pte(pt + idx_pte,
-								pfn_pte(p2m_pfn, PAGE_KERNEL));
-						p2m_pfn++;
-					}
-					n_pte -= PTRS_PER_PTE;
-					early_memunmap(pt, PAGE_SIZE);
-					make_lowmem_page_readonly(__va(pt_phys));
-					pin_pagetable_pfn(MMUEXT_PIN_L1_TABLE,
-							PFN_DOWN(pt_phys));
-					set_pmd(pmd + idx_pt,
-							__pmd(_PAGE_TABLE | pt_phys));
-					pt_phys += PAGE_SIZE;
+	for (idx_pud = 0; idx_pud < n_pud; idx_pud++) {
+		pud = early_memremap(pud_phys, PAGE_SIZE);
+		clear_page(pud);
+		for (idx_pmd = 0; idx_pmd < min(n_pmd, PTRS_PER_PUD);
+				idx_pmd++) {
+			pmd = early_memremap(pmd_phys, PAGE_SIZE);
+			clear_page(pmd);
+			for (idx_pt = 0; idx_pt < min(n_pt, PTRS_PER_PMD);
+					idx_pt++) {
+				pt = early_memremap(pt_phys, PAGE_SIZE);
+				clear_page(pt);
+				for (idx_pte = 0;
+						idx_pte < min(n_pte, PTRS_PER_PTE);
+						idx_pte++) {
+					set_pte(pt + idx_pte,
+							pfn_pte(p2m_pfn, PAGE_KERNEL));
+					p2m_pfn++;
 				}
-				n_pt -= PTRS_PER_PMD;
-				early_memunmap(pmd, PAGE_SIZE);
-				make_lowmem_page_readonly(__va(pmd_phys));
-				pin_pagetable_pfn(MMUEXT_PIN_L2_TABLE,
-						PFN_DOWN(pmd_phys));
-				set_pud(pud + idx_pmd, __pud(_PAGE_TABLE | pmd_phys));
-				pmd_phys += PAGE_SIZE;
+				n_pte -= PTRS_PER_PTE;
+				early_memunmap(pt, PAGE_SIZE);
+				make_lowmem_page_readonly(__va(pt_phys));
+				pin_pagetable_pfn(MMUEXT_PIN_L1_TABLE,
+						PFN_DOWN(pt_phys));
+				set_pmd(pmd + idx_pt,
+						__pmd(_PAGE_TABLE | pt_phys));
+				pt_phys += PAGE_SIZE;
 			}
-			n_pmd -= PTRS_PER_PUD;
-			early_memunmap(pud, PAGE_SIZE);
-			make_lowmem_page_readonly(__va(pud_phys));
-			pin_pagetable_pfn(MMUEXT_PIN_L3_TABLE, PFN_DOWN(pud_phys));
-			if (n_p4d > 0)
-				set_p4d(p4d + idx_pud, __p4d(_PAGE_TABLE | pud_phys));
-			else
-				set_pgd(pgd + 2 + idx_pud, __pgd(_PAGE_TABLE | pud_phys));
-			pud_phys += PAGE_SIZE;
-		}
-		if (n_p4d > 0) {
-			save_pud -= PTRS_PER_P4D;
-			early_memunmap(p4d, PAGE_SIZE);
-			make_lowmem_page_readonly(__va(p4d_phys));
-			pin_pagetable_pfn(MMUEXT_PIN_L4_TABLE, PFN_DOWN(p4d_phys));
-			set_pgd(pgd + 2 + idx_p4d, __pgd(_PAGE_TABLE | p4d_phys));
-			p4d_phys += PAGE_SIZE;
+			n_pt -= PTRS_PER_PMD;
+			early_memunmap(pmd, PAGE_SIZE);
+			make_lowmem_page_readonly(__va(pmd_phys));
+			pin_pagetable_pfn(MMUEXT_PIN_L2_TABLE,
+					PFN_DOWN(pmd_phys));
+			set_pud(pud + idx_pmd, __pud(_PAGE_TABLE | pmd_phys));
+			pmd_phys += PAGE_SIZE;
 		}
-	} while (++idx_p4d < n_p4d);
+		n_pmd -= PTRS_PER_PUD;
+		early_memunmap(pud, PAGE_SIZE);
+		make_lowmem_page_readonly(__va(pud_phys));
+		pin_pagetable_pfn(MMUEXT_PIN_L3_TABLE, PFN_DOWN(pud_phys));
+		set_pgd(pgd + 2 + idx_pud, __pgd(_PAGE_TABLE | pud_phys));
+		pud_phys += PAGE_SIZE;
+	}
 
 	/* Now copy the old p2m info to the new area. */
 	memcpy(new_p2m, xen_p2m_addr, size);
@@ -2387,7 +2348,7 @@ static void __init xen_post_allocator_init(void)
 	pv_mmu_ops.set_pte = xen_set_pte;
 	pv_mmu_ops.set_pmd = xen_set_pmd;
 	pv_mmu_ops.set_pud = xen_set_pud;
-#if CONFIG_PGTABLE_LEVELS >= 4
+#ifdef CONFIG_X86_64
 	pv_mmu_ops.set_p4d = xen_set_p4d;
 #endif
 
@@ -2397,7 +2358,7 @@ static void __init xen_post_allocator_init(void)
 	pv_mmu_ops.alloc_pmd = xen_alloc_pmd;
 	pv_mmu_ops.release_pte = xen_release_pte;
 	pv_mmu_ops.release_pmd = xen_release_pmd;
-#if CONFIG_PGTABLE_LEVELS >= 4
+#ifdef CONFIG_X86_64
 	pv_mmu_ops.alloc_pud = xen_alloc_pud;
 	pv_mmu_ops.release_pud = xen_release_pud;
 #endif
@@ -2463,14 +2424,14 @@ static const struct pv_mmu_ops xen_mmu_ops __initconst = {
 	.make_pmd = PV_CALLEE_SAVE(xen_make_pmd),
 	.pmd_val = PV_CALLEE_SAVE(xen_pmd_val),
 
-#if CONFIG_PGTABLE_LEVELS >= 4
+#ifdef CONFIG_X86_64
 	.pud_val = PV_CALLEE_SAVE(xen_pud_val),
 	.make_pud = PV_CALLEE_SAVE(xen_make_pud),
 	.set_p4d = xen_set_p4d_hyper,
 
 	.alloc_pud = xen_alloc_pmd_init,
 	.release_pud = xen_release_pmd_init,
-#endif	/* CONFIG_PGTABLE_LEVELS == 4 */
+#endif	/* CONFIG_X86_64 */
 
 	.activate_mm = xen_activate_mm,
 	.dup_mmap = xen_dup_mmap,
-- 
 Kirill A. Shutemov

[toc] | [prev] | [next] | [standalone]

#1696840 — Re: [PATCHv2 08/10] x86/mm: Replace compile-time checks for 5-level with runtime-time

FromJuergen Gross <jgross@suse.com>
Date2017-07-26 09:30 +0200
SubjectRe: [PATCHv2 08/10] x86/mm: Replace compile-time checks for 5-level with runtime-time
Message-ID<u7oVA-5L0-5@gated-at.bofh.it>
In reply to#1695517
On 25/07/17 11:05, Kirill A. Shutemov wrote:
> On Tue, Jul 18, 2017 at 04:24:06PM +0200, Juergen Gross wrote:
>> Xen PV guests will never run with 5-level-paging enabled. So I guess you
>> can drop the complete if (IS_ENABLED(CONFIG_X86_5LEVEL)) {} block.
> 
> There is more code to drop from mmu_pv.c.
> 
> But while there, I thought if with boot-time 5-level paging switching we
> can allow kernel to compile with XEN_PV and XEN_PVH, so the kernel image
> can be used in these XEN modes with 4-level paging.
> 
> Could you check if with the patch below we can boot in XEN_PV and XEN_PVH
> modes?

We can't. I have used your branch:

git://git.kernel.org/pub/scm/linux/kernel/git/kas/linux.git
la57/boot-switching/v2

with this patch applied on top.

Doesn't boot PV guest with X86_5LEVEL configured (very early crash).
Doesn't build with X86_5LEVEL not configured:

  AS      arch/x86/kernel/head_64.o
/home/gross/linux/arch/x86/kernel/head_64.S: Assembler messages:
/home/gross/linux/arch/x86/kernel/head_64.S:350: Error: attempt to move
.org backwards
/home/gross/linux/arch/x86/kernel/head_64.S:352: Error: attempt to move
.org backwards
/home/gross/linux/arch/x86/kernel/head_64.S:43: Error: invalid operands
(*ABS* and *UND* sections) for `>>'
/home/gross/linux/arch/x86/kernel/head_64.S:44: Error: invalid operands
(*ABS* and *UND* sections) for `>>'
/home/gross/linux/scripts/Makefile.build:403: recipe for target
'arch/x86/kernel/head_64.o' failed
make[7]: *** [arch/x86/kernel/head_64.o] Error 1


Juergen

[toc] | [prev] | [next] | [standalone]

#1697348 — Re: [PATCHv2 08/10] x86/mm: Replace compile-time checks for 5-level with runtime-time

From"Kirill A. Shutemov" <kirill@shutemov.name>
Date2017-07-26 18:50 +0200
SubjectRe: [PATCHv2 08/10] x86/mm: Replace compile-time checks for 5-level with runtime-time
Message-ID<u7xFv-2JL-5@gated-at.bofh.it>
In reply to#1696840
On Wed, Jul 26, 2017 at 09:28:16AM +0200, Juergen Gross wrote:
> On 25/07/17 11:05, Kirill A. Shutemov wrote:
> > On Tue, Jul 18, 2017 at 04:24:06PM +0200, Juergen Gross wrote:
> >> Xen PV guests will never run with 5-level-paging enabled. So I guess you
> >> can drop the complete if (IS_ENABLED(CONFIG_X86_5LEVEL)) {} block.
> > 
> > There is more code to drop from mmu_pv.c.
> > 
> > But while there, I thought if with boot-time 5-level paging switching we
> > can allow kernel to compile with XEN_PV and XEN_PVH, so the kernel image
> > can be used in these XEN modes with 4-level paging.
> > 
> > Could you check if with the patch below we can boot in XEN_PV and XEN_PVH
> > modes?
> 
> We can't. I have used your branch:
> 
> git://git.kernel.org/pub/scm/linux/kernel/git/kas/linux.git
> la57/boot-switching/v2
> 
> with this patch applied on top.
> 
> Doesn't boot PV guest with X86_5LEVEL configured (very early crash).

Hm. Okay.

Have you tried PVH?

> Doesn't build with X86_5LEVEL not configured:
> 
>   AS      arch/x86/kernel/head_64.o

I've fixed the patch and split the patch into two parts: cleanup and
re-enabling XEN_PV and XEN_PVH for X86_5LEVEL.

There's chance that I screw somthing up in clenaup part. Could you check
that?

-- 
 Kirill A. Shutemov

[toc] | [prev] | [next] | [standalone]

#1697798 — Re: [PATCHv2 08/10] x86/mm: Replace compile-time checks for 5-level with runtime-time

FromJuergen Gross <jgross@suse.com>
Date2017-07-27 10:30 +0200
SubjectRe: [PATCHv2 08/10] x86/mm: Replace compile-time checks for 5-level with runtime-time
Message-ID<u7Mlc-3KZ-9@gated-at.bofh.it>
In reply to#1697348
On 26/07/17 18:43, Kirill A. Shutemov wrote:
> On Wed, Jul 26, 2017 at 09:28:16AM +0200, Juergen Gross wrote:
>> On 25/07/17 11:05, Kirill A. Shutemov wrote:
>>> On Tue, Jul 18, 2017 at 04:24:06PM +0200, Juergen Gross wrote:
>>>> Xen PV guests will never run with 5-level-paging enabled. So I guess you
>>>> can drop the complete if (IS_ENABLED(CONFIG_X86_5LEVEL)) {} block.
>>>
>>> There is more code to drop from mmu_pv.c.
>>>
>>> But while there, I thought if with boot-time 5-level paging switching we
>>> can allow kernel to compile with XEN_PV and XEN_PVH, so the kernel image
>>> can be used in these XEN modes with 4-level paging.
>>>
>>> Could you check if with the patch below we can boot in XEN_PV and XEN_PVH
>>> modes?
>>
>> We can't. I have used your branch:
>>
>> git://git.kernel.org/pub/scm/linux/kernel/git/kas/linux.git
>> la57/boot-switching/v2
>>
>> with this patch applied on top.
>>
>> Doesn't boot PV guest with X86_5LEVEL configured (very early crash).
> 
> Hm. Okay.
> 
> Have you tried PVH?

Now I have. Its coming up.

> 
>> Doesn't build with X86_5LEVEL not configured:
>>
>>   AS      arch/x86/kernel/head_64.o
> 
> I've fixed the patch and split the patch into two parts: cleanup and
> re-enabling XEN_PV and XEN_PVH for X86_5LEVEL.
> 
> There's chance that I screw somthing up in clenaup part. Could you check
> that?

Not sure I'll manage to do this today. Stay tuned...


Juergen

[toc] | [prev] | [standalone]

Back to top | Article view | linux.kernel

csiph-web