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| Started by | Borislav Petkov <bp@suse.de> |
|---|---|
| First post | 2017-04-18 20:40 +0200 |
| Last post | 2017-04-19 12:20 +0200 |
| Articles | 4 — 4 participants |
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[RFC PATCH] x86/mce: Check MCi_STATUS[MISCV] for usable addr on Intel only Borislav Petkov <bp@suse.de> - 2017-04-18 20:40 +0200
RE: [RFC PATCH] x86/mce: Check MCi_STATUS[MISCV] for usable addr on Intel only "Ghannam, Yazen" <Yazen.Ghannam@amd.com> - 2017-04-18 23:30 +0200
Re: [RFC PATCH] x86/mce: Check MCi_STATUS[MISCV] for usable addr on Intel only Borislav Petkov <bp@alien8.de> - 2017-04-19 00:20 +0200
[tip:ras/core] x86/mce: Check MCi_STATUS[MISCV] for usable addr on Intel only tip-bot for Borislav Petkov <tipbot@zytor.com> - 2017-04-19 12:20 +0200
| From | Borislav Petkov <bp@suse.de> |
|---|---|
| Date | 2017-04-18 20:40 +0200 |
| Subject | [RFC PATCH] x86/mce: Check MCi_STATUS[MISCV] for usable addr on Intel only |
| Message-ID | <txGcG-140-31@gated-at.bofh.it> |
mce_usable_address() does a bunch of basic sanity checks to verify
whether the address reported with the error is usable for further
processing. However, we do check MCi_STATUS[MISCV] and that is not
needed on AMD as that bit says that there's additional information about
the logged error in the MCi_MISCj banks.
But we don't need that to know whether the address is usable - we only
need to know whether the physical address is valid - i.e., ADDRV.
[ On Intel the MISCV bit is needed to perform additional checks to
determine whether the reported address is a physical one, etc. ]
Signed-off-by: Borislav Petkov <bp@suse.de>
Cc: "Ghannam, Yazen" <Yazen.Ghannam@amd.com>
---
Right, so I think we don't need to look at MISCV on AMD to check whether
the address is usable because ADDRV already denotes that MCi_ADDR has
the physical address. Yes?
arch/x86/kernel/cpu/mcheck/mce.c | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c
index d409e21ec275..5abd4bf73d6e 100644
--- a/arch/x86/kernel/cpu/mcheck/mce.c
+++ b/arch/x86/kernel/cpu/mcheck/mce.c
@@ -480,17 +480,22 @@ static void mce_report_event(struct pt_regs *regs)
*/
static int mce_usable_address(struct mce *m)
{
- if (!(m->status & MCI_STATUS_MISCV) || !(m->status & MCI_STATUS_ADDRV))
+ if (!(m->status & MCI_STATUS_ADDRV))
return 0;
/* Checks after this one are Intel-specific: */
if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
return 1;
+ if (!(m->status & MCI_STATUS_MISCV))
+ return 0;
+
if (MCI_MISC_ADDR_LSB(m->misc) > PAGE_SHIFT)
return 0;
+
if (MCI_MISC_ADDR_MODE(m->misc) != MCI_MISC_ADDR_PHYS)
return 0;
+
return 1;
}
--
2.11.0
--
Regards/Gruss,
Boris.
Good mailing practices for 400: avoid top-posting and trim the reply.
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| From | "Ghannam, Yazen" <Yazen.Ghannam@amd.com> |
|---|---|
| Date | 2017-04-18 23:30 +0200 |
| Message-ID | <txIRc-2HH-9@gated-at.bofh.it> |
| In reply to | #1625536 |
> -----Original Message----- > From: linux-edac-owner@vger.kernel.org [mailto:linux-edac- > owner@vger.kernel.org] On Behalf Of Borislav Petkov > Sent: Tuesday, April 18, 2017 2:39 PM > To: Ghannam, Yazen <Yazen.Ghannam@amd.com> > Cc: Tony Luck <tony.luck@intel.com>; linux-edac <linux- > edac@vger.kernel.org>; lkml <linux-kernel@vger.kernel.org> > Subject: [RFC PATCH] x86/mce: Check MCi_STATUS[MISCV] for usable addr on > Intel only > > mce_usable_address() does a bunch of basic sanity checks to verify whether > the address reported with the error is usable for further processing. > However, we do check MCi_STATUS[MISCV] and that is not needed on AMD as > that bit says that there's additional information about the logged error in the > MCi_MISCj banks. > > But we don't need that to know whether the address is usable - we only need > to know whether the physical address is valid - i.e., ADDRV. > > [ On Intel the MISCV bit is needed to perform additional checks to > determine whether the reported address is a physical one, etc. ] > > Signed-off-by: Borislav Petkov <bp@suse.de> > Cc: "Ghannam, Yazen" <Yazen.Ghannam@amd.com> > --- > > Right, so I think we don't need to look at MISCV on AMD to check whether the > address is usable because ADDRV already denotes that MCi_ADDR has the > physical address. Yes? > We definitely don't need to look at MiscV. But the value in MCA_ADDR isn't necessarily a system physical address. It can be, or it can be a normalized address in the case of UMCs, or it can a set/way for caches. So it depends on the bank type and error type. All this may just be for SMCA systems though. I need to double check. Thanks, Yazen
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| From | Borislav Petkov <bp@alien8.de> |
|---|---|
| Date | 2017-04-19 00:20 +0200 |
| Message-ID | <txJDz-3bW-5@gated-at.bofh.it> |
| In reply to | #1625660 |
On Tue, Apr 18, 2017 at 09:26:03PM +0000, Ghannam, Yazen wrote:
> We definitely don't need to look at MiscV.
>
> But the value in MCA_ADDR isn't necessarily a system physical address. It can be,
> or it can be a normalized address in the case of UMCs, or it can a set/way for caches.
> So it depends on the bank type and error type.
Right, this is all future work. mce_usable_address() would need some
beefing up then.
> All this may just be for SMCA systems though. I need to double check.
Thanks!
--
Regards/Gruss,
Boris.
Good mailing practices for 400: avoid top-posting and trim the reply.
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| From | tip-bot for Borislav Petkov <tipbot@zytor.com> |
|---|---|
| Date | 2017-04-19 12:20 +0200 |
| Subject | [tip:ras/core] x86/mce: Check MCi_STATUS[MISCV] for usable addr on Intel only |
| Message-ID | <txUSm-2dE-19@gated-at.bofh.it> |
| In reply to | #1625536 |
Commit-ID: c6a9583fb41c8bd017f643d5bc90a0fe0a92fe43
Gitweb: http://git.kernel.org/tip/c6a9583fb41c8bd017f643d5bc90a0fe0a92fe43
Author: Borislav Petkov <bp@suse.de>
AuthorDate: Tue, 18 Apr 2017 20:39:24 +0200
Committer: Thomas Gleixner <tglx@linutronix.de>
CommitDate: Wed, 19 Apr 2017 12:04:46 +0200
x86/mce: Check MCi_STATUS[MISCV] for usable addr on Intel only
mce_usable_address() does a bunch of basic sanity checks to verify
whether the address reported with the error is usable for further
processing. However, we do check MCi_STATUS[MISCV] and that is not
needed on AMD as that bit says that there's additional information about
the logged error in the MCi_MISCj banks.
But we don't need that to know whether the address is usable - we only
need to know whether the physical address is valid - i.e., ADDRV.
On Intel the MISCV bit is needed to perform additional checks to determine
whether the reported address is a physical one, etc.
Signed-off-by: Borislav Petkov <bp@suse.de>
Cc: Yazen Ghannam <yazen.ghannam@amd.com>
Cc: Tony Luck <tony.luck@intel.com>
Cc: linux-edac <linux-edac@vger.kernel.org>
Link: http://lkml.kernel.org/r/20170418183924.6agjkebilwqj26or@pd.tnic
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
---
arch/x86/kernel/cpu/mcheck/mce.c | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c
index 9d41ec8..4a29f74 100644
--- a/arch/x86/kernel/cpu/mcheck/mce.c
+++ b/arch/x86/kernel/cpu/mcheck/mce.c
@@ -491,17 +491,22 @@ static void mce_report_event(struct pt_regs *regs)
*/
static int mce_usable_address(struct mce *m)
{
- if (!(m->status & MCI_STATUS_MISCV) || !(m->status & MCI_STATUS_ADDRV))
+ if (!(m->status & MCI_STATUS_ADDRV))
return 0;
/* Checks after this one are Intel-specific: */
if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
return 1;
+ if (!(m->status & MCI_STATUS_MISCV))
+ return 0;
+
if (MCI_MISC_ADDR_LSB(m->misc) > PAGE_SHIFT)
return 0;
+
if (MCI_MISC_ADDR_MODE(m->misc) != MCI_MISC_ADDR_PHYS)
return 0;
+
return 1;
}
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