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[PATCH v3 0/6] bus: brcmstb_gisb: add support for GISBv7 arbiter

Started byDoug Berger <opendmb@gmail.com>
First post2017-03-30 02:40 +0200
Last post2017-03-30 21:40 +0200
Articles 6 — 3 participants

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  [PATCH v3 0/6] bus: brcmstb_gisb: add support for GISBv7 arbiter Doug Berger <opendmb@gmail.com> - 2017-03-30 02:40 +0200
    [PATCH v3 6/6] bus: brcmstb_gisb: update to support new revision Doug Berger <opendmb@gmail.com> - 2017-03-30 02:40 +0200
    [PATCH v3 5/6] bus: brcmstb_gisb: enable driver for ARM64 architecture Doug Berger <opendmb@gmail.com> - 2017-03-30 02:40 +0200
    Re: [PATCH v3 0/6] bus: brcmstb_gisb: add support for GISBv7 arbiter Florian Fainelli <f.fainelli@gmail.com> - 2017-03-30 18:40 +0200
      Re: [PATCH v3 0/6] bus: brcmstb_gisb: add support for GISBv7 arbiter Mark Rutland <mark.rutland@arm.com> - 2017-03-30 20:30 +0200
        Re: [PATCH v3 0/6] bus: brcmstb_gisb: add support for GISBv7 arbiter Florian Fainelli <f.fainelli@gmail.com> - 2017-03-30 21:40 +0200

#1612466 — [PATCH v3 0/6] bus: brcmstb_gisb: add support for GISBv7 arbiter

FromDoug Berger <opendmb@gmail.com>
Date2017-03-30 02:40 +0200
Subject[PATCH v3 0/6] bus: brcmstb_gisb: add support for GISBv7 arbiter
Message-ID<tqwi5-6vs-3@gated-at.bofh.it>
This patch set contains changes to enable the GISB arbiter driver
on the latest ARM64 architecture Set-Top Box chips from Broadcom.

Since the ARM64 architecture does not support the hooking of low
level fault handlers the driver has been adjusted to depend solely
on GISB interrupts and notify events to provide diagnostic
messaging.  The GISB hardware still triggers bus faults for the
processor so the default low-level aborts will occur and will be
handled based on the architecture specific kernel implementation.

While this tends to obsure the GISB error messaging it is still
reasonable so the same approach is applied to the ARM architecture
for consistency.

The patches also correct some issues with the existing driver
and add the new register map for the GISBv7 hardware first
appearing in the BCM7278 device.

Changes since v2 at [2]:
 - Removed code associated with enabling the hooking of ARM64
   memory faults as well as the code that hooks them for both
   ARM and ARM64 architectures within the GISB arbiter driver.
 - Created separate notifiers for die and panic events to
   prevent list corruption, and substituted the notifier return
   name for the previous magic number (Thanks Mark!)

Changes since v1 at [1]:
 - Removed code associated with hooking SError handling in favor
   of a registered notifier (Thanks Mark!)
 - Removed an unnecessary explicit cast (Thanks Gregory!)

[1] https://lkml.org/lkml/2017/3/24/413
[2] https://lkml.org/lkml/2017/3/28/1125

Doug Berger (6):
  bus: brcmstb_gisb: Use register offsets with writes too
  bus: brcmstb_gisb: correct support for 64-bit address output
  bus: brcmstb_gisb: add notifier handling
  bus: brcmstb_gisb: remove low-level ARM hooks
  bus: brcmstb_gisb: enable driver for ARM64 architecture
  bus: brcmstb_gisb: update to support new revision

 .../devicetree/bindings/bus/brcm,gisb-arb.txt      |   3 +-
 drivers/bus/Kconfig                                |   2 +-
 drivers/bus/brcmstb_gisb.c                         | 121 ++++++++++++---------
 3 files changed, 75 insertions(+), 51 deletions(-)

-- 
2.12.0

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#1612467 — [PATCH v3 6/6] bus: brcmstb_gisb: update to support new revision

FromDoug Berger <opendmb@gmail.com>
Date2017-03-30 02:40 +0200
Subject[PATCH v3 6/6] bus: brcmstb_gisb: update to support new revision
Message-ID<tqwi5-6vs-19@gated-at.bofh.it>
In reply to#1612466
The 7278 introduces a new version of this core.  This
commit adds support for that revision.

Signed-off-by: Doug Berger <opendmb@gmail.com>
---
 Documentation/devicetree/bindings/bus/brcm,gisb-arb.txt |  3 ++-
 drivers/bus/brcmstb_gisb.c                              | 10 ++++++++++
 2 files changed, 12 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/bus/brcm,gisb-arb.txt b/Documentation/devicetree/bindings/bus/brcm,gisb-arb.txt
index 1eceefb20f01..8a6c3c2e58fe 100644
--- a/Documentation/devicetree/bindings/bus/brcm,gisb-arb.txt
+++ b/Documentation/devicetree/bindings/bus/brcm,gisb-arb.txt
@@ -3,7 +3,8 @@ Broadcom GISB bus Arbiter controller
 Required properties:
 
 - compatible:
-    "brcm,gisb-arb" or "brcm,bcm7445-gisb-arb" for 28nm chips
+    "brcm,bcm7278-gisb-arb" for V7 28nm chips
+    "brcm,gisb-arb" or "brcm,bcm7445-gisb-arb" for other 28nm chips
     "brcm,bcm7435-gisb-arb" for newer 40nm chips
     "brcm,bcm7400-gisb-arb" for older 40nm chips and all 65nm chips
     "brcm,bcm7038-gisb-arb" for 130nm chips
diff --git a/drivers/bus/brcmstb_gisb.c b/drivers/bus/brcmstb_gisb.c
index 3fbc116e6b95..68ac3e93b600 100644
--- a/drivers/bus/brcmstb_gisb.c
+++ b/drivers/bus/brcmstb_gisb.c
@@ -56,6 +56,15 @@ static const int gisb_offsets_bcm7038[] = {
 	[ARB_ERR_CAP_MASTER]	= -1,
 };
 
+static const int gisb_offsets_bcm7278[] = {
+	[ARB_TIMER]		= 0x008,
+	[ARB_ERR_CAP_CLR]	= 0x7f8,
+	[ARB_ERR_CAP_HI_ADDR]	= -1,
+	[ARB_ERR_CAP_ADDR]	= 0x7e0,
+	[ARB_ERR_CAP_STATUS]	= 0x7f0,
+	[ARB_ERR_CAP_MASTER]	= 0x7f4,
+};
+
 static const int gisb_offsets_bcm7400[] = {
 	[ARB_TIMER]		= 0x00c,
 	[ARB_ERR_CAP_CLR]	= 0x0c8,
@@ -307,6 +316,7 @@ static const struct of_device_id brcmstb_gisb_arb_of_match[] = {
 	{ .compatible = "brcm,bcm7445-gisb-arb", .data = gisb_offsets_bcm7445 },
 	{ .compatible = "brcm,bcm7435-gisb-arb", .data = gisb_offsets_bcm7435 },
 	{ .compatible = "brcm,bcm7400-gisb-arb", .data = gisb_offsets_bcm7400 },
+	{ .compatible = "brcm,bcm7278-gisb-arb", .data = gisb_offsets_bcm7278 },
 	{ .compatible = "brcm,bcm7038-gisb-arb", .data = gisb_offsets_bcm7038 },
 	{ },
 };
-- 
2.12.0

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#1612468 — [PATCH v3 5/6] bus: brcmstb_gisb: enable driver for ARM64 architecture

FromDoug Berger <opendmb@gmail.com>
Date2017-03-30 02:40 +0200
Subject[PATCH v3 5/6] bus: brcmstb_gisb: enable driver for ARM64 architecture
Message-ID<tqwi5-6vs-21@gated-at.bofh.it>
In reply to#1612466
The ARM64 architecture can provide meaningful diagnostic
output from the GISB arbiter solely from interrupts and
notifiers without the need to hook the low level fault
handlers.

Signed-off-by: Doug Berger <opendmb@gmail.com>
---
 drivers/bus/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/bus/Kconfig b/drivers/bus/Kconfig
index 0a52da439abf..d2a5f1184022 100644
--- a/drivers/bus/Kconfig
+++ b/drivers/bus/Kconfig
@@ -57,7 +57,7 @@ config ARM_CCN
 
 config BRCMSTB_GISB_ARB
 	bool "Broadcom STB GISB bus arbiter"
-	depends on ARM || MIPS
+	depends on ARM || ARM64 || MIPS
 	default ARCH_BRCMSTB || BMIPS_GENERIC
 	help
 	  Driver for the Broadcom Set Top Box System-on-a-chip internal bus
-- 
2.12.0

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#1613273

FromFlorian Fainelli <f.fainelli@gmail.com>
Date2017-03-30 18:40 +0200
Message-ID<tqLh7-GX-1@gated-at.bofh.it>
In reply to#1612466
On 03/29/2017 05:29 PM, Doug Berger wrote:
> This patch set contains changes to enable the GISB arbiter driver
> on the latest ARM64 architecture Set-Top Box chips from Broadcom.
> 
> Since the ARM64 architecture does not support the hooking of low
> level fault handlers the driver has been adjusted to depend solely
> on GISB interrupts and notify events to provide diagnostic
> messaging.  The GISB hardware still triggers bus faults for the
> processor so the default low-level aborts will occur and will be
> handled based on the architecture specific kernel implementation.
> 
> While this tends to obsure the GISB error messaging it is still
> reasonable so the same approach is applied to the ARM architecture
> for consistency.
> 
> The patches also correct some issues with the existing driver
> and add the new register map for the GISBv7 hardware first
> appearing in the BCM7278 device.

This all looks great to me, and since there are no more ARM64
dependencies I can take this via the Broadcom ARM/ARM64 SoC pull requests.

Mark, are you also happy with this v3?

Thanks Doug!

> 
> Changes since v2 at [2]:
>  - Removed code associated with enabling the hooking of ARM64
>    memory faults as well as the code that hooks them for both
>    ARM and ARM64 architectures within the GISB arbiter driver.
>  - Created separate notifiers for die and panic events to
>    prevent list corruption, and substituted the notifier return
>    name for the previous magic number (Thanks Mark!)
> 
> Changes since v1 at [1]:
>  - Removed code associated with hooking SError handling in favor
>    of a registered notifier (Thanks Mark!)
>  - Removed an unnecessary explicit cast (Thanks Gregory!)
> 
> [1] https://lkml.org/lkml/2017/3/24/413
> [2] https://lkml.org/lkml/2017/3/28/1125
> 
> Doug Berger (6):
>   bus: brcmstb_gisb: Use register offsets with writes too
>   bus: brcmstb_gisb: correct support for 64-bit address output
>   bus: brcmstb_gisb: add notifier handling
>   bus: brcmstb_gisb: remove low-level ARM hooks
>   bus: brcmstb_gisb: enable driver for ARM64 architecture
>   bus: brcmstb_gisb: update to support new revision
> 
>  .../devicetree/bindings/bus/brcm,gisb-arb.txt      |   3 +-
>  drivers/bus/Kconfig                                |   2 +-
>  drivers/bus/brcmstb_gisb.c                         | 121 ++++++++++++---------
>  3 files changed, 75 insertions(+), 51 deletions(-)
> 


-- 
Florian

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#1613348

FromMark Rutland <mark.rutland@arm.com>
Date2017-03-30 20:30 +0200
Message-ID<tqMZA-1Yh-11@gated-at.bofh.it>
In reply to#1613273
On Thu, Mar 30, 2017 at 09:33:32AM -0700, Florian Fainelli wrote:
> On 03/29/2017 05:29 PM, Doug Berger wrote:
> > This patch set contains changes to enable the GISB arbiter driver
> > on the latest ARM64 architecture Set-Top Box chips from Broadcom.
> > 
> > Since the ARM64 architecture does not support the hooking of low
> > level fault handlers the driver has been adjusted to depend solely
> > on GISB interrupts and notify events to provide diagnostic
> > messaging.  The GISB hardware still triggers bus faults for the
> > processor so the default low-level aborts will occur and will be
> > handled based on the architecture specific kernel implementation.
> > 
> > While this tends to obsure the GISB error messaging it is still
> > reasonable so the same approach is applied to the ARM architecture
> > for consistency.
> > 
> > The patches also correct some issues with the existing driver
> > and add the new register map for the GISBv7 hardware first
> > appearing in the BCM7278 device.
> 
> This all looks great to me, and since there are no more ARM64
> dependencies I can take this via the Broadcom ARM/ARM64 SoC pull requests.
> 
> Mark, are you also happy with this v3?

It looks fine by me.

Thanks,
Mark.

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#1613393

FromFlorian Fainelli <f.fainelli@gmail.com>
Date2017-03-30 21:40 +0200
Message-ID<tqO5j-2G9-5@gated-at.bofh.it>
In reply to#1613348
On 03/30/2017 11:19 AM, Mark Rutland wrote:
> On Thu, Mar 30, 2017 at 09:33:32AM -0700, Florian Fainelli wrote:
>> On 03/29/2017 05:29 PM, Doug Berger wrote:
>>> This patch set contains changes to enable the GISB arbiter driver
>>> on the latest ARM64 architecture Set-Top Box chips from Broadcom.
>>>
>>> Since the ARM64 architecture does not support the hooking of low
>>> level fault handlers the driver has been adjusted to depend solely
>>> on GISB interrupts and notify events to provide diagnostic
>>> messaging.  The GISB hardware still triggers bus faults for the
>>> processor so the default low-level aborts will occur and will be
>>> handled based on the architecture specific kernel implementation.
>>>
>>> While this tends to obsure the GISB error messaging it is still
>>> reasonable so the same approach is applied to the ARM architecture
>>> for consistency.
>>>
>>> The patches also correct some issues with the existing driver
>>> and add the new register map for the GISBv7 hardware first
>>> appearing in the BCM7278 device.
>>
>> This all looks great to me, and since there are no more ARM64
>> dependencies I can take this via the Broadcom ARM/ARM64 SoC pull requests.
>>
>> Mark, are you also happy with this v3?
> 
> It looks fine by me.

Series applied to drivers/next, thanks everyone!
-- 
Florian

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