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Groups > linux.kernel > #1599381 > unrolled thread

[PATCH v4 0/7] PCI: dwc: Miscellaneous fixes and cleanups

Started byKishon Vijay Abraham I <kishon@ti.com>
First post2017-03-13 14:50 +0100
Last post2017-03-13 14:50 +0100
Articles 6 — 2 participants

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Contents

  [PATCH v4 0/7] PCI: dwc: Miscellaneous fixes and cleanups Kishon Vijay Abraham I <kishon@ti.com> - 2017-03-13 14:50 +0100
    [PATCH v4 1/7] PCI: dwc: designware: Add new *ops* for cpu addr fixup Kishon Vijay Abraham I <kishon@ti.com> - 2017-03-13 14:50 +0100
    [PATCH v4 7/7] PCI: dwc: dra7xx: Push request_irq call to the bottom of probe Kishon Vijay Abraham I <kishon@ti.com> - 2017-03-13 14:50 +0100
    [PATCH v4 5/7] PCI: dwc: all: Modify dbi accessors to access data of  4/2/1 bytes Kishon Vijay Abraham I <kishon@ti.com> - 2017-03-13 14:50 +0100
      Re: [PATCH v4 5/7] PCI: dwc: all: Modify dbi accessors to access data  of 4/2/1 bytes Niklas Cassel <niklas.cassel@axis.com> - 2017-03-13 15:40 +0100
    [PATCH v4 3/7] PCI: dwc: artpec6: Populate cpu_addr_fixup ops Kishon Vijay Abraham I <kishon@ti.com> - 2017-03-13 14:50 +0100

#1599381 — [PATCH v4 0/7] PCI: dwc: Miscellaneous fixes and cleanups

FromKishon Vijay Abraham I <kishon@ti.com>
Date2017-03-13 14:50 +0100
Subject[PATCH v4 0/7] PCI: dwc: Miscellaneous fixes and cleanups
Message-ID<tkywh-1es-13@gated-at.bofh.it>
This should be the final set of cleanups/fixes before endpoint
support can be merged.

Keerthy's patch is a general fix in dra7xx driver and is not
directly related to endpoint mode.

This v1 of this series was previously sent with a different
cover letter $subject [1]

Changes from v3:
*) instead of changing all the callers of dbi accessors (taking
   dbi_base and size), manage it using static inline as suggested
   by Niklas (used static inline instead of macros because of
   checkpatch error).

Changes from v2:
*) Kconfig changes that was spilled into a patch is removed.
*) In addition to renaming _unroll() to _ob_unroll(), all the
   _unroll configurations is also moved a separate function.

Changes from v1:
*) included a patch to rename _unroll() to _ob_unroll() as
   similar thing has to be done for inbound window in the case
   of EP mode.
*) used 'size_t' instead of 'int' for specifying the size
   in read_dbi/write_dbi function arguments.
*) Populate cpu_addr_fixup ops for artpec6 as suggested by
   Niklas

This series is based on 4.11-rc1

[1] -> https://lkml.org/lkml/2017/2/16/270

Keerthy (1):
  PCI: dwc: dra7xx: Push request_irq call to the bottom of probe

Kishon Vijay Abraham I (6):
  PCI: dwc: designware: Add new *ops* for cpu addr fixup
  PCI: dwc: dra7xx: Populate cpu_addr_fixup ops
  PCI: dwc: artpec6: Populate cpu_addr_fixup ops
  PCI: dwc: all: Modify dbi accessors to take dbi_base as argument
  PCI: dwc: all: Modify dbi accessors to access data of  4/2/1 bytes
  PCI: dwc: designware: Move _unroll configurations to a separate
    function

 drivers/pci/dwc/pci-dra7xx.c      |  25 +++----
 drivers/pci/dwc/pci-exynos.c      |  14 ++--
 drivers/pci/dwc/pcie-artpec6.c    |  15 +++--
 drivers/pci/dwc/pcie-designware.c | 133 ++++++++++++++++++++++++--------------
 drivers/pci/dwc/pcie-designware.h |  23 +++++--
 5 files changed, 135 insertions(+), 75 deletions(-)

-- 
2.11.0

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#1599382 — [PATCH v4 1/7] PCI: dwc: designware: Add new *ops* for cpu addr fixup

FromKishon Vijay Abraham I <kishon@ti.com>
Date2017-03-13 14:50 +0100
Subject[PATCH v4 1/7] PCI: dwc: designware: Add new *ops* for cpu addr fixup
Message-ID<tkywi-1es-33@gated-at.bofh.it>
In reply to#1599381
Some platforms (like dra7xx) require only the least 28 bits of the
corresponding 32 bit CPU address to be programmed in the address
translation unit. This modified address is stored in io_base/mem_base/
cfg0_base/cfg1_base in dra7xx_pcie_host_init. While this is okay for
host mode where the address range is fixed, device mode requires
different addresses to be programmed based on the host buffer address.
Add a new ops to get the least 28 bits of the corresponding 32 bit
CPU address and invoke it before programming the address translation
unit.

Acked-by: Joao Pinto <jpinto@synopsys.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
 drivers/pci/dwc/pcie-designware.c | 3 +++
 drivers/pci/dwc/pcie-designware.h | 1 +
 2 files changed, 4 insertions(+)

diff --git a/drivers/pci/dwc/pcie-designware.c b/drivers/pci/dwc/pcie-designware.c
index 7e1fb7d6643c..3eaf3ccdc118 100644
--- a/drivers/pci/dwc/pcie-designware.c
+++ b/drivers/pci/dwc/pcie-designware.c
@@ -97,6 +97,9 @@ void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type,
 {
 	u32 retries, val;
 
+	if (pci->ops->cpu_addr_fixup)
+		cpu_addr = pci->ops->cpu_addr_fixup(cpu_addr);
+
 	if (pci->iatu_unroll_enabled) {
 		dw_pcie_writel_unroll(pci, index, PCIE_ATU_UNR_LOWER_BASE,
 				      lower_32_bits(cpu_addr));
diff --git a/drivers/pci/dwc/pcie-designware.h b/drivers/pci/dwc/pcie-designware.h
index cd3b8713fe50..8f3dcb2b099b 100644
--- a/drivers/pci/dwc/pcie-designware.h
+++ b/drivers/pci/dwc/pcie-designware.h
@@ -143,6 +143,7 @@ struct pcie_port {
 };
 
 struct dw_pcie_ops {
+	u64	(*cpu_addr_fixup)(u64 cpu_addr);
 	u32	(*readl_dbi)(struct dw_pcie *pcie, u32 reg);
 	void	(*writel_dbi)(struct dw_pcie *pcie, u32 reg, u32 val);
 	int	(*link_up)(struct dw_pcie *pcie);
-- 
2.11.0

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#1599383 — [PATCH v4 7/7] PCI: dwc: dra7xx: Push request_irq call to the bottom of probe

FromKishon Vijay Abraham I <kishon@ti.com>
Date2017-03-13 14:50 +0100
Subject[PATCH v4 7/7] PCI: dwc: dra7xx: Push request_irq call to the bottom of probe
Message-ID<tkywi-1es-27@gated-at.bofh.it>
In reply to#1599381
From: Keerthy <j-keerthy@ti.com>

Currently devm_request_irq is being called before base, pci fields
of dra7xx_pcie structure are populated. It is called even before
pm_runtime_enable and pm_runtime_get_sync are called. This will
lead to exceptions if in case an interrupt is triggered before
the all of the above are done. Hence push the devm_request_irq
call to the end of the probe.

Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
 drivers/pci/dwc/pci-dra7xx.c | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/pci/dwc/pci-dra7xx.c b/drivers/pci/dwc/pci-dra7xx.c
index 07c45ec07662..7c9ed6a6675c 100644
--- a/drivers/pci/dwc/pci-dra7xx.c
+++ b/drivers/pci/dwc/pci-dra7xx.c
@@ -410,13 +410,6 @@ static int __init dra7xx_pcie_probe(struct platform_device *pdev)
 		return -EINVAL;
 	}
 
-	ret = devm_request_irq(dev, irq, dra7xx_pcie_irq_handler,
-			       IRQF_SHARED, "dra7xx-pcie-main", dra7xx);
-	if (ret) {
-		dev_err(dev, "failed to request irq\n");
-		return ret;
-	}
-
 	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ti_conf");
 	base = devm_ioremap_nocache(dev, res->start, resource_size(res));
 	if (!base)
@@ -478,6 +471,13 @@ static int __init dra7xx_pcie_probe(struct platform_device *pdev)
 	if (ret < 0)
 		goto err_gpio;
 
+	ret = devm_request_irq(dev, irq, dra7xx_pcie_irq_handler,
+			       IRQF_SHARED, "dra7xx-pcie-main", dra7xx);
+	if (ret) {
+		dev_err(dev, "failed to request irq\n");
+		goto err_gpio;
+	}
+
 	return 0;
 
 err_gpio:
-- 
2.11.0

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#1599384 — [PATCH v4 5/7] PCI: dwc: all: Modify dbi accessors to access data of 4/2/1 bytes

FromKishon Vijay Abraham I <kishon@ti.com>
Date2017-03-13 14:50 +0100
Subject[PATCH v4 5/7] PCI: dwc: all: Modify dbi accessors to access data of 4/2/1 bytes
Message-ID<tkywj-1es-43@gated-at.bofh.it>
In reply to#1599381
Previously dbi accessors can be used to access data of size 4
bytes. But there might be situations (like accessing
MSI_MESSAGE_CONTROL in order to set/get the number of required
MSI interrupts in EP mode) where dbi accessors must
be used to access data of size 2. This is in preparation for
adding endpoint mode support to designware driver.

Cc: Jingoo Han <jingoohan1@gmail.com>
Cc: Joao Pinto <Joao.Pinto@synopsys.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
 drivers/pci/dwc/pci-exynos.c      | 16 ++++++++--------
 drivers/pci/dwc/pcie-designware.c | 34 ++++++++++++++++++++++++----------
 drivers/pci/dwc/pcie-designware.h | 20 +++++++++++---------
 3 files changed, 43 insertions(+), 27 deletions(-)

diff --git a/drivers/pci/dwc/pci-exynos.c b/drivers/pci/dwc/pci-exynos.c
index a0d40f74b88d..37d6d2b7378f 100644
--- a/drivers/pci/dwc/pci-exynos.c
+++ b/drivers/pci/dwc/pci-exynos.c
@@ -521,25 +521,25 @@ static void exynos_pcie_enable_interrupts(struct exynos_pcie *ep)
 		exynos_pcie_msi_init(ep);
 }
 
-static u32 exynos_pcie_readl_dbi(struct dw_pcie *pci, void __iomem *base,
-				 u32 reg)
+static u32 exynos_pcie_read_dbi(struct dw_pcie *pci, void __iomem *base,
+				u32 reg, size_t size)
 {
 	struct exynos_pcie *ep = to_exynos_pcie(pci);
 	u32 val;
 
 	exynos_pcie_sideband_dbi_r_mode(ep, true);
-	val = readl(base + reg);
+	dw_pcie_read(base + reg, size, &val);
 	exynos_pcie_sideband_dbi_r_mode(ep, false);
 	return val;
 }
 
-static void exynos_pcie_writel_dbi(struct dw_pcie *pci, void __iomem *base,
-				   u32 reg, u32 val)
+static void exynos_pcie_write_dbi(struct dw_pcie *pci, void __iomem *base,
+				  u32 reg, size_t size, u32 val)
 {
 	struct exynos_pcie *ep = to_exynos_pcie(pci);
 
 	exynos_pcie_sideband_dbi_w_mode(ep, true);
-	writel(val, base + reg);
+	dw_pcie_write(base + reg, size, val);
 	exynos_pcie_sideband_dbi_w_mode(ep, false);
 }
 
@@ -646,8 +646,8 @@ static int __init exynos_add_pcie_port(struct exynos_pcie *ep,
 }
 
 static const struct dw_pcie_ops dw_pcie_ops = {
-	.readl_dbi = exynos_pcie_readl_dbi,
-	.writel_dbi = exynos_pcie_writel_dbi,
+	.read_dbi = exynos_pcie_read_dbi,
+	.write_dbi = exynos_pcie_write_dbi,
 	.link_up = exynos_pcie_link_up,
 };
 
diff --git a/drivers/pci/dwc/pcie-designware.c b/drivers/pci/dwc/pcie-designware.c
index ea403e2240cf..734acac1926d 100644
--- a/drivers/pci/dwc/pcie-designware.c
+++ b/drivers/pci/dwc/pcie-designware.c
@@ -61,21 +61,35 @@ int dw_pcie_write(void __iomem *addr, int size, u32 val)
 	return PCIBIOS_SUCCESSFUL;
 }
 
-u32 __dw_pcie_readl_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg)
+u32 __dw_pcie_read_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg,
+		       size_t size)
 {
-	if (pci->ops->readl_dbi)
-		return pci->ops->readl_dbi(pci, base, reg);
+	int ret;
+	u32 val;
+
+	if (pci->ops->read_dbi)
+		return pci->ops->read_dbi(pci, base, reg, size);
 
-	return readl(base + reg);
+	ret = dw_pcie_read(base + reg, size, &val);
+	if (ret)
+		dev_err(pci->dev, "read DBI address failed\n");
+
+	return val;
 }
 
-void __dw_pcie_writel_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg,
-			  u32 val)
+void __dw_pcie_write_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg,
+			 size_t size, u32 val)
 {
-	if (pci->ops->writel_dbi)
-		pci->ops->writel_dbi(pci, base, reg, val);
-	else
-		writel(val, base + reg);
+	int ret;
+
+	if (pci->ops->write_dbi) {
+		pci->ops->write_dbi(pci, base, reg, size, val);
+		return;
+	}
+
+	ret = dw_pcie_write(base + reg, size, val);
+	if (ret)
+		dev_err(pci->dev, "write DBI address failed\n");
 }
 
 static u32 dw_pcie_readl_unroll(struct dw_pcie *pci, u32 index, u32 reg)
diff --git a/drivers/pci/dwc/pcie-designware.h b/drivers/pci/dwc/pcie-designware.h
index e97fc4ce7d49..bfaf2b850a88 100644
--- a/drivers/pci/dwc/pcie-designware.h
+++ b/drivers/pci/dwc/pcie-designware.h
@@ -144,9 +144,10 @@ struct pcie_port {
 
 struct dw_pcie_ops {
 	u64	(*cpu_addr_fixup)(u64 cpu_addr);
-	u32	(*readl_dbi)(struct dw_pcie *pcie, void __iomem *base, u32 reg);
-	void	(*writel_dbi)(struct dw_pcie *pcie, void __iomem *base, u32 reg,
-			      u32 val);
+	u32	(*read_dbi)(struct dw_pcie *pcie, void __iomem *base, u32 reg,
+			    size_t size);
+	void	(*write_dbi)(struct dw_pcie *pcie, void __iomem *base, u32 reg,
+			     size_t size, u32 val);
 	int	(*link_up)(struct dw_pcie *pcie);
 };
 
@@ -164,9 +165,10 @@ struct dw_pcie {
 int dw_pcie_read(void __iomem *addr, int size, u32 *val);
 int dw_pcie_write(void __iomem *addr, int size, u32 val);
 
-u32 __dw_pcie_readl_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg);
-void __dw_pcie_writel_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg,
-			  u32 val);
+u32 __dw_pcie_read_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg,
+		       size_t size);
+void __dw_pcie_write_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg,
+			 size_t size, u32 val);
 int dw_pcie_link_up(struct dw_pcie *pci);
 int dw_pcie_wait_for_link(struct dw_pcie *pci);
 void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index,
@@ -174,14 +176,14 @@ void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index,
 			       u32 size);
 void dw_pcie_setup(struct dw_pcie *pci);
 
-static inline dw_pcie_writel_dbi(struct dw_pcie *pci, u32 reg, u32 val)
+static inline void dw_pcie_writel_dbi(struct dw_pcie *pci, u32 reg, u32 val)
 {
-	__dw_pcie_writel_dbi(pci, pci->dbi_base, reg, val);
+	__dw_pcie_write_dbi(pci, pci->dbi_base, reg, 0x4, val);
 }
 
 static inline u32 dw_pcie_readl_dbi(struct dw_pcie *pci, u32 reg)
 {
-	return  __dw_pcie_readl_dbi(pci, pci->dbi_base, reg);
+	return __dw_pcie_read_dbi(pci, pci->dbi_base, reg, 0x4);
 }
 
 #ifdef CONFIG_PCIE_DW_HOST
-- 
2.11.0

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#1599465 — Re: [PATCH v4 5/7] PCI: dwc: all: Modify dbi accessors to access data of 4/2/1 bytes

FromNiklas Cassel <niklas.cassel@axis.com>
Date2017-03-13 15:40 +0100
SubjectRe: [PATCH v4 5/7] PCI: dwc: all: Modify dbi accessors to access data of 4/2/1 bytes
Message-ID<tkziH-1PZ-49@gated-at.bofh.it>
In reply to#1599384
Acked-by: Niklas Cassel <niklas.cassel@axis.com>

On 03/13/2017 02:43 PM, Kishon Vijay Abraham I wrote:
> Previously dbi accessors can be used to access data of size 4
> bytes. But there might be situations (like accessing
> MSI_MESSAGE_CONTROL in order to set/get the number of required
> MSI interrupts in EP mode) where dbi accessors must
> be used to access data of size 2. This is in preparation for
> adding endpoint mode support to designware driver.
>
> Cc: Jingoo Han <jingoohan1@gmail.com>
> Cc: Joao Pinto <Joao.Pinto@synopsys.com>
> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
> ---
>  drivers/pci/dwc/pci-exynos.c      | 16 ++++++++--------
>  drivers/pci/dwc/pcie-designware.c | 34 ++++++++++++++++++++++++----------
>  drivers/pci/dwc/pcie-designware.h | 20 +++++++++++---------
>  3 files changed, 43 insertions(+), 27 deletions(-)
>
> diff --git a/drivers/pci/dwc/pci-exynos.c b/drivers/pci/dwc/pci-exynos.c
> index a0d40f74b88d..37d6d2b7378f 100644
> --- a/drivers/pci/dwc/pci-exynos.c
> +++ b/drivers/pci/dwc/pci-exynos.c
> @@ -521,25 +521,25 @@ static void exynos_pcie_enable_interrupts(struct exynos_pcie *ep)
>  		exynos_pcie_msi_init(ep);
>  }
>  
> -static u32 exynos_pcie_readl_dbi(struct dw_pcie *pci, void __iomem *base,
> -				 u32 reg)
> +static u32 exynos_pcie_read_dbi(struct dw_pcie *pci, void __iomem *base,
> +				u32 reg, size_t size)
>  {
>  	struct exynos_pcie *ep = to_exynos_pcie(pci);
>  	u32 val;
>  
>  	exynos_pcie_sideband_dbi_r_mode(ep, true);
> -	val = readl(base + reg);
> +	dw_pcie_read(base + reg, size, &val);
>  	exynos_pcie_sideband_dbi_r_mode(ep, false);
>  	return val;
>  }
>  
> -static void exynos_pcie_writel_dbi(struct dw_pcie *pci, void __iomem *base,
> -				   u32 reg, u32 val)
> +static void exynos_pcie_write_dbi(struct dw_pcie *pci, void __iomem *base,
> +				  u32 reg, size_t size, u32 val)
>  {
>  	struct exynos_pcie *ep = to_exynos_pcie(pci);
>  
>  	exynos_pcie_sideband_dbi_w_mode(ep, true);
> -	writel(val, base + reg);
> +	dw_pcie_write(base + reg, size, val);
>  	exynos_pcie_sideband_dbi_w_mode(ep, false);
>  }
>  
> @@ -646,8 +646,8 @@ static int __init exynos_add_pcie_port(struct exynos_pcie *ep,
>  }
>  
>  static const struct dw_pcie_ops dw_pcie_ops = {
> -	.readl_dbi = exynos_pcie_readl_dbi,
> -	.writel_dbi = exynos_pcie_writel_dbi,
> +	.read_dbi = exynos_pcie_read_dbi,
> +	.write_dbi = exynos_pcie_write_dbi,
>  	.link_up = exynos_pcie_link_up,
>  };
>  
> diff --git a/drivers/pci/dwc/pcie-designware.c b/drivers/pci/dwc/pcie-designware.c
> index ea403e2240cf..734acac1926d 100644
> --- a/drivers/pci/dwc/pcie-designware.c
> +++ b/drivers/pci/dwc/pcie-designware.c
> @@ -61,21 +61,35 @@ int dw_pcie_write(void __iomem *addr, int size, u32 val)
>  	return PCIBIOS_SUCCESSFUL;
>  }
>  
> -u32 __dw_pcie_readl_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg)
> +u32 __dw_pcie_read_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg,
> +		       size_t size)
>  {
> -	if (pci->ops->readl_dbi)
> -		return pci->ops->readl_dbi(pci, base, reg);
> +	int ret;
> +	u32 val;
> +
> +	if (pci->ops->read_dbi)
> +		return pci->ops->read_dbi(pci, base, reg, size);
>  
> -	return readl(base + reg);
> +	ret = dw_pcie_read(base + reg, size, &val);
> +	if (ret)
> +		dev_err(pci->dev, "read DBI address failed\n");
> +
> +	return val;
>  }
>  
> -void __dw_pcie_writel_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg,
> -			  u32 val)
> +void __dw_pcie_write_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg,
> +			 size_t size, u32 val)
>  {
> -	if (pci->ops->writel_dbi)
> -		pci->ops->writel_dbi(pci, base, reg, val);
> -	else
> -		writel(val, base + reg);
> +	int ret;
> +
> +	if (pci->ops->write_dbi) {
> +		pci->ops->write_dbi(pci, base, reg, size, val);
> +		return;
> +	}
> +
> +	ret = dw_pcie_write(base + reg, size, val);
> +	if (ret)
> +		dev_err(pci->dev, "write DBI address failed\n");
>  }
>  
>  static u32 dw_pcie_readl_unroll(struct dw_pcie *pci, u32 index, u32 reg)
> diff --git a/drivers/pci/dwc/pcie-designware.h b/drivers/pci/dwc/pcie-designware.h
> index e97fc4ce7d49..bfaf2b850a88 100644
> --- a/drivers/pci/dwc/pcie-designware.h
> +++ b/drivers/pci/dwc/pcie-designware.h
> @@ -144,9 +144,10 @@ struct pcie_port {
>  
>  struct dw_pcie_ops {
>  	u64	(*cpu_addr_fixup)(u64 cpu_addr);
> -	u32	(*readl_dbi)(struct dw_pcie *pcie, void __iomem *base, u32 reg);
> -	void	(*writel_dbi)(struct dw_pcie *pcie, void __iomem *base, u32 reg,
> -			      u32 val);
> +	u32	(*read_dbi)(struct dw_pcie *pcie, void __iomem *base, u32 reg,
> +			    size_t size);
> +	void	(*write_dbi)(struct dw_pcie *pcie, void __iomem *base, u32 reg,
> +			     size_t size, u32 val);
>  	int	(*link_up)(struct dw_pcie *pcie);
>  };
>  
> @@ -164,9 +165,10 @@ struct dw_pcie {
>  int dw_pcie_read(void __iomem *addr, int size, u32 *val);
>  int dw_pcie_write(void __iomem *addr, int size, u32 val);
>  
> -u32 __dw_pcie_readl_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg);
> -void __dw_pcie_writel_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg,
> -			  u32 val);
> +u32 __dw_pcie_read_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg,
> +		       size_t size);
> +void __dw_pcie_write_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg,
> +			 size_t size, u32 val);
>  int dw_pcie_link_up(struct dw_pcie *pci);
>  int dw_pcie_wait_for_link(struct dw_pcie *pci);
>  void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index,
> @@ -174,14 +176,14 @@ void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index,
>  			       u32 size);
>  void dw_pcie_setup(struct dw_pcie *pci);
>  
> -static inline dw_pcie_writel_dbi(struct dw_pcie *pci, u32 reg, u32 val)
> +static inline void dw_pcie_writel_dbi(struct dw_pcie *pci, u32 reg, u32 val)
>  {
> -	__dw_pcie_writel_dbi(pci, pci->dbi_base, reg, val);
> +	__dw_pcie_write_dbi(pci, pci->dbi_base, reg, 0x4, val);
>  }
>  
>  static inline u32 dw_pcie_readl_dbi(struct dw_pcie *pci, u32 reg)
>  {
> -	return  __dw_pcie_readl_dbi(pci, pci->dbi_base, reg);
> +	return __dw_pcie_read_dbi(pci, pci->dbi_base, reg, 0x4);
>  }
>  
>  #ifdef CONFIG_PCIE_DW_HOST

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#1599387 — [PATCH v4 3/7] PCI: dwc: artpec6: Populate cpu_addr_fixup ops

FromKishon Vijay Abraham I <kishon@ti.com>
Date2017-03-13 14:50 +0100
Subject[PATCH v4 3/7] PCI: dwc: artpec6: Populate cpu_addr_fixup ops
Message-ID<tkywj-1es-45@gated-at.bofh.it>
In reply to#1599381
Populate cpu_addr_fixup ops to extract the least 28 bits of the
corresponding cpu address.

Cc: Niklas Cassel <niklas.cassel@axis.com>
Acked-by: Niklas Cassel <niklas.cassel@axis.com>
Acked-by: Joao Pinto <jpinto@synopsys.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
 drivers/pci/dwc/pcie-artpec6.c | 15 ++++++++++-----
 1 file changed, 10 insertions(+), 5 deletions(-)

diff --git a/drivers/pci/dwc/pcie-artpec6.c b/drivers/pci/dwc/pcie-artpec6.c
index fcd3ef845883..5b3b3afc0edb 100644
--- a/drivers/pci/dwc/pcie-artpec6.c
+++ b/drivers/pci/dwc/pcie-artpec6.c
@@ -78,6 +78,11 @@ static void artpec6_pcie_writel(struct artpec6_pcie *artpec6_pcie, u32 offset, u
 	regmap_write(artpec6_pcie->regmap, offset, val);
 }
 
+static u64 artpec6_pcie_cpu_addr_fixup(u64 pci_addr)
+{
+	return pci_addr & ARTPEC6_CPU_TO_BUS_ADDR;
+}
+
 static int artpec6_pcie_establish_link(struct artpec6_pcie *artpec6_pcie)
 {
 	struct dw_pcie *pci = artpec6_pcie->pci;
@@ -142,11 +147,6 @@ static int artpec6_pcie_establish_link(struct artpec6_pcie *artpec6_pcie)
 	 */
 	dw_pcie_writel_dbi(pci, MISC_CONTROL_1_OFF, DBI_RO_WR_EN);
 
-	pp->io_base &= ARTPEC6_CPU_TO_BUS_ADDR;
-	pp->mem_base &= ARTPEC6_CPU_TO_BUS_ADDR;
-	pp->cfg0_base &= ARTPEC6_CPU_TO_BUS_ADDR;
-	pp->cfg1_base &= ARTPEC6_CPU_TO_BUS_ADDR;
-
 	/* setup root complex */
 	dw_pcie_setup_rc(pp);
 
@@ -234,6 +234,10 @@ static int artpec6_add_pcie_port(struct artpec6_pcie *artpec6_pcie,
 	return 0;
 }
 
+static const struct dw_pcie_ops dw_pcie_ops = {
+	.cpu_addr_fixup = artpec6_pcie_cpu_addr_fixup,
+};
+
 static int artpec6_pcie_probe(struct platform_device *pdev)
 {
 	struct device *dev = &pdev->dev;
@@ -252,6 +256,7 @@ static int artpec6_pcie_probe(struct platform_device *pdev)
 		return -ENOMEM;
 
 	pci->dev = dev;
+	pci->ops = &dw_pcie_ops;
 
 	artpec6_pcie->pci = pci;
 
-- 
2.11.0

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