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[PATCH v4 1/7] PCI: dwc: designware: Add new *ops* for cpu addr fixup

From Kishon Vijay Abraham I <kishon@ti.com>
Newsgroups linux.kernel
Subject [PATCH v4 1/7] PCI: dwc: designware: Add new *ops* for cpu addr fixup
Date 2017-03-13 14:50 +0100
Message-ID <tkywi-1es-33@gated-at.bofh.it> (permalink)
References <tkywh-1es-13@gated-at.bofh.it>
Organization linux.* mail to news gateway

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Some platforms (like dra7xx) require only the least 28 bits of the
corresponding 32 bit CPU address to be programmed in the address
translation unit. This modified address is stored in io_base/mem_base/
cfg0_base/cfg1_base in dra7xx_pcie_host_init. While this is okay for
host mode where the address range is fixed, device mode requires
different addresses to be programmed based on the host buffer address.
Add a new ops to get the least 28 bits of the corresponding 32 bit
CPU address and invoke it before programming the address translation
unit.

Acked-by: Joao Pinto <jpinto@synopsys.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
 drivers/pci/dwc/pcie-designware.c | 3 +++
 drivers/pci/dwc/pcie-designware.h | 1 +
 2 files changed, 4 insertions(+)

diff --git a/drivers/pci/dwc/pcie-designware.c b/drivers/pci/dwc/pcie-designware.c
index 7e1fb7d6643c..3eaf3ccdc118 100644
--- a/drivers/pci/dwc/pcie-designware.c
+++ b/drivers/pci/dwc/pcie-designware.c
@@ -97,6 +97,9 @@ void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type,
 {
 	u32 retries, val;
 
+	if (pci->ops->cpu_addr_fixup)
+		cpu_addr = pci->ops->cpu_addr_fixup(cpu_addr);
+
 	if (pci->iatu_unroll_enabled) {
 		dw_pcie_writel_unroll(pci, index, PCIE_ATU_UNR_LOWER_BASE,
 				      lower_32_bits(cpu_addr));
diff --git a/drivers/pci/dwc/pcie-designware.h b/drivers/pci/dwc/pcie-designware.h
index cd3b8713fe50..8f3dcb2b099b 100644
--- a/drivers/pci/dwc/pcie-designware.h
+++ b/drivers/pci/dwc/pcie-designware.h
@@ -143,6 +143,7 @@ struct pcie_port {
 };
 
 struct dw_pcie_ops {
+	u64	(*cpu_addr_fixup)(u64 cpu_addr);
 	u32	(*readl_dbi)(struct dw_pcie *pcie, u32 reg);
 	void	(*writel_dbi)(struct dw_pcie *pcie, u32 reg, u32 val);
 	int	(*link_up)(struct dw_pcie *pcie);
-- 
2.11.0

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Thread

[PATCH v4 0/7] PCI: dwc: Miscellaneous fixes and cleanups Kishon Vijay Abraham I <kishon@ti.com> - 2017-03-13 14:50 +0100
  [PATCH v4 1/7] PCI: dwc: designware: Add new *ops* for cpu addr fixup Kishon Vijay Abraham I <kishon@ti.com> - 2017-03-13 14:50 +0100
  [PATCH v4 7/7] PCI: dwc: dra7xx: Push request_irq call to the bottom of probe Kishon Vijay Abraham I <kishon@ti.com> - 2017-03-13 14:50 +0100
  [PATCH v4 5/7] PCI: dwc: all: Modify dbi accessors to access data of  4/2/1 bytes Kishon Vijay Abraham I <kishon@ti.com> - 2017-03-13 14:50 +0100
    Re: [PATCH v4 5/7] PCI: dwc: all: Modify dbi accessors to access data  of 4/2/1 bytes Niklas Cassel <niklas.cassel@axis.com> - 2017-03-13 15:40 +0100
  [PATCH v4 3/7] PCI: dwc: artpec6: Populate cpu_addr_fixup ops Kishon Vijay Abraham I <kishon@ti.com> - 2017-03-13 14:50 +0100

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