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Groups > linux.kernel > #1581561 > unrolled thread
| Started by | Scott Wood <oss@buserror.net> |
|---|---|
| First post | 2017-02-15 19:40 +0100 |
| Last post | 2017-02-16 03:30 +0100 |
| Articles | 2 — 2 participants |
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Re: [PATCH 2/2] clk: qoriq: Separate root input clock for core PLLs on ls1012a Scott Wood <oss@buserror.net> - 2017-02-15 19:40 +0100
RE: [PATCH 2/2] clk: qoriq: Separate root input clock for core PLLs on ls1012a "Y.T. Tang" <yuantian.tang@nxp.com> - 2017-02-16 03:30 +0100
| From | Scott Wood <oss@buserror.net> |
|---|---|
| Date | 2017-02-15 19:40 +0100 |
| Subject | Re: [PATCH 2/2] clk: qoriq: Separate root input clock for core PLLs on ls1012a |
| Message-ID | <tbcEG-3vT-13@gated-at.bofh.it> |
On Wed, 2017-02-15 at 13:47 +0800, yuantian.tang@nxp.com wrote: > From: Tang Yuantian <Yuantian.Tang@nxp.com> > > ls1012a has separate input root clocks for core PLLs versus the > platform PLL, with the latter described as sysclk in the hw docs. > If a second input clock, named "coreclk", is present, this clock will be > used for the core PLLs. > > Signed-off-by: Scott Wood <oss@buserror.net> > Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com> > --- > drivers/clk/clk-qoriq.c | 91 +++++++++++++++++++++++++++++++++++++++++----- Why did you reset the author on these patches? Have you changed anything? Why aren't they marked either v2 or resend? -Scott
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| From | "Y.T. Tang" <yuantian.tang@nxp.com> |
|---|---|
| Date | 2017-02-16 03:30 +0100 |
| Message-ID | <tbjZw-8cO-23@gated-at.bofh.it> |
| In reply to | #1581561 |
> -----Original Message----- > From: Scott Wood [mailto:oss@buserror.net] > Sent: Thursday, February 16, 2017 2:37 AM > To: Y.T. Tang <yuantian.tang@nxp.com>; mturquette@baylibre.com > Cc: sboyd@codeaurora.org; robh+dt@kernel.org; mark.rutland@arm.com; > linux-clk@vger.kernel.org; devicetree@vger.kernel.org; linux- > kernel@vger.kernel.org; linux-arm-kernel@lists.infradead.org > Subject: Re: [PATCH 2/2] clk: qoriq: Separate root input clock for core PLLs on > ls1012a > > On Wed, 2017-02-15 at 13:47 +0800, yuantian.tang@nxp.com wrote: > > From: Tang Yuantian <Yuantian.Tang@nxp.com> > > > > ls1012a has separate input root clocks for core PLLs versus the > > platform PLL, with the latter described as sysclk in the hw docs. > > If a second input clock, named "coreclk", is present, this clock will > > be used for the core PLLs. > > > > Signed-off-by: Scott Wood <oss@buserror.net> > > Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com> > > --- > > drivers/clk/clk-qoriq.c | 91 > > +++++++++++++++++++++++++++++++++++++++++----- > > Why did you reset the author on these patches? Have you changed anything? > Why aren't they marked either v2 or resend? > I should have marked as v2 or resend. If anything changed, I take it over and dropped the 2/3 patch in your original patch set to speed up the merge, which I think so. This patch set blocks other patches and 20 days passed, no any action on it. We can't account on you to push it. That's why I take it over and resend it. All in all, what you suggest to do to make them get accepted ASAP? Regards, Yuantian > -Scott
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