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Groups > linux.kernel > #1581561
| From | Scott Wood <oss@buserror.net> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | Re: [PATCH 2/2] clk: qoriq: Separate root input clock for core PLLs on ls1012a |
| Date | 2017-02-15 19:40 +0100 |
| Message-ID | <tbcEG-3vT-13@gated-at.bofh.it> (permalink) |
| References | <tbcEG-3vT-15@gated-at.bofh.it> <tbcEG-3vT-17@gated-at.bofh.it> |
| Organization | NXP |
On Wed, 2017-02-15 at 13:47 +0800, yuantian.tang@nxp.com wrote: > From: Tang Yuantian <Yuantian.Tang@nxp.com> > > ls1012a has separate input root clocks for core PLLs versus the > platform PLL, with the latter described as sysclk in the hw docs. > If a second input clock, named "coreclk", is present, this clock will be > used for the core PLLs. > > Signed-off-by: Scott Wood <oss@buserror.net> > Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com> > --- > drivers/clk/clk-qoriq.c | 91 +++++++++++++++++++++++++++++++++++++++++----- Why did you reset the author on these patches? Have you changed anything? Why aren't they marked either v2 or resend? -Scott
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Re: [PATCH 2/2] clk: qoriq: Separate root input clock for core PLLs on ls1012a Scott Wood <oss@buserror.net> - 2017-02-15 19:40 +0100 RE: [PATCH 2/2] clk: qoriq: Separate root input clock for core PLLs on ls1012a "Y.T. Tang" <yuantian.tang@nxp.com> - 2017-02-16 03:30 +0100
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