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[PATCH 0/3] irqchip: Miscellaneous fixes for GIC/GICv3

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  [PATCH 0/3] irqchip: Miscellaneous fixes for GIC/GICv3 Suzuki K Poulose <suzuki.poulose@arm.com> - 2017-07-04 12:00 +0200
    [PATCH 2/3] irqchip: gic-v2: Report failures in gic_irq_domain_alloc Suzuki K Poulose <suzuki.poulose@arm.com> - 2017-07-04 12:00 +0200
    [PATCH 1/3] irqchip: gic-v3: Report failures in gic_irq_domain_alloc Suzuki K Poulose <suzuki.poulose@arm.com> - 2017-07-04 12:00 +0200
    [PATCH 3/3] irq: gic-v3: Honor forced affinity setting Suzuki K Poulose <suzuki.poulose@arm.com> - 2017-07-04 12:00 +0200
    Re: [PATCH 0/3] irqchip: Miscellaneous fixes for GIC/GICv3 Marc Zyngier <marc.zyngier@arm.com> - 2017-07-04 12:20 +0200

#1680820 — [PATCH 0/3] irqchip: Miscellaneous fixes for GIC/GICv3

This series contains some fixes for GIC/GIC-v3 to behave as expected
by the generic management layer.

Suzuki K Poulose (3):
  irqchip: gic-v3: Report failures in gic_irq_domain_alloc
  irqchip: gic-v2: Report failures in gic_irq_domain_alloc
  irq: gic-v3: Honor forced affinity setting

 drivers/irqchip/irq-gic-v3.c | 14 +++++++++++---
 drivers/irqchip/irq-gic.c    |  7 +++++--
 2 files changed, 16 insertions(+), 5 deletions(-)

-- 
2.7.5

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#1680823 — [PATCH 2/3] irqchip: gic-v2: Report failures in gic_irq_domain_alloc

If the GIC cannot map an IRQ via irq_domain_ops->alloc(), it doesn't
return an error code.  This can cause a problem with drivers, where
it thinks it has successfully got an IRQ for the device, but requesting
the same ends up failure with -ENOSYS (as the IRQ's chip is not set).

Fixes: commit 9a1091ef0017c ("irqchip: gic: Support hierarchy irq domain.")
Cc: Yingjoe Chen <yingjoe.chen@mediatek.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
---
 drivers/irqchip/irq-gic.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
index 1b1df4f..940c162 100644
--- a/drivers/irqchip/irq-gic.c
+++ b/drivers/irqchip/irq-gic.c
@@ -1027,8 +1027,11 @@ static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
 	if (ret)
 		return ret;
 
-	for (i = 0; i < nr_irqs; i++)
-		gic_irq_domain_map(domain, virq + i, hwirq + i);
+	for (i = 0; i < nr_irqs; i++) {
+		ret = gic_irq_domain_map(domain, virq + i, hwirq + i);
+		if (ret)
+			return ret;
+	}
 
 	return 0;
 }
-- 
2.7.5

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#1680825 — [PATCH 1/3] irqchip: gic-v3: Report failures in gic_irq_domain_alloc

If the GIC cannot map an IRQ via irq_domain_ops->alloc(), it doesn't
return an error code.  This can cause a problem with drivers, where
it thinks it has successfully got an IRQ for the device, but requesting
the same ends up failure with -ENOSYS (as the IRQ's chip is not set).

Fixes: commit 443acc4f37f6 ("irqchip: GICv3: Convert to domain hierarchy")
Cc: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
---
 drivers/irqchip/irq-gic-v3.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c
index fc037d9..ea82342 100644
--- a/drivers/irqchip/irq-gic-v3.c
+++ b/drivers/irqchip/irq-gic-v3.c
@@ -835,8 +835,11 @@ static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
 	if (ret)
 		return ret;
 
-	for (i = 0; i < nr_irqs; i++)
-		gic_irq_domain_map(domain, virq + i, hwirq + i);
+	for (i = 0; i < nr_irqs; i++) {
+		ret = gic_irq_domain_map(domain, virq + i, hwirq + i);
+		if (ret)
+			return ret;
+	}
 
 	return 0;
 }
-- 
2.7.5

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#1680828 — [PATCH 3/3] irq: gic-v3: Honor forced affinity setting

Honor the 'force' flag for set_affinity, by selecting a CPU
from the given mask (which may not be reported "online" by
the cpu_online_mask). Some drivers, like ARM PMU, rely on it.

Cc: Marc Zyngier <marc.zyngier@arm.com>
Reported-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
---
 drivers/irqchip/irq-gic-v3.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c
index ea82342..883597f 100644
--- a/drivers/irqchip/irq-gic-v3.c
+++ b/drivers/irqchip/irq-gic-v3.c
@@ -642,11 +642,16 @@ static void gic_smp_init(void)
 static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
 			    bool force)
 {
-	unsigned int cpu = cpumask_any_and(mask_val, cpu_online_mask);
+	unsigned int cpu;
 	void __iomem *reg;
 	int enabled;
 	u64 val;
 
+	if (force)
+		cpu = cpumask_first(mask_val);
+	else
+		cpu = cpumask_any_and(mask_val, cpu_online_mask);
+
 	if (cpu >= nr_cpu_ids)
 		return -EINVAL;
 
-- 
2.7.5

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#1680841

On 04/07/17 10:56, Suzuki K Poulose wrote:
> This series contains some fixes for GIC/GIC-v3 to behave as expected
> by the generic management layer.
> 
> Suzuki K Poulose (3):
>   irqchip: gic-v3: Report failures in gic_irq_domain_alloc
>   irqchip: gic-v2: Report failures in gic_irq_domain_alloc
>   irq: gic-v3: Honor forced affinity setting
> 
>  drivers/irqchip/irq-gic-v3.c | 14 +++++++++++---
>  drivers/irqchip/irq-gic.c    |  7 +++++--
>  2 files changed, 16 insertions(+), 5 deletions(-)
> 

All 3 patches queued for post -rc1.

Thanks,

	M.
-- 
Jazz is not dead. It just smells funny...

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