Groups | Search | Server Info | Keyboard shortcuts | Login | Register [http] [https] [nntp] [nntps]
Groups > linux.kernel > #1680828
| From | Suzuki K Poulose <suzuki.poulose@arm.com> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | [PATCH 3/3] irq: gic-v3: Honor forced affinity setting |
| Date | 2017-07-04 12:00 +0200 |
| Message-ID | <tZsMG-6xj-29@gated-at.bofh.it> (permalink) |
| References | <tZsMF-6xj-1@gated-at.bofh.it> |
| Organization | linux.* mail to news gateway |
Honor the 'force' flag for set_affinity, by selecting a CPU
from the given mask (which may not be reported "online" by
the cpu_online_mask). Some drivers, like ARM PMU, rely on it.
Cc: Marc Zyngier <marc.zyngier@arm.com>
Reported-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
---
drivers/irqchip/irq-gic-v3.c | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c
index ea82342..883597f 100644
--- a/drivers/irqchip/irq-gic-v3.c
+++ b/drivers/irqchip/irq-gic-v3.c
@@ -642,11 +642,16 @@ static void gic_smp_init(void)
static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
bool force)
{
- unsigned int cpu = cpumask_any_and(mask_val, cpu_online_mask);
+ unsigned int cpu;
void __iomem *reg;
int enabled;
u64 val;
+ if (force)
+ cpu = cpumask_first(mask_val);
+ else
+ cpu = cpumask_any_and(mask_val, cpu_online_mask);
+
if (cpu >= nr_cpu_ids)
return -EINVAL;
--
2.7.5
Back to linux.kernel | Previous | Next — Previous in thread | Next in thread | Find similar | Unroll thread
[PATCH 0/3] irqchip: Miscellaneous fixes for GIC/GICv3 Suzuki K Poulose <suzuki.poulose@arm.com> - 2017-07-04 12:00 +0200 [PATCH 2/3] irqchip: gic-v2: Report failures in gic_irq_domain_alloc Suzuki K Poulose <suzuki.poulose@arm.com> - 2017-07-04 12:00 +0200 [PATCH 1/3] irqchip: gic-v3: Report failures in gic_irq_domain_alloc Suzuki K Poulose <suzuki.poulose@arm.com> - 2017-07-04 12:00 +0200 [PATCH 3/3] irq: gic-v3: Honor forced affinity setting Suzuki K Poulose <suzuki.poulose@arm.com> - 2017-07-04 12:00 +0200 Re: [PATCH 0/3] irqchip: Miscellaneous fixes for GIC/GICv3 Marc Zyngier <marc.zyngier@arm.com> - 2017-07-04 12:20 +0200
csiph-web