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[PATCH 0/2] Couple of fixes for pinctrl-armada-37xx

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  [PATCH 0/2] Couple of fixes for pinctrl-armada-37xx Gregory CLEMENT <gregory.clement@free-electrons.com> - 2017-06-23 14:40 +0200
    [PATCH 1/2] pinctrl: armada-37xx: Fix uart2 group selection register mask Gregory CLEMENT <gregory.clement@free-electrons.com> - 2017-06-23 14:40 +0200
      Re: [PATCH 1/2] pinctrl: armada-37xx: Fix uart2 group selection  register mask Linus Walleij <linus.walleij@linaro.org> - 2017-06-29 11:50 +0200

#1673513 — [PATCH 0/2] Couple of fixes for pinctrl-armada-37xx

Hi,

Ken Ma found few issues in the driver. I wrote the first fix is based
on his report and the second one was written for U-Boot but as they
use the same driver it can be applied on linux too.

thanks,

Gregory

Gregory CLEMENT (1):
  pinctrl: armada-37xx: Fix number of pin in sdio_sb

Ken Ma (1):
  pinctrl: armada-37xx: Fix uart2 group selection register mask

 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

-- 
2.11.0

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#1673514 — [PATCH 1/2] pinctrl: armada-37xx: Fix uart2 group selection register mask

From: Ken Ma <make@marvell.com>

If north bridge selection register bit1 is clear, pins [10:8] are for
SDIO0 Resetn, Wakeup, and PDN while if bit1 is set, pins [10:8]are for
GPIO; when bit1 is clear, pin 9 and pin 10 can be used for uart2 RTSn
and CTSn, so bit1 should be added to uart2 group and it must be set
for both "gpio" and "uart" functions of uart2 group.

Signed-off-by: Ken Ma <make@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
index 5c96f5558310..2fb1c67886fc 100644
--- a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
+++ b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
@@ -147,8 +147,9 @@ static struct armada_37xx_pin_group armada_37xx_nb_groups[] = {
 	PIN_GRP_GPIO("onewire", 4, 1, BIT(16), "onewire"),
 	PIN_GRP_GPIO("uart1", 25, 2, BIT(17), "uart"),
 	PIN_GRP_GPIO("spi_quad", 15, 2, BIT(18), "spi"),
-	PIN_GRP_EXTRA("uart2", 9, 2, BIT(13) | BIT(14) | BIT(19),
-		      BIT(13) | BIT(14), BIT(19), 18, 2, "gpio", "uart"),
+	PIN_GRP_EXTRA("uart2", 9, 2, BIT(1) | BIT(13) | BIT(14) | BIT(19),
+		      BIT(1) | BIT(13) | BIT(14), BIT(1) | BIT(19),
+		      18, 2, "gpio", "uart"),
 	PIN_GRP_GPIO("led0_od", 11, 1, BIT(20), "led"),
 	PIN_GRP_GPIO("led1_od", 12, 1, BIT(21), "led"),
 	PIN_GRP_GPIO("led2_od", 13, 1, BIT(22), "led"),
-- 
2.11.0

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#1677569 — Re: [PATCH 1/2] pinctrl: armada-37xx: Fix uart2 group selection register mask

On Fri, Jun 23, 2017 at 2:29 PM, Gregory CLEMENT
<gregory.clement@free-electrons.com> wrote:

> From: Ken Ma <make@marvell.com>
>
> If north bridge selection register bit1 is clear, pins [10:8] are for
> SDIO0 Resetn, Wakeup, and PDN while if bit1 is set, pins [10:8]are for
> GPIO; when bit1 is clear, pin 9 and pin 10 can be used for uart2 RTSn
> and CTSn, so bit1 should be added to uart2 group and it must be set
> for both "gpio" and "uart" functions of uart2 group.
>
> Signed-off-by: Ken Ma <make@marvell.com>
> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>

Patch applied.

Yours,
Linus Walleij

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