Groups | Search | Server Info | Keyboard shortcuts | Login | Register [http] [https] [nntp] [nntps]

Groups > linux.kernel > #1650689 > unrolled thread

[PATCH v11 0/6] FPGA Manager support for altera passive serial

Started byJoshua Clayton <stillcompiling@gmail.com>
First post2017-05-25 19:40 +0200
Last post2017-06-05 17:20 +0200
Articles 20 on this page of 21 — 5 participants

Back to article view | Back to linux.kernel

Contents

  [PATCH v11 0/6] FPGA Manager support for altera passive serial Joshua Clayton <stillcompiling@gmail.com> - 2017-05-25 19:40 +0200
    [PATCH v11 5/6] lib: add bitrev8x4() Joshua Clayton <stillcompiling@gmail.com> - 2017-05-25 19:40 +0200
    [PATCH v11 3/6] fpga manager: Add altera-ps-spi driver for Altera FPGAs Joshua Clayton <stillcompiling@gmail.com> - 2017-05-25 19:40 +0200
    [PATCH v11 4/6] ARM: dts: imx6q-evi: support altera-ps-spi Joshua Clayton <stillcompiling@gmail.com> - 2017-05-25 19:40 +0200
      Re: [PATCH v11 4/6] ARM: dts: imx6q-evi: support altera-ps-spi Andreas Färber <afaerber@suse.de> - 2017-06-02 18:40 +0200
        Re: [PATCH v11 4/6] ARM: dts: imx6q-evi: support altera-ps-spi stillcompiling@gmail.com - 2017-06-02 21:40 +0200
          Re: [PATCH v11 4/6] ARM: dts: imx6q-evi: support altera-ps-spi Andreas Färber <afaerber@suse.de> - 2017-06-02 22:00 +0200
            Re: [PATCH v11 4/6] ARM: dts: imx6q-evi: support altera-ps-spi stillcompiling@gmail.com - 2017-06-02 23:20 +0200
              Re: [PATCH v11 4/6] ARM: dts: imx6q-evi: support altera-ps-spi Alan Tull <atull@kernel.org> - 2017-06-05 17:20 +0200
    [PATCH v11 1/6] fpga: Add flag to indicate SPI bitstream is bit-reversed Joshua Clayton <stillcompiling@gmail.com> - 2017-05-25 19:40 +0200
    Re: [PATCH v11 0/6] FPGA Manager support for altera passive serial Anatolij Gustschin <agust@denx.de> - 2017-06-02 18:00 +0200
    [PATCH v12 1/6] fpga: Add flag to indicate SPI bitstream is bit-reversed Joshua Clayton <stillcompiling@gmail.com> - 2017-06-02 22:40 +0200
      [PATCH v12 5/6] lib: add bitrev8x4() Joshua Clayton <stillcompiling@gmail.com> - 2017-06-02 22:40 +0200
        Re: [PATCH v12 5/6] lib: add bitrev8x4() Alan Tull <atull@kernel.org> - 2017-06-05 17:20 +0200
      [PATCH v12 3/6] fpga manager: Add altera-ps-spi driver for Altera FPGAs Joshua Clayton <stillcompiling@gmail.com> - 2017-06-02 22:40 +0200
        Re: [PATCH v12 3/6] fpga manager: Add altera-ps-spi driver for Altera FPGAs Alan Tull <atull@kernel.org> - 2017-06-05 17:20 +0200
      [PATCH v12 2/6] doc: dt: document altera-passive-serial binding Joshua Clayton <stillcompiling@gmail.com> - 2017-06-02 22:40 +0200
        Re: [PATCH v12 2/6] doc: dt: document altera-passive-serial binding Alan Tull <atull@kernel.org> - 2017-06-05 17:20 +0200
      [PATCH v12 4/6] ARM: dts: imx6q-evi: support altera-ps-spi Joshua Clayton <stillcompiling@gmail.com> - 2017-06-02 22:40 +0200
        Re: [PATCH v12 4/6] ARM: dts: imx6q-evi: support altera-ps-spi Alan Tull <atull@kernel.org> - 2017-06-05 17:20 +0200
      Re: [PATCH v12 1/6] fpga: Add flag to indicate SPI bitstream is bit-reversed Alan Tull <atull@kernel.org> - 2017-06-05 17:20 +0200

Page 1 of 2  [1] 2  Next page →

#1650689 — [PATCH v11 0/6] FPGA Manager support for altera passive serial

FromJoshua Clayton <stillcompiling@gmail.com>
Date2017-05-25 19:40 +0200
Subject[PATCH v11 0/6] FPGA Manager support for altera passive serial
Message-ID<tL4TT-2Ht-3@gated-at.bofh.it>
FPGA Manager passive serial can now support Stratix, Cyclone and Arria
FPGAs.
Thanks to Bastian and Anatolij for helping to extend support beyond Cyclone

changes from v10

- Rebase on v4.12-rc2
- Remove an erroneous cyclone-ps-spi.o reference from drivers/fpga/Makefile
- Change FPGA_MGR_SPI_BITSTREAM_LSB_FIRST tp FPGA_MGR_BITSTREAM_LSB_FIRST
- Change CONF_DONE "low" to "inactive" in an error message
- Add a MODULE_DEVICE_TABLE for SPI
- Patches 1-4 can be merged without 5 and 6
- Patches 5, and 6 Add back in the bitrev8x4 speed up code newly with support
  for any size buffer.

Anatolij Gustschin (1):
  fpga: Add flag to indicate SPI bitstream is bit-reversed

Joshua Clayton (4):
  doc: dt: add altera-ps-spi binding document
  fpga manager: Add altera-ps-spi driver for Altera FPGAs
  ARM: dts: imx6q-evi: support altera-ps-spi
  lib: add bitrev8x4()
  fpga-manager: altera-ps-spi: use bitrev8x4

 .../bindings/fpga/altera-passive-serial.txt        |  29 ++
 arch/arm/boot/dts/imx6q-evi.dts                    |  16 ++
 drivers/fpga/Kconfig                               |   7 +
 drivers/fpga/Makefile                              |   1 +
 drivers/fpga/altera-ps-spi.c                       | 307 +++++++++++++++++++++
 include/linux/bitrev.h                             |  19 ++
 include/linux/fpga/fpga-mgr.h                      |   2 +
 7 files changed, 381 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/fpga/altera-passive-serial.txt
 create mode 100644 drivers/fpga/altera-ps-spi.c

-- 
2.11.0

[toc] | [next] | [standalone]

#1650690 — [PATCH v11 5/6] lib: add bitrev8x4()

FromJoshua Clayton <stillcompiling@gmail.com>
Date2017-05-25 19:40 +0200
Subject[PATCH v11 5/6] lib: add bitrev8x4()
Message-ID<tL4TT-2Ht-9@gated-at.bofh.it>
In reply to#1650689
Add a function to reverse bytes within a 32 bit word.
Operate on a u32 rather than individual bytes.

Signed-off-by: Joshua Clayton <stillcompiling@gmail.com>
---
 include/linux/bitrev.h | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/include/linux/bitrev.h b/include/linux/bitrev.h
index fb790b8449c1..b97be27e5a85 100644
--- a/include/linux/bitrev.h
+++ b/include/linux/bitrev.h
@@ -29,6 +29,8 @@ static inline u32 __bitrev32(u32 x)
 
 #endif /* CONFIG_HAVE_ARCH_BITREVERSE */
 
+#define __bitrev8x4(x)	(__bitrev32(swab32(x)))
+
 #define __constant_bitrev32(x)	\
 ({					\
 	u32 __x = x;			\
@@ -50,6 +52,15 @@ static inline u32 __bitrev32(u32 x)
 	__x;								\
 })
 
+#define __constant_bitrev8x4(x) \
+({			\
+	u32 __x = x;	\
+	__x = ((__x & (u32)0xF0F0F0F0UL) >> 4) | ((__x & (u32)0x0F0F0F0FUL) << 4);	\
+	__x = ((__x & (u32)0xCCCCCCCCUL) >> 2) | ((__x & (u32)0x33333333UL) << 2);	\
+	__x = ((__x & (u32)0xAAAAAAAAUL) >> 1) | ((__x & (u32)0x55555555UL) << 1);	\
+	__x;								\
+})
+
 #define __constant_bitrev8(x)	\
 ({					\
 	u8 __x = x;			\
@@ -75,6 +86,14 @@ static inline u32 __bitrev32(u32 x)
 	__bitrev16(__x);				\
  })
 
+#define bitrev8x4(x) \
+({			\
+	u32 __x = x;	\
+	__builtin_constant_p(__x) ?	\
+	__constant_bitrev8x4(__x) :			\
+	__bitrev8x4(__x);				\
+ })
+
 #define bitrev8(x) \
 ({			\
 	u8 __x = x;	\
-- 
2.11.0

[toc] | [prev] | [next] | [standalone]

#1650692 — [PATCH v11 3/6] fpga manager: Add altera-ps-spi driver for Altera FPGAs

FromJoshua Clayton <stillcompiling@gmail.com>
Date2017-05-25 19:40 +0200
Subject[PATCH v11 3/6] fpga manager: Add altera-ps-spi driver for Altera FPGAs
Message-ID<tL4TT-2Ht-13@gated-at.bofh.it>
In reply to#1650689
altera-ps-spi loads FPGA firmware over SPI, using the "passive serial"
interface on Altera Arria 10, Cyclone V or Stratix V FPGAs.

This is one of the simpler ways to set up an FPGA at runtime.
The signal interface is close to unidirectional SPI with lsb first.

Signed-off-by: Joshua Clayton <stillcompiling@gmail.com>
Signed-off-by: Anatolij Gustschin <agust@denx.de>
---
 drivers/fpga/Kconfig         |   7 +
 drivers/fpga/Makefile        |   1 +
 drivers/fpga/altera-ps-spi.c | 296 +++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 304 insertions(+)
 create mode 100644 drivers/fpga/altera-ps-spi.c

diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
index 161ba9dccede..00e4cae7b79e 100644
--- a/drivers/fpga/Kconfig
+++ b/drivers/fpga/Kconfig
@@ -26,6 +26,13 @@ config FPGA_MGR_ICE40_SPI
 	help
 	  FPGA manager driver support for Lattice iCE40 FPGAs over SPI.
 
+config FPGA_MGR_ALTERA_PS_SPI
+	tristate "Altera FPGA Passive Serial over SPI"
+	depends on SPI || COMPILE_TEST
+	help
+	  FPGA manager driver support for Altera Arria/Cyclone/Stratix
+	  using the passive serial interface over SPI.
+
 config FPGA_MGR_SOCFPGA
 	tristate "Altera SOCFPGA FPGA Manager"
 	depends on ARCH_SOCFPGA || COMPILE_TEST
diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
index 2a4f0218145c..e75d3570e26a 100644
--- a/drivers/fpga/Makefile
+++ b/drivers/fpga/Makefile
@@ -6,6 +6,7 @@
 obj-$(CONFIG_FPGA)			+= fpga-mgr.o
 
 # FPGA Manager Drivers
+obj-$(CONFIG_FPGA_MGR_ALTERA_PS_SPI)	+= altera-ps-spi.o
 obj-$(CONFIG_FPGA_MGR_ICE40_SPI)	+= ice40-spi.o
 obj-$(CONFIG_FPGA_MGR_SOCFPGA)		+= socfpga.o
 obj-$(CONFIG_FPGA_MGR_SOCFPGA_A10)	+= socfpga-a10.o
diff --git a/drivers/fpga/altera-ps-spi.c b/drivers/fpga/altera-ps-spi.c
new file mode 100644
index 000000000000..9e90f8086cd5
--- /dev/null
+++ b/drivers/fpga/altera-ps-spi.c
@@ -0,0 +1,297 @@
+/*
+ * Altera Passive Serial SPI Driver
+ *
+ *  Copyright (c) 2017 United Western Technologies, Corporation
+ *
+ *  Joshua Clayton <stillcompiling@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * Manage Altera FPGA firmware that is loaded over SPI using the passive
+ * serial configuration method.
+ * Firmware must be in binary "rbf" format.
+ * Works on Arria 10, Cyclone V and Stratix V. Should work on Cyclone series.
+ * May work on other Altera FPGAs.
+ */
+
+#include <linux/bitrev.h>
+#include <linux/delay.h>
+#include <linux/fpga/fpga-mgr.h>
+#include <linux/gpio/consumer.h>
+#include <linux/module.h>
+#include <linux/of_gpio.h>
+#include <linux/of_device.h>
+#include <linux/spi/spi.h>
+#include <linux/sizes.h>
+
+enum altera_ps_devtype {
+	CYCLONE5,
+	ARRIA10,
+};
+
+struct altera_ps_data {
+	enum altera_ps_devtype devtype;
+	int status_wait_min_us;
+	int status_wait_max_us;
+	int t_cfg_us;
+	int t_st2ck_us;
+};
+
+struct altera_ps_conf {
+	struct gpio_desc *config;
+	struct gpio_desc *confd;
+	struct gpio_desc *status;
+	struct spi_device *spi;
+	const struct altera_ps_data *data;
+	u32 info_flags;
+	char mgr_name[64];
+};
+
+/*          |   Arria 10  |   Cyclone5  |   Stratix5  |
+ * t_CF2ST0 |     [; 600] |     [; 600] |     [; 600] |ns
+ * t_CFG    |        [2;] |        [2;] |        [2;] |µs
+ * t_STATUS | [268; 3000] | [268; 1506] | [268; 1506] |µs
+ * t_CF2ST1 |    [; 3000] |    [; 1506] |    [; 1506] |µs
+ * t_CF2CK  |     [3010;] |     [1506;] |     [1506;] |µs
+ * t_ST2CK  |       [10;] |        [2;] |        [2;] |µs
+ * t_CD2UM  |  [175; 830] |  [175; 437] |  [175; 437] |µs
+ */
+static struct altera_ps_data c5_data = {
+	/* these values for Cyclone5 are compatible with Stratix5 */
+	.devtype = CYCLONE5,
+	.status_wait_min_us = 268,
+	.status_wait_max_us = 1506,
+	.t_cfg_us = 2,
+	.t_st2ck_us = 2,
+};
+
+static struct altera_ps_data a10_data = {
+	.devtype = ARRIA10,
+	.status_wait_min_us = 268,  /* min(t_STATUS) */
+	.status_wait_max_us = 3000, /* max(t_CF2ST1) */
+	.t_cfg_us = 2,    /* max { min(t_CFG), max(tCF2ST0) } */
+	.t_st2ck_us = 10, /* min(t_ST2CK) */
+};
+
+static const struct of_device_id of_ef_match[] = {
+	{ .compatible = "altr,fpga-passive-serial", .data = &c5_data },
+	{ .compatible = "altr,fpga-arria10-passive-serial", .data = &a10_data },
+	{}
+};
+MODULE_DEVICE_TABLE(of, of_ef_match);
+
+static enum fpga_mgr_states altera_ps_state(struct fpga_manager *mgr)
+{
+	struct altera_ps_conf *conf = mgr->priv;
+
+	if (gpiod_get_value_cansleep(conf->status))
+		return FPGA_MGR_STATE_RESET;
+
+	return FPGA_MGR_STATE_UNKNOWN;
+}
+
+static inline void altera_ps_delay(int delay_us)
+{
+	if (delay_us > 10)
+		usleep_range(delay_us, delay_us + 5);
+	else
+		udelay(delay_us);
+}
+
+static int altera_ps_write_init(struct fpga_manager *mgr,
+				struct fpga_image_info *info,
+				const char *buf, size_t count)
+{
+	struct altera_ps_conf *conf = mgr->priv;
+	int min, max, waits;
+	int i;
+
+	conf->info_flags = info->flags;
+
+	if (info->flags & FPGA_MGR_PARTIAL_RECONFIG) {
+		dev_err(&mgr->dev, "Partial reconfiguration not supported.\n");
+		return -EINVAL;
+	}
+
+	gpiod_set_value_cansleep(conf->config, 1);
+
+	/* wait min reset pulse time */
+	altera_ps_delay(conf->data->t_cfg_us);
+
+	if (!gpiod_get_value_cansleep(conf->status)) {
+		dev_err(&mgr->dev, "Status pin failed to show a reset\n");
+		return -EIO;
+	}
+
+	gpiod_set_value_cansleep(conf->config, 0);
+
+	min = conf->data->status_wait_min_us;
+	max = conf->data->status_wait_max_us;
+	waits = max / min;
+	if (max % min)
+		waits++;
+
+	/* wait for max { max(t_STATUS), max(t_CF2ST1) } */
+	for (i = 0; i < waits; i++) {
+		usleep_range(min, min + 10);
+		if (!gpiod_get_value_cansleep(conf->status)) {
+			/* wait for min(t_ST2CK)*/
+			altera_ps_delay(conf->data->t_st2ck_us);
+			return 0;
+		}
+	}
+
+	dev_err(&mgr->dev, "Status pin not ready.\n");
+	return -EIO;
+}
+
+static void rev_buf(char *buf, size_t len)
+{
+	const char *fw_end = (buf + len);
+
+	/* set buffer to lsb first */
+	while (buf < fw_end) {
+		*buf = bitrev8(*buf);
+		buf++;
+	}
+}
+
+static int altera_ps_write(struct fpga_manager *mgr, const char *buf,
+			   size_t count)
+{
+	struct altera_ps_conf *conf = mgr->priv;
+	const char *fw_data = buf;
+	const char *fw_data_end = fw_data + count;
+
+	while (fw_data < fw_data_end) {
+		int ret;
+		size_t stride = min_t(size_t, fw_data_end - fw_data, SZ_4K);
+
+		if (!(conf->info_flags & FPGA_MGR_BITSTREAM_LSB_FIRST))
+			rev_buf((char *)fw_data, stride);
+
+		ret = spi_write(conf->spi, fw_data, stride);
+		if (ret) {
+			dev_err(&mgr->dev, "spi error in firmware write: %d\n",
+				ret);
+			return ret;
+		}
+		fw_data += stride;
+	}
+
+	return 0;
+}
+
+static int altera_ps_write_complete(struct fpga_manager *mgr,
+				    struct fpga_image_info *info)
+{
+	struct altera_ps_conf *conf = mgr->priv;
+	const char dummy[] = {0};
+	int ret;
+
+	if (gpiod_get_value_cansleep(conf->status)) {
+		dev_err(&mgr->dev, "Error during configuration.\n");
+		return -EIO;
+	}
+
+	if (!IS_ERR(conf->confd)) {
+		if (!gpiod_get_raw_value_cansleep(conf->confd)) {
+			dev_err(&mgr->dev, "CONF_DONE is inactive!\n");
+			return -EIO;
+		}
+	}
+
+	/*
+	 * After CONF_DONE goes high, send two additional falling edges on DCLK
+	 * to begin initialization and enter user mode
+	 */
+	ret = spi_write(conf->spi, dummy, 1);
+	if (ret) {
+		dev_err(&mgr->dev, "spi error during end sequence: %d\n", ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+static const struct fpga_manager_ops altera_ps_ops = {
+	.state = altera_ps_state,
+	.write_init = altera_ps_write_init,
+	.write = altera_ps_write,
+	.write_complete = altera_ps_write_complete,
+};
+
+static int altera_ps_probe(struct spi_device *spi)
+{
+	struct altera_ps_conf *conf;
+	const struct of_device_id *of_id;
+
+	conf = devm_kzalloc(&spi->dev, sizeof(*conf), GFP_KERNEL);
+	if (!conf)
+		return -ENOMEM;
+
+	of_id = of_match_device(of_ef_match, &spi->dev);
+	if (!of_id)
+		return -ENODEV;
+
+	conf->data = of_id->data;
+	conf->spi = spi;
+	conf->config = devm_gpiod_get(&spi->dev, "nconfig", GPIOD_OUT_HIGH);
+	if (IS_ERR(conf->config)) {
+		dev_err(&spi->dev, "Failed to get config gpio: %ld\n",
+			PTR_ERR(conf->config));
+		return PTR_ERR(conf->config);
+	}
+
+	conf->status = devm_gpiod_get(&spi->dev, "nstat", GPIOD_IN);
+	if (IS_ERR(conf->status)) {
+		dev_err(&spi->dev, "Failed to get status gpio: %ld\n",
+			PTR_ERR(conf->status));
+		return PTR_ERR(conf->status);
+	}
+
+	conf->confd = devm_gpiod_get(&spi->dev, "confd", GPIOD_IN);
+	if (IS_ERR(conf->confd)) {
+		dev_warn(&spi->dev, "Not using confd gpio: %ld\n",
+			 PTR_ERR(conf->confd));
+	}
+
+	/* Register manager with unique name */
+	snprintf(conf->mgr_name, sizeof(conf->mgr_name), "%s %s",
+		 dev_driver_string(&spi->dev), dev_name(&spi->dev));
+
+	return fpga_mgr_register(&spi->dev, conf->mgr_name,
+				 &altera_ps_ops, conf);
+}
+
+static int altera_ps_remove(struct spi_device *spi)
+{
+	fpga_mgr_unregister(&spi->dev);
+
+	return 0;
+}
+
+static const struct spi_device_id altera_ps_spi_ids[] = {
+	{"cyclone-ps-spi", 0},
+	{}
+};
+MODULE_DEVICE_TABLE(spi, altera_ps_spi_ids);
+
+static struct spi_driver altera_ps_driver = {
+	.driver = {
+		.name = "altera-ps-spi",
+		.owner = THIS_MODULE,
+		.of_match_table = of_match_ptr(of_ef_match),
+	},
+	.id_table = altera_ps_spi_ids,
+	.probe = altera_ps_probe,
+	.remove = altera_ps_remove,
+};
+
+module_spi_driver(altera_ps_driver)
+
+MODULE_LICENSE("GPL v2");
+MODULE_AUTHOR("Joshua Clayton <stillcompiling@gmail.com>");
+MODULE_DESCRIPTION("Module to load Altera FPGA firmware over SPI");
-- 
2.11.0

[toc] | [prev] | [next] | [standalone]

#1650695 — [PATCH v11 4/6] ARM: dts: imx6q-evi: support altera-ps-spi

FromJoshua Clayton <stillcompiling@gmail.com>
Date2017-05-25 19:40 +0200
Subject[PATCH v11 4/6] ARM: dts: imx6q-evi: support altera-ps-spi
Message-ID<tL4TU-2Ht-17@gated-at.bofh.it>
In reply to#1650689
Add support for Altera V FPGA connected to an spi port
to the evi devicetree file

Signed-off-by: Joshua Clayton <stillcompiling@gmail.com>
---
 arch/arm/boot/dts/imx6q-evi.dts | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/arch/arm/boot/dts/imx6q-evi.dts b/arch/arm/boot/dts/imx6q-evi.dts
index 24fe093a66db..a0cbb2d84803 100644
--- a/arch/arm/boot/dts/imx6q-evi.dts
+++ b/arch/arm/boot/dts/imx6q-evi.dts
@@ -82,6 +82,15 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1cs>;
 	status = "okay";
+
+	fpga_spi: cyclonespi@0 {
+		compatible = "altr,fpga-passive-serial";
+		spi-max-frequency = <20000000>;
+		reg = <0>;
+		pinctrl-0 = <&pinctrl_fpgaspi>;
+		nconfig-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>;
+		nstat-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>;
+	};
 };
 
 &ecspi3 {
@@ -313,6 +322,13 @@
 		>;
 	};
 
+	pinctrl_fpgaspi: fpgaspigrp {
+		fsl,pins = <
+			MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x1b0b0
+			MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0
+		>;
+	};
+
 	pinctrl_gpminand: gpminandgrp {
 		fsl,pins = <
 			MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
-- 
2.11.0

[toc] | [prev] | [next] | [standalone]

#1656384 — Re: [PATCH v11 4/6] ARM: dts: imx6q-evi: support altera-ps-spi

FromAndreas Färber <afaerber@suse.de>
Date2017-06-02 18:40 +0200
SubjectRe: [PATCH v11 4/6] ARM: dts: imx6q-evi: support altera-ps-spi
Message-ID<tNXMd-3Dk-3@gated-at.bofh.it>
In reply to#1650695
Hi,

Am 25.05.2017 um 19:29 schrieb Joshua Clayton:
> Add support for Altera V FPGA connected to an spi port

Did you mean "Altera Cyclone V"?

> to the evi devicetree file
> 
> Signed-off-by: Joshua Clayton <stillcompiling@gmail.com>
> ---
>  arch/arm/boot/dts/imx6q-evi.dts | 16 ++++++++++++++++
>  1 file changed, 16 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/imx6q-evi.dts b/arch/arm/boot/dts/imx6q-evi.dts
> index 24fe093a66db..a0cbb2d84803 100644
> --- a/arch/arm/boot/dts/imx6q-evi.dts
> +++ b/arch/arm/boot/dts/imx6q-evi.dts
> @@ -82,6 +82,15 @@
>  	pinctrl-names = "default";
>  	pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1cs>;
>  	status = "okay";
> +
> +	fpga_spi: cyclonespi@0 {

"cyclonespi" does not strike me as the best node name.

I am guessing this is a sub-node of a SPI controller node, so no need to
repeat "spi", and Cyclone seems more or less implied by "altr,fpga-".

Note that the example in the bindings doc uses "evi-fpga-spi". Nodes
don't need to be (shouldn't be?) prefixed with the board. Note that
bindings examples tend to get copied a lot.

Any reason not to just use "fpga@0" in both places for simplicity?

> +		compatible = "altr,fpga-passive-serial";
> +		spi-max-frequency = <20000000>;
> +		reg = <0>;
> +		pinctrl-0 = <&pinctrl_fpgaspi>;
> +		nconfig-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>;
> +		nstat-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>;
> +	};
>  };
>  
>  &ecspi3 {
[snip]

Regards,
Andreas

-- 
SUSE Linux GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Felix Imendörffer, Jane Smithard, Graham Norton
HRB 21284 (AG Nürnberg)

[toc] | [prev] | [next] | [standalone]

#1656507 — Re: [PATCH v11 4/6] ARM: dts: imx6q-evi: support altera-ps-spi

Fromstillcompiling@gmail.com
Date2017-06-02 21:40 +0200
SubjectRe: [PATCH v11 4/6] ARM: dts: imx6q-evi: support altera-ps-spi
Message-ID<tO0Ar-5nM-55@gated-at.bofh.it>
In reply to#1656384
On Friday, June 2, 2017 6:30:12 PM PDT Andreas Färber wrote:
> Hi,
> 
> Am 25.05.2017 um 19:29 schrieb Joshua Clayton:
> > Add support for Altera V FPGA connected to an spi port
> 
> Did you mean "Altera Cyclone V"?
I meant to shorten it from Altera Cyclone V to Altera FPGA.
Didn't quite make it.  Will fix and resubmit today.
> 
> > to the evi devicetree file
> > 
> > Signed-off-by: Joshua Clayton <stillcompiling@gmail.com>
> > ---
> > 
> >  arch/arm/boot/dts/imx6q-evi.dts | 16 ++++++++++++++++
> >  1 file changed, 16 insertions(+)
> > 
> > diff --git a/arch/arm/boot/dts/imx6q-evi.dts
> > b/arch/arm/boot/dts/imx6q-evi.dts index 24fe093a66db..a0cbb2d84803 100644
> > --- a/arch/arm/boot/dts/imx6q-evi.dts
> > +++ b/arch/arm/boot/dts/imx6q-evi.dts
> > @@ -82,6 +82,15 @@
> > 
> >  	pinctrl-names = "default";
> >  	pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1cs>;
> >  	status = "okay";
> > 
> > +
> > +	fpga_spi: cyclonespi@0 {
> 
> "cyclonespi" does not strike me as the best node name.
> 
> I am guessing this is a sub-node of a SPI controller node, so no need to
> repeat "spi", and Cyclone seems more or less implied by "altr,fpga-".
True.
> 
> Note that the example in the bindings doc uses "evi-fpga-spi". Nodes
> don't need to be (shouldn't be?) prefixed with the board. Note that
> bindings examples tend to get copied a lot.
> 
> Any reason not to just use "fpga@0" in both places for simplicity?
Sure. fpga: fpga@0 is probably better.
I'll change it in both the dts and the binding doc.
> 
> > +		compatible = "altr,fpga-passive-serial";
> > +		spi-max-frequency = <20000000>;
> > +		reg = <0>;
> > +		pinctrl-0 = <&pinctrl_fpgaspi>;
> > +		nconfig-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>;
> > +		nstat-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>;
> > +	};
> > 
> >  };
> >  
> >  &ecspi3 {
> 
> [snip]
> 
> Regards,
> Andreas


-- 
~Joshua A Clayton

[toc] | [prev] | [next] | [standalone]

#1656509 — Re: [PATCH v11 4/6] ARM: dts: imx6q-evi: support altera-ps-spi

FromAndreas Färber <afaerber@suse.de>
Date2017-06-02 22:00 +0200
SubjectRe: [PATCH v11 4/6] ARM: dts: imx6q-evi: support altera-ps-spi
Message-ID<tO0TL-5uo-1@gated-at.bofh.it>
In reply to#1656507
Am 02.06.2017 um 21:39 schrieb stillcompiling@gmail.com:
> On Friday, June 2, 2017 6:30:12 PM PDT Andreas Färber wrote:
>> Am 25.05.2017 um 19:29 schrieb Joshua Clayton:
>>> diff --git a/arch/arm/boot/dts/imx6q-evi.dts
>>> b/arch/arm/boot/dts/imx6q-evi.dts index 24fe093a66db..a0cbb2d84803 100644
>>> --- a/arch/arm/boot/dts/imx6q-evi.dts
>>> +++ b/arch/arm/boot/dts/imx6q-evi.dts
>>> @@ -82,6 +82,15 @@
>>>
>>>  	pinctrl-names = "default";
>>>  	pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1cs>;
>>>  	status = "okay";
>>>
>>> +
>>> +	fpga_spi: cyclonespi@0 {
>>
>> "cyclonespi" does not strike me as the best node name.
>>
>> I am guessing this is a sub-node of a SPI controller node, so no need to
>> repeat "spi", and Cyclone seems more or less implied by "altr,fpga-".
> True.
>>
>> Note that the example in the bindings doc uses "evi-fpga-spi". Nodes
>> don't need to be (shouldn't be?) prefixed with the board. Note that
>> bindings examples tend to get copied a lot.
>>
>> Any reason not to just use "fpga@0" in both places for simplicity?
> Sure. fpga: fpga@0 is probably better.

Note that I was only commenting on the node name, the latter part.

I'm not aware of any rules for the label, so that could remain unchanged
or adopt cyclone_spi from the old node name or whatever is unique and
syntactically valid.

> I'll change it in both the dts and the binding doc.

Thanks. Maybe double-check if there's any conventions Xilinx/Lattice DTs
are using.

Cheers,
Andreas

-- 
SUSE Linux GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Felix Imendörffer, Jane Smithard, Graham Norton
HRB 21284 (AG Nürnberg)

[toc] | [prev] | [next] | [standalone]

#1656562 — Re: [PATCH v11 4/6] ARM: dts: imx6q-evi: support altera-ps-spi

Fromstillcompiling@gmail.com
Date2017-06-02 23:20 +0200
SubjectRe: [PATCH v11 4/6] ARM: dts: imx6q-evi: support altera-ps-spi
Message-ID<tO29c-6rm-5@gated-at.bofh.it>
In reply to#1656509
On Friday, June 2, 2017 9:54:22 PM PDT Andreas Färber wrote:
> Am 02.06.2017 um 21:39 schrieb stillcompiling@gmail.com:
> > On Friday, June 2, 2017 6:30:12 PM PDT Andreas Färber wrote:
> >> Am 25.05.2017 um 19:29 schrieb Joshua Clayton:
> >>> diff --git a/arch/arm/boot/dts/imx6q-evi.dts
> >>> b/arch/arm/boot/dts/imx6q-evi.dts index 24fe093a66db..a0cbb2d84803
> >>> 100644
> >>> --- a/arch/arm/boot/dts/imx6q-evi.dts
> >>> +++ b/arch/arm/boot/dts/imx6q-evi.dts
> >>> @@ -82,6 +82,15 @@
> >>> 
> >>>  	pinctrl-names = "default";
> >>>  	pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1cs>;
> >>>  	status = "okay";
> >>> 
> >>> +
> >>> +	fpga_spi: cyclonespi@0 {
> >> 
> >> "cyclonespi" does not strike me as the best node name.
> >> 
> >> I am guessing this is a sub-node of a SPI controller node, so no need to
> >> repeat "spi", and Cyclone seems more or less implied by "altr,fpga-".
> > 
> > True.
> > 
> >> Note that the example in the bindings doc uses "evi-fpga-spi". Nodes
> >> don't need to be (shouldn't be?) prefixed with the board. Note that
> >> bindings examples tend to get copied a lot.
> >> 
> >> Any reason not to just use "fpga@0" in both places for simplicity?
> > 
> > Sure. fpga: fpga@0 is probably better.
> 
> Note that I was only commenting on the node name, the latter part.
> 
> I'm not aware of any rules for the label, so that could remain unchanged
> or adopt cyclone_spi from the old node name or whatever is unique and
> syntactically valid.
Too late! Patches posted.
Oh, well, I'm not changing it back.
> 
> > I'll change it in both the dts and the binding doc.
> 
> Thanks. Maybe double-check if there's any conventions Xilinx/Lattice DTs
> are using.
> 
Of the conventions I found, fpga seemed the most "hardware descriptive"
for a plain FPGA.
The other one several binding doc examples are using is "fpga-mgr".

> Cheers,
> Andreas


-- 
~Joshua A Clayton

[toc] | [prev] | [next] | [standalone]

#1657661 — Re: [PATCH v11 4/6] ARM: dts: imx6q-evi: support altera-ps-spi

FromAlan Tull <atull@kernel.org>
Date2017-06-05 17:20 +0200
SubjectRe: [PATCH v11 4/6] ARM: dts: imx6q-evi: support altera-ps-spi
Message-ID<tP1Xr-4zX-15@gated-at.bofh.it>
In reply to#1656562
On Fri, Jun 2, 2017 at 4:10 PM,  <stillcompiling@gmail.com> wrote:
> On Friday, June 2, 2017 9:54:22 PM PDT Andreas Färber wrote:
>> Am 02.06.2017 um 21:39 schrieb stillcompiling@gmail.com:
>> > On Friday, June 2, 2017 6:30:12 PM PDT Andreas Färber wrote:
>> >> Am 25.05.2017 um 19:29 schrieb Joshua Clayton:
>> >>> diff --git a/arch/arm/boot/dts/imx6q-evi.dts
>> >>> b/arch/arm/boot/dts/imx6q-evi.dts index 24fe093a66db..a0cbb2d84803
>> >>> 100644
>> >>> --- a/arch/arm/boot/dts/imx6q-evi.dts
>> >>> +++ b/arch/arm/boot/dts/imx6q-evi.dts
>> >>> @@ -82,6 +82,15 @@
>> >>>
>> >>>   pinctrl-names = "default";
>> >>>   pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1cs>;
>> >>>   status = "okay";
>> >>>
>> >>> +
>> >>> + fpga_spi: cyclonespi@0 {
>> >>
>> >> "cyclonespi" does not strike me as the best node name.
>> >>
>> >> I am guessing this is a sub-node of a SPI controller node, so no need to
>> >> repeat "spi", and Cyclone seems more or less implied by "altr,fpga-".
>> >
>> > True.
>> >
>> >> Note that the example in the bindings doc uses "evi-fpga-spi". Nodes
>> >> don't need to be (shouldn't be?) prefixed with the board. Note that
>> >> bindings examples tend to get copied a lot.
>> >>
>> >> Any reason not to just use "fpga@0" in both places for simplicity?
>> >
>> > Sure. fpga: fpga@0 is probably better.
>>
>> Note that I was only commenting on the node name, the latter part.
>>
>> I'm not aware of any rules for the label, so that could remain unchanged
>> or adopt cyclone_spi from the old node name or whatever is unique and
>> syntactically valid.
> Too late! Patches posted.
> Oh, well, I'm not changing it back.

It's fine as it is in v12.

fpga_mgr: fpga-mgr@0 is what I've been using most recently.  It
distinguishes the one block that is used to program the fpga from the
fpga and hardware in the fpga.  But no need to respin this.

Alan

>>
>> > I'll change it in both the dts and the binding doc.
>>
>> Thanks. Maybe double-check if there's any conventions Xilinx/Lattice DTs
>> are using.
>>
> Of the conventions I found, fpga seemed the most "hardware descriptive"
> for a plain FPGA.
> The other one several binding doc examples are using is "fpga-mgr".
>
>> Cheers,
>> Andreas
>
>
> --
> ~Joshua A Clayton

[toc] | [prev] | [next] | [standalone]

#1650697 — [PATCH v11 1/6] fpga: Add flag to indicate SPI bitstream is bit-reversed

FromJoshua Clayton <stillcompiling@gmail.com>
Date2017-05-25 19:40 +0200
Subject[PATCH v11 1/6] fpga: Add flag to indicate SPI bitstream is bit-reversed
Message-ID<tL4TU-2Ht-19@gated-at.bofh.it>
In reply to#1650689
From: Anatolij Gustschin <agust@denx.de>

Add a flag that is passed to the write_init() callback,
indicating that the SPI bitstream starts with LSB first.
SPI controllers usually send data with MSB first. If an
FPGA expects bitstream data as LSB first, the data must
be reversed either by the SPI controller or by the driver.

Alternatively the bitstream could be prepared as bit-reversed
to avoid the bit-swapping while sending. This flag indicates
such bit-reversed SPI bitstream. The low-level driver will
deal with the flag and perform bit-reversing if needed.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Joshua Clayton <stillcompiling@gmail.com>
---
 include/linux/fpga/fpga-mgr.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/include/linux/fpga/fpga-mgr.h b/include/linux/fpga/fpga-mgr.h
index b4ac24c4411d..01c348ca38b7 100644
--- a/include/linux/fpga/fpga-mgr.h
+++ b/include/linux/fpga/fpga-mgr.h
@@ -67,10 +67,12 @@ enum fpga_mgr_states {
  * FPGA Manager flags
  * FPGA_MGR_PARTIAL_RECONFIG: do partial reconfiguration if supported
  * FPGA_MGR_EXTERNAL_CONFIG: FPGA has been configured prior to Linux booting
+ * FPGA_MGR_BITSTREAM_LSB_FIRST: SPI bitstream bit order is LSB first
  */
 #define FPGA_MGR_PARTIAL_RECONFIG	BIT(0)
 #define FPGA_MGR_EXTERNAL_CONFIG	BIT(1)
 #define FPGA_MGR_ENCRYPTED_BITSTREAM	BIT(2)
+#define FPGA_MGR_BITSTREAM_LSB_FIRST	BIT(3)
 
 /**
  * struct fpga_image_info - information specific to a FPGA image
-- 
2.11.0

[toc] | [prev] | [next] | [standalone]

#1656358

FromAnatolij Gustschin <agust@denx.de>
Date2017-06-02 18:00 +0200
Message-ID<tNX9w-37F-21@gated-at.bofh.it>
In reply to#1650689
Hi Alan,

On Thu, 25 May 2017 10:29:05 -0700
Joshua Clayton stillcompiling@gmail.com wrote:

>FPGA Manager passive serial can now support Stratix, Cyclone and Arria
>FPGAs.

can this series be queued for merging in v4.13 or are there any
issues with it?

Thanks,
Anatolij

[toc] | [prev] | [next] | [standalone]

#1656531 — [PATCH v12 1/6] fpga: Add flag to indicate SPI bitstream is bit-reversed

FromJoshua Clayton <stillcompiling@gmail.com>
Date2017-06-02 22:40 +0200
Subject[PATCH v12 1/6] fpga: Add flag to indicate SPI bitstream is bit-reversed
Message-ID<tO1wt-5YJ-5@gated-at.bofh.it>
In reply to#1650689
From: Anatolij Gustschin <agust@denx.de>

Add a flag that is passed to the write_init() callback,
indicating that the SPI bitstream starts with LSB first.
SPI controllers usually send data with MSB first. If an
FPGA expects bitstream data as LSB first, the data must
be reversed either by the SPI controller or by the driver.

Alternatively the bitstream could be prepared as bit-reversed
to avoid the bit-swapping while sending. This flag indicates
such bit-reversed SPI bitstream. The low-level driver will
deal with the flag and perform bit-reversing if needed.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Joshua Clayton <stillcompiling@gmail.com>
---

Changes from v11 (all in patch 4/4)
- Change "Altera V FPGA" to simply "Altera FPGA"
- Change the devicetree name to a generic "fpga: fpga@0"
  from "fpga_spi: cyclonespi@0"

 include/linux/fpga/fpga-mgr.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/include/linux/fpga/fpga-mgr.h b/include/linux/fpga/fpga-mgr.h
index b4ac24c4411d..01c348ca38b7 100644
--- a/include/linux/fpga/fpga-mgr.h
+++ b/include/linux/fpga/fpga-mgr.h
@@ -67,10 +67,12 @@ enum fpga_mgr_states {
  * FPGA Manager flags
  * FPGA_MGR_PARTIAL_RECONFIG: do partial reconfiguration if supported
  * FPGA_MGR_EXTERNAL_CONFIG: FPGA has been configured prior to Linux booting
+ * FPGA_MGR_BITSTREAM_LSB_FIRST: SPI bitstream bit order is LSB first
  */
 #define FPGA_MGR_PARTIAL_RECONFIG	BIT(0)
 #define FPGA_MGR_EXTERNAL_CONFIG	BIT(1)
 #define FPGA_MGR_ENCRYPTED_BITSTREAM	BIT(2)
+#define FPGA_MGR_BITSTREAM_LSB_FIRST	BIT(3)
 
 /**
  * struct fpga_image_info - information specific to a FPGA image
-- 
2.11.0

[toc] | [prev] | [next] | [standalone]

#1656533 — [PATCH v12 5/6] lib: add bitrev8x4()

FromJoshua Clayton <stillcompiling@gmail.com>
Date2017-06-02 22:40 +0200
Subject[PATCH v12 5/6] lib: add bitrev8x4()
Message-ID<tO1wu-5YJ-21@gated-at.bofh.it>
In reply to#1656531
Add a function to reverse bytes within a 32 bit word.
Operate on a u32 rather than individual bytes.

Signed-off-by: Joshua Clayton <stillcompiling@gmail.com>
---
 include/linux/bitrev.h | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/include/linux/bitrev.h b/include/linux/bitrev.h
index fb790b8449c1..b97be27e5a85 100644
--- a/include/linux/bitrev.h
+++ b/include/linux/bitrev.h
@@ -29,6 +29,8 @@ static inline u32 __bitrev32(u32 x)
 
 #endif /* CONFIG_HAVE_ARCH_BITREVERSE */
 
+#define __bitrev8x4(x)	(__bitrev32(swab32(x)))
+
 #define __constant_bitrev32(x)	\
 ({					\
 	u32 __x = x;			\
@@ -50,6 +52,15 @@ static inline u32 __bitrev32(u32 x)
 	__x;								\
 })
 
+#define __constant_bitrev8x4(x) \
+({			\
+	u32 __x = x;	\
+	__x = ((__x & (u32)0xF0F0F0F0UL) >> 4) | ((__x & (u32)0x0F0F0F0FUL) << 4);	\
+	__x = ((__x & (u32)0xCCCCCCCCUL) >> 2) | ((__x & (u32)0x33333333UL) << 2);	\
+	__x = ((__x & (u32)0xAAAAAAAAUL) >> 1) | ((__x & (u32)0x55555555UL) << 1);	\
+	__x;								\
+})
+
 #define __constant_bitrev8(x)	\
 ({					\
 	u8 __x = x;			\
@@ -75,6 +86,14 @@ static inline u32 __bitrev32(u32 x)
 	__bitrev16(__x);				\
  })
 
+#define bitrev8x4(x) \
+({			\
+	u32 __x = x;	\
+	__builtin_constant_p(__x) ?	\
+	__constant_bitrev8x4(__x) :			\
+	__bitrev8x4(__x);				\
+ })
+
 #define bitrev8(x) \
 ({			\
 	u8 __x = x;	\
-- 
2.11.0

[toc] | [prev] | [next] | [standalone]

#1657662 — Re: [PATCH v12 5/6] lib: add bitrev8x4()

FromAlan Tull <atull@kernel.org>
Date2017-06-05 17:20 +0200
SubjectRe: [PATCH v12 5/6] lib: add bitrev8x4()
Message-ID<tP1Xs-4zX-19@gated-at.bofh.it>
In reply to#1656533
On Fri, Jun 2, 2017 at 3:30 PM, Joshua Clayton <stillcompiling@gmail.com> wrote:
> Add a function to reverse bytes within a 32 bit word.
> Operate on a u32 rather than individual bytes.
>
> Signed-off-by: Joshua Clayton <stillcompiling@gmail.com>

Signed-off-by: Alan Tull <atull@kernel.org>

> ---
>  include/linux/bitrev.h | 19 +++++++++++++++++++
>  1 file changed, 19 insertions(+)
>
> diff --git a/include/linux/bitrev.h b/include/linux/bitrev.h
> index fb790b8449c1..b97be27e5a85 100644
> --- a/include/linux/bitrev.h
> +++ b/include/linux/bitrev.h
> @@ -29,6 +29,8 @@ static inline u32 __bitrev32(u32 x)
>
>  #endif /* CONFIG_HAVE_ARCH_BITREVERSE */
>
> +#define __bitrev8x4(x) (__bitrev32(swab32(x)))
> +
>  #define __constant_bitrev32(x) \
>  ({                                     \
>         u32 __x = x;                    \
> @@ -50,6 +52,15 @@ static inline u32 __bitrev32(u32 x)
>         __x;                                                            \
>  })
>
> +#define __constant_bitrev8x4(x) \
> +({                     \
> +       u32 __x = x;    \
> +       __x = ((__x & (u32)0xF0F0F0F0UL) >> 4) | ((__x & (u32)0x0F0F0F0FUL) << 4);      \
> +       __x = ((__x & (u32)0xCCCCCCCCUL) >> 2) | ((__x & (u32)0x33333333UL) << 2);      \
> +       __x = ((__x & (u32)0xAAAAAAAAUL) >> 1) | ((__x & (u32)0x55555555UL) << 1);      \
> +       __x;                                                            \
> +})
> +
>  #define __constant_bitrev8(x)  \
>  ({                                     \
>         u8 __x = x;                     \
> @@ -75,6 +86,14 @@ static inline u32 __bitrev32(u32 x)
>         __bitrev16(__x);                                \
>   })
>
> +#define bitrev8x4(x) \
> +({                     \
> +       u32 __x = x;    \
> +       __builtin_constant_p(__x) ?     \
> +       __constant_bitrev8x4(__x) :                     \
> +       __bitrev8x4(__x);                               \
> + })
> +
>  #define bitrev8(x) \
>  ({                     \
>         u8 __x = x;     \
> --
> 2.11.0
>

[toc] | [prev] | [next] | [standalone]

#1656534 — [PATCH v12 3/6] fpga manager: Add altera-ps-spi driver for Altera FPGAs

FromJoshua Clayton <stillcompiling@gmail.com>
Date2017-06-02 22:40 +0200
Subject[PATCH v12 3/6] fpga manager: Add altera-ps-spi driver for Altera FPGAs
Message-ID<tO1wu-5YJ-23@gated-at.bofh.it>
In reply to#1656531
altera-ps-spi loads FPGA firmware over SPI, using the "passive serial"
interface on Altera Arria 10, Cyclone V or Stratix V FPGAs.

This is one of the simpler ways to set up an FPGA at runtime.
The signal interface is close to unidirectional SPI with lsb first.

Signed-off-by: Joshua Clayton <stillcompiling@gmail.com>
Signed-off-by: Anatolij Gustschin <agust@denx.de>
---
 drivers/fpga/Kconfig         |   7 +
 drivers/fpga/Makefile        |   1 +
 drivers/fpga/altera-ps-spi.c | 297 +++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 305 insertions(+)
 create mode 100644 drivers/fpga/altera-ps-spi.c

diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
index 161ba9dccede..00e4cae7b79e 100644
--- a/drivers/fpga/Kconfig
+++ b/drivers/fpga/Kconfig
@@ -26,6 +26,13 @@ config FPGA_MGR_ICE40_SPI
 	help
 	  FPGA manager driver support for Lattice iCE40 FPGAs over SPI.
 
+config FPGA_MGR_ALTERA_PS_SPI
+	tristate "Altera FPGA Passive Serial over SPI"
+	depends on SPI || COMPILE_TEST
+	help
+	  FPGA manager driver support for Altera Arria/Cyclone/Stratix
+	  using the passive serial interface over SPI.
+
 config FPGA_MGR_SOCFPGA
 	tristate "Altera SOCFPGA FPGA Manager"
 	depends on ARCH_SOCFPGA || COMPILE_TEST
diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
index 2a4f0218145c..e75d3570e26a 100644
--- a/drivers/fpga/Makefile
+++ b/drivers/fpga/Makefile
@@ -6,6 +6,7 @@
 obj-$(CONFIG_FPGA)			+= fpga-mgr.o
 
 # FPGA Manager Drivers
+obj-$(CONFIG_FPGA_MGR_ALTERA_PS_SPI)	+= altera-ps-spi.o
 obj-$(CONFIG_FPGA_MGR_ICE40_SPI)	+= ice40-spi.o
 obj-$(CONFIG_FPGA_MGR_SOCFPGA)		+= socfpga.o
 obj-$(CONFIG_FPGA_MGR_SOCFPGA_A10)	+= socfpga-a10.o
diff --git a/drivers/fpga/altera-ps-spi.c b/drivers/fpga/altera-ps-spi.c
new file mode 100644
index 000000000000..0db8def668ed
--- /dev/null
+++ b/drivers/fpga/altera-ps-spi.c
@@ -0,0 +1,297 @@
+/*
+ * Altera Passive Serial SPI Driver
+ *
+ *  Copyright (c) 2017 United Western Technologies, Corporation
+ *
+ *  Joshua Clayton <stillcompiling@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * Manage Altera FPGA firmware that is loaded over SPI using the passive
+ * serial configuration method.
+ * Firmware must be in binary "rbf" format.
+ * Works on Arria 10, Cyclone V and Stratix V. Should work on Cyclone series.
+ * May work on other Altera FPGAs.
+ */
+
+#include <linux/bitrev.h>
+#include <linux/delay.h>
+#include <linux/fpga/fpga-mgr.h>
+#include <linux/gpio/consumer.h>
+#include <linux/module.h>
+#include <linux/of_gpio.h>
+#include <linux/of_device.h>
+#include <linux/spi/spi.h>
+#include <linux/sizes.h>
+
+enum altera_ps_devtype {
+	CYCLONE5,
+	ARRIA10,
+};
+
+struct altera_ps_data {
+	enum altera_ps_devtype devtype;
+	int status_wait_min_us;
+	int status_wait_max_us;
+	int t_cfg_us;
+	int t_st2ck_us;
+};
+
+struct altera_ps_conf {
+	struct gpio_desc *config;
+	struct gpio_desc *confd;
+	struct gpio_desc *status;
+	struct spi_device *spi;
+	const struct altera_ps_data *data;
+	u32 info_flags;
+	char mgr_name[64];
+};
+
+/*          |   Arria 10  |   Cyclone5  |   Stratix5  |
+ * t_CF2ST0 |     [; 600] |     [; 600] |     [; 600] |ns
+ * t_CFG    |        [2;] |        [2;] |        [2;] |µs
+ * t_STATUS | [268; 3000] | [268; 1506] | [268; 1506] |µs
+ * t_CF2ST1 |    [; 3000] |    [; 1506] |    [; 1506] |µs
+ * t_CF2CK  |     [3010;] |     [1506;] |     [1506;] |µs
+ * t_ST2CK  |       [10;] |        [2;] |        [2;] |µs
+ * t_CD2UM  |  [175; 830] |  [175; 437] |  [175; 437] |µs
+ */
+static struct altera_ps_data c5_data = {
+	/* these values for Cyclone5 are compatible with Stratix5 */
+	.devtype = CYCLONE5,
+	.status_wait_min_us = 268,
+	.status_wait_max_us = 1506,
+	.t_cfg_us = 2,
+	.t_st2ck_us = 2,
+};
+
+static struct altera_ps_data a10_data = {
+	.devtype = ARRIA10,
+	.status_wait_min_us = 268,  /* min(t_STATUS) */
+	.status_wait_max_us = 3000, /* max(t_CF2ST1) */
+	.t_cfg_us = 2,    /* max { min(t_CFG), max(tCF2ST0) } */
+	.t_st2ck_us = 10, /* min(t_ST2CK) */
+};
+
+static const struct of_device_id of_ef_match[] = {
+	{ .compatible = "altr,fpga-passive-serial", .data = &c5_data },
+	{ .compatible = "altr,fpga-arria10-passive-serial", .data = &a10_data },
+	{}
+};
+MODULE_DEVICE_TABLE(of, of_ef_match);
+
+static enum fpga_mgr_states altera_ps_state(struct fpga_manager *mgr)
+{
+	struct altera_ps_conf *conf = mgr->priv;
+
+	if (gpiod_get_value_cansleep(conf->status))
+		return FPGA_MGR_STATE_RESET;
+
+	return FPGA_MGR_STATE_UNKNOWN;
+}
+
+static inline void altera_ps_delay(int delay_us)
+{
+	if (delay_us > 10)
+		usleep_range(delay_us, delay_us + 5);
+	else
+		udelay(delay_us);
+}
+
+static int altera_ps_write_init(struct fpga_manager *mgr,
+				struct fpga_image_info *info,
+				const char *buf, size_t count)
+{
+	struct altera_ps_conf *conf = mgr->priv;
+	int min, max, waits;
+	int i;
+
+	conf->info_flags = info->flags;
+
+	if (info->flags & FPGA_MGR_PARTIAL_RECONFIG) {
+		dev_err(&mgr->dev, "Partial reconfiguration not supported.\n");
+		return -EINVAL;
+	}
+
+	gpiod_set_value_cansleep(conf->config, 1);
+
+	/* wait min reset pulse time */
+	altera_ps_delay(conf->data->t_cfg_us);
+
+	if (!gpiod_get_value_cansleep(conf->status)) {
+		dev_err(&mgr->dev, "Status pin failed to show a reset\n");
+		return -EIO;
+	}
+
+	gpiod_set_value_cansleep(conf->config, 0);
+
+	min = conf->data->status_wait_min_us;
+	max = conf->data->status_wait_max_us;
+	waits = max / min;
+	if (max % min)
+		waits++;
+
+	/* wait for max { max(t_STATUS), max(t_CF2ST1) } */
+	for (i = 0; i < waits; i++) {
+		usleep_range(min, min + 10);
+		if (!gpiod_get_value_cansleep(conf->status)) {
+			/* wait for min(t_ST2CK)*/
+			altera_ps_delay(conf->data->t_st2ck_us);
+			return 0;
+		}
+	}
+
+	dev_err(&mgr->dev, "Status pin not ready.\n");
+	return -EIO;
+}
+
+static void rev_buf(char *buf, size_t len)
+{
+	const char *fw_end = (buf + len);
+
+	/* set buffer to lsb first */
+	while (buf < fw_end) {
+		*buf = bitrev8(*buf);
+		buf++;
+	}
+}
+
+static int altera_ps_write(struct fpga_manager *mgr, const char *buf,
+			   size_t count)
+{
+	struct altera_ps_conf *conf = mgr->priv;
+	const char *fw_data = buf;
+	const char *fw_data_end = fw_data + count;
+
+	while (fw_data < fw_data_end) {
+		int ret;
+		size_t stride = min_t(size_t, fw_data_end - fw_data, SZ_4K);
+
+		if (!(conf->info_flags & FPGA_MGR_BITSTREAM_LSB_FIRST))
+			rev_buf((char *)fw_data, stride);
+
+		ret = spi_write(conf->spi, fw_data, stride);
+		if (ret) {
+			dev_err(&mgr->dev, "spi error in firmware write: %d\n",
+				ret);
+			return ret;
+		}
+		fw_data += stride;
+	}
+
+	return 0;
+}
+
+static int altera_ps_write_complete(struct fpga_manager *mgr,
+				    struct fpga_image_info *info)
+{
+	struct altera_ps_conf *conf = mgr->priv;
+	const char dummy[] = {0};
+	int ret;
+
+	if (gpiod_get_value_cansleep(conf->status)) {
+		dev_err(&mgr->dev, "Error during configuration.\n");
+		return -EIO;
+	}
+
+	if (!IS_ERR(conf->confd)) {
+		if (!gpiod_get_raw_value_cansleep(conf->confd)) {
+			dev_err(&mgr->dev, "CONF_DONE is inactive!\n");
+			return -EIO;
+		}
+	}
+
+	/*
+	 * After CONF_DONE goes high, send two additional falling edges on DCLK
+	 * to begin initialization and enter user mode
+	 */
+	ret = spi_write(conf->spi, dummy, 1);
+	if (ret) {
+		dev_err(&mgr->dev, "spi error during end sequence: %d\n", ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+static const struct fpga_manager_ops altera_ps_ops = {
+	.state = altera_ps_state,
+	.write_init = altera_ps_write_init,
+	.write = altera_ps_write,
+	.write_complete = altera_ps_write_complete,
+};
+
+static int altera_ps_probe(struct spi_device *spi)
+{
+	struct altera_ps_conf *conf;
+	const struct of_device_id *of_id;
+
+	conf = devm_kzalloc(&spi->dev, sizeof(*conf), GFP_KERNEL);
+	if (!conf)
+		return -ENOMEM;
+
+	of_id = of_match_device(of_ef_match, &spi->dev);
+	if (!of_id)
+		return -ENODEV;
+
+	conf->data = of_id->data;
+	conf->spi = spi;
+	conf->config = devm_gpiod_get(&spi->dev, "nconfig", GPIOD_OUT_HIGH);
+	if (IS_ERR(conf->config)) {
+		dev_err(&spi->dev, "Failed to get config gpio: %ld\n",
+			PTR_ERR(conf->config));
+		return PTR_ERR(conf->config);
+	}
+
+	conf->status = devm_gpiod_get(&spi->dev, "nstat", GPIOD_IN);
+	if (IS_ERR(conf->status)) {
+		dev_err(&spi->dev, "Failed to get status gpio: %ld\n",
+			PTR_ERR(conf->status));
+		return PTR_ERR(conf->status);
+	}
+
+	conf->confd = devm_gpiod_get(&spi->dev, "confd", GPIOD_IN);
+	if (IS_ERR(conf->confd)) {
+		dev_warn(&spi->dev, "Not using confd gpio: %ld\n",
+			 PTR_ERR(conf->confd));
+	}
+
+	/* Register manager with unique name */
+	snprintf(conf->mgr_name, sizeof(conf->mgr_name), "%s %s",
+		 dev_driver_string(&spi->dev), dev_name(&spi->dev));
+
+	return fpga_mgr_register(&spi->dev, conf->mgr_name,
+				 &altera_ps_ops, conf);
+}
+
+static int altera_ps_remove(struct spi_device *spi)
+{
+	fpga_mgr_unregister(&spi->dev);
+
+	return 0;
+}
+
+static const struct spi_device_id altera_ps_spi_ids[] = {
+	{"cyclone-ps-spi", 0},
+	{}
+};
+MODULE_DEVICE_TABLE(spi, altera_ps_spi_ids);
+
+static struct spi_driver altera_ps_driver = {
+	.driver = {
+		.name = "altera-ps-spi",
+		.owner = THIS_MODULE,
+		.of_match_table = of_match_ptr(of_ef_match),
+	},
+	.id_table = altera_ps_spi_ids,
+	.probe = altera_ps_probe,
+	.remove = altera_ps_remove,
+};
+
+module_spi_driver(altera_ps_driver)
+
+MODULE_LICENSE("GPL v2");
+MODULE_AUTHOR("Joshua Clayton <stillcompiling@gmail.com>");
+MODULE_DESCRIPTION("Module to load Altera FPGA firmware over SPI");
-- 
2.11.0

[toc] | [prev] | [next] | [standalone]

#1657656 — Re: [PATCH v12 3/6] fpga manager: Add altera-ps-spi driver for Altera FPGAs

FromAlan Tull <atull@kernel.org>
Date2017-06-05 17:20 +0200
SubjectRe: [PATCH v12 3/6] fpga manager: Add altera-ps-spi driver for Altera FPGAs
Message-ID<tP1Xr-4zX-7@gated-at.bofh.it>
In reply to#1656534
On Fri, Jun 2, 2017 at 3:30 PM, Joshua Clayton <stillcompiling@gmail.com> wrote:
> altera-ps-spi loads FPGA firmware over SPI, using the "passive serial"
> interface on Altera Arria 10, Cyclone V or Stratix V FPGAs.
>
> This is one of the simpler ways to set up an FPGA at runtime.
> The signal interface is close to unidirectional SPI with lsb first.
>
> Signed-off-by: Joshua Clayton <stillcompiling@gmail.com>
> Signed-off-by: Anatolij Gustschin <agust@denx.de>

Signed-off-by: Alan Tull <atull@kernel.org>

> ---
>  drivers/fpga/Kconfig         |   7 +
>  drivers/fpga/Makefile        |   1 +
>  drivers/fpga/altera-ps-spi.c | 297 +++++++++++++++++++++++++++++++++++++++++++
>  3 files changed, 305 insertions(+)
>  create mode 100644 drivers/fpga/altera-ps-spi.c
>
> diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
> index 161ba9dccede..00e4cae7b79e 100644
> --- a/drivers/fpga/Kconfig
> +++ b/drivers/fpga/Kconfig
> @@ -26,6 +26,13 @@ config FPGA_MGR_ICE40_SPI
>         help
>           FPGA manager driver support for Lattice iCE40 FPGAs over SPI.
>
> +config FPGA_MGR_ALTERA_PS_SPI
> +       tristate "Altera FPGA Passive Serial over SPI"
> +       depends on SPI || COMPILE_TEST
> +       help
> +         FPGA manager driver support for Altera Arria/Cyclone/Stratix
> +         using the passive serial interface over SPI.
> +
>  config FPGA_MGR_SOCFPGA
>         tristate "Altera SOCFPGA FPGA Manager"
>         depends on ARCH_SOCFPGA || COMPILE_TEST
> diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
> index 2a4f0218145c..e75d3570e26a 100644
> --- a/drivers/fpga/Makefile
> +++ b/drivers/fpga/Makefile
> @@ -6,6 +6,7 @@
>  obj-$(CONFIG_FPGA)                     += fpga-mgr.o
>
>  # FPGA Manager Drivers
> +obj-$(CONFIG_FPGA_MGR_ALTERA_PS_SPI)   += altera-ps-spi.o
>  obj-$(CONFIG_FPGA_MGR_ICE40_SPI)       += ice40-spi.o
>  obj-$(CONFIG_FPGA_MGR_SOCFPGA)         += socfpga.o
>  obj-$(CONFIG_FPGA_MGR_SOCFPGA_A10)     += socfpga-a10.o
> diff --git a/drivers/fpga/altera-ps-spi.c b/drivers/fpga/altera-ps-spi.c
> new file mode 100644
> index 000000000000..0db8def668ed
> --- /dev/null
> +++ b/drivers/fpga/altera-ps-spi.c
> @@ -0,0 +1,297 @@
> +/*
> + * Altera Passive Serial SPI Driver
> + *
> + *  Copyright (c) 2017 United Western Technologies, Corporation
> + *
> + *  Joshua Clayton <stillcompiling@gmail.com>
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2, as published by the Free Software Foundation.
> + *
> + * Manage Altera FPGA firmware that is loaded over SPI using the passive
> + * serial configuration method.
> + * Firmware must be in binary "rbf" format.
> + * Works on Arria 10, Cyclone V and Stratix V. Should work on Cyclone series.
> + * May work on other Altera FPGAs.
> + */
> +
> +#include <linux/bitrev.h>
> +#include <linux/delay.h>
> +#include <linux/fpga/fpga-mgr.h>
> +#include <linux/gpio/consumer.h>
> +#include <linux/module.h>
> +#include <linux/of_gpio.h>
> +#include <linux/of_device.h>
> +#include <linux/spi/spi.h>
> +#include <linux/sizes.h>
> +
> +enum altera_ps_devtype {
> +       CYCLONE5,
> +       ARRIA10,
> +};
> +
> +struct altera_ps_data {
> +       enum altera_ps_devtype devtype;
> +       int status_wait_min_us;
> +       int status_wait_max_us;
> +       int t_cfg_us;
> +       int t_st2ck_us;
> +};
> +
> +struct altera_ps_conf {
> +       struct gpio_desc *config;
> +       struct gpio_desc *confd;
> +       struct gpio_desc *status;
> +       struct spi_device *spi;
> +       const struct altera_ps_data *data;
> +       u32 info_flags;
> +       char mgr_name[64];
> +};
> +
> +/*          |   Arria 10  |   Cyclone5  |   Stratix5  |
> + * t_CF2ST0 |     [; 600] |     [; 600] |     [; 600] |ns
> + * t_CFG    |        [2;] |        [2;] |        [2;] |µs
> + * t_STATUS | [268; 3000] | [268; 1506] | [268; 1506] |µs
> + * t_CF2ST1 |    [; 3000] |    [; 1506] |    [; 1506] |µs
> + * t_CF2CK  |     [3010;] |     [1506;] |     [1506;] |µs
> + * t_ST2CK  |       [10;] |        [2;] |        [2;] |µs
> + * t_CD2UM  |  [175; 830] |  [175; 437] |  [175; 437] |µs
> + */
> +static struct altera_ps_data c5_data = {
> +       /* these values for Cyclone5 are compatible with Stratix5 */
> +       .devtype = CYCLONE5,
> +       .status_wait_min_us = 268,
> +       .status_wait_max_us = 1506,
> +       .t_cfg_us = 2,
> +       .t_st2ck_us = 2,
> +};
> +
> +static struct altera_ps_data a10_data = {
> +       .devtype = ARRIA10,
> +       .status_wait_min_us = 268,  /* min(t_STATUS) */
> +       .status_wait_max_us = 3000, /* max(t_CF2ST1) */
> +       .t_cfg_us = 2,    /* max { min(t_CFG), max(tCF2ST0) } */
> +       .t_st2ck_us = 10, /* min(t_ST2CK) */
> +};
> +
> +static const struct of_device_id of_ef_match[] = {
> +       { .compatible = "altr,fpga-passive-serial", .data = &c5_data },
> +       { .compatible = "altr,fpga-arria10-passive-serial", .data = &a10_data },
> +       {}
> +};
> +MODULE_DEVICE_TABLE(of, of_ef_match);
> +
> +static enum fpga_mgr_states altera_ps_state(struct fpga_manager *mgr)
> +{
> +       struct altera_ps_conf *conf = mgr->priv;
> +
> +       if (gpiod_get_value_cansleep(conf->status))
> +               return FPGA_MGR_STATE_RESET;
> +
> +       return FPGA_MGR_STATE_UNKNOWN;
> +}
> +
> +static inline void altera_ps_delay(int delay_us)
> +{
> +       if (delay_us > 10)
> +               usleep_range(delay_us, delay_us + 5);
> +       else
> +               udelay(delay_us);
> +}
> +
> +static int altera_ps_write_init(struct fpga_manager *mgr,
> +                               struct fpga_image_info *info,
> +                               const char *buf, size_t count)
> +{
> +       struct altera_ps_conf *conf = mgr->priv;
> +       int min, max, waits;
> +       int i;
> +
> +       conf->info_flags = info->flags;
> +
> +       if (info->flags & FPGA_MGR_PARTIAL_RECONFIG) {
> +               dev_err(&mgr->dev, "Partial reconfiguration not supported.\n");
> +               return -EINVAL;
> +       }
> +
> +       gpiod_set_value_cansleep(conf->config, 1);
> +
> +       /* wait min reset pulse time */
> +       altera_ps_delay(conf->data->t_cfg_us);
> +
> +       if (!gpiod_get_value_cansleep(conf->status)) {
> +               dev_err(&mgr->dev, "Status pin failed to show a reset\n");
> +               return -EIO;
> +       }
> +
> +       gpiod_set_value_cansleep(conf->config, 0);
> +
> +       min = conf->data->status_wait_min_us;
> +       max = conf->data->status_wait_max_us;
> +       waits = max / min;
> +       if (max % min)
> +               waits++;
> +
> +       /* wait for max { max(t_STATUS), max(t_CF2ST1) } */
> +       for (i = 0; i < waits; i++) {
> +               usleep_range(min, min + 10);
> +               if (!gpiod_get_value_cansleep(conf->status)) {
> +                       /* wait for min(t_ST2CK)*/
> +                       altera_ps_delay(conf->data->t_st2ck_us);
> +                       return 0;
> +               }
> +       }
> +
> +       dev_err(&mgr->dev, "Status pin not ready.\n");
> +       return -EIO;
> +}
> +
> +static void rev_buf(char *buf, size_t len)
> +{
> +       const char *fw_end = (buf + len);
> +
> +       /* set buffer to lsb first */
> +       while (buf < fw_end) {
> +               *buf = bitrev8(*buf);
> +               buf++;
> +       }
> +}
> +
> +static int altera_ps_write(struct fpga_manager *mgr, const char *buf,
> +                          size_t count)
> +{
> +       struct altera_ps_conf *conf = mgr->priv;
> +       const char *fw_data = buf;
> +       const char *fw_data_end = fw_data + count;
> +
> +       while (fw_data < fw_data_end) {
> +               int ret;
> +               size_t stride = min_t(size_t, fw_data_end - fw_data, SZ_4K);
> +
> +               if (!(conf->info_flags & FPGA_MGR_BITSTREAM_LSB_FIRST))
> +                       rev_buf((char *)fw_data, stride);
> +
> +               ret = spi_write(conf->spi, fw_data, stride);
> +               if (ret) {
> +                       dev_err(&mgr->dev, "spi error in firmware write: %d\n",
> +                               ret);
> +                       return ret;
> +               }
> +               fw_data += stride;
> +       }
> +
> +       return 0;
> +}
> +
> +static int altera_ps_write_complete(struct fpga_manager *mgr,
> +                                   struct fpga_image_info *info)
> +{
> +       struct altera_ps_conf *conf = mgr->priv;
> +       const char dummy[] = {0};
> +       int ret;
> +
> +       if (gpiod_get_value_cansleep(conf->status)) {
> +               dev_err(&mgr->dev, "Error during configuration.\n");
> +               return -EIO;
> +       }
> +
> +       if (!IS_ERR(conf->confd)) {
> +               if (!gpiod_get_raw_value_cansleep(conf->confd)) {
> +                       dev_err(&mgr->dev, "CONF_DONE is inactive!\n");
> +                       return -EIO;
> +               }
> +       }
> +
> +       /*
> +        * After CONF_DONE goes high, send two additional falling edges on DCLK
> +        * to begin initialization and enter user mode
> +        */
> +       ret = spi_write(conf->spi, dummy, 1);
> +       if (ret) {
> +               dev_err(&mgr->dev, "spi error during end sequence: %d\n", ret);
> +               return ret;
> +       }
> +
> +       return 0;
> +}
> +
> +static const struct fpga_manager_ops altera_ps_ops = {
> +       .state = altera_ps_state,
> +       .write_init = altera_ps_write_init,
> +       .write = altera_ps_write,
> +       .write_complete = altera_ps_write_complete,
> +};
> +
> +static int altera_ps_probe(struct spi_device *spi)
> +{
> +       struct altera_ps_conf *conf;
> +       const struct of_device_id *of_id;
> +
> +       conf = devm_kzalloc(&spi->dev, sizeof(*conf), GFP_KERNEL);
> +       if (!conf)
> +               return -ENOMEM;
> +
> +       of_id = of_match_device(of_ef_match, &spi->dev);
> +       if (!of_id)
> +               return -ENODEV;
> +
> +       conf->data = of_id->data;
> +       conf->spi = spi;
> +       conf->config = devm_gpiod_get(&spi->dev, "nconfig", GPIOD_OUT_HIGH);
> +       if (IS_ERR(conf->config)) {
> +               dev_err(&spi->dev, "Failed to get config gpio: %ld\n",
> +                       PTR_ERR(conf->config));
> +               return PTR_ERR(conf->config);
> +       }
> +
> +       conf->status = devm_gpiod_get(&spi->dev, "nstat", GPIOD_IN);
> +       if (IS_ERR(conf->status)) {
> +               dev_err(&spi->dev, "Failed to get status gpio: %ld\n",
> +                       PTR_ERR(conf->status));
> +               return PTR_ERR(conf->status);
> +       }
> +
> +       conf->confd = devm_gpiod_get(&spi->dev, "confd", GPIOD_IN);
> +       if (IS_ERR(conf->confd)) {
> +               dev_warn(&spi->dev, "Not using confd gpio: %ld\n",
> +                        PTR_ERR(conf->confd));
> +       }
> +
> +       /* Register manager with unique name */
> +       snprintf(conf->mgr_name, sizeof(conf->mgr_name), "%s %s",
> +                dev_driver_string(&spi->dev), dev_name(&spi->dev));
> +
> +       return fpga_mgr_register(&spi->dev, conf->mgr_name,
> +                                &altera_ps_ops, conf);
> +}
> +
> +static int altera_ps_remove(struct spi_device *spi)
> +{
> +       fpga_mgr_unregister(&spi->dev);
> +
> +       return 0;
> +}
> +
> +static const struct spi_device_id altera_ps_spi_ids[] = {
> +       {"cyclone-ps-spi", 0},
> +       {}
> +};
> +MODULE_DEVICE_TABLE(spi, altera_ps_spi_ids);
> +
> +static struct spi_driver altera_ps_driver = {
> +       .driver = {
> +               .name = "altera-ps-spi",
> +               .owner = THIS_MODULE,
> +               .of_match_table = of_match_ptr(of_ef_match),
> +       },
> +       .id_table = altera_ps_spi_ids,
> +       .probe = altera_ps_probe,
> +       .remove = altera_ps_remove,
> +};
> +
> +module_spi_driver(altera_ps_driver)
> +
> +MODULE_LICENSE("GPL v2");
> +MODULE_AUTHOR("Joshua Clayton <stillcompiling@gmail.com>");
> +MODULE_DESCRIPTION("Module to load Altera FPGA firmware over SPI");
> --
> 2.11.0
>

[toc] | [prev] | [next] | [standalone]

#1656535 — [PATCH v12 2/6] doc: dt: document altera-passive-serial binding

FromJoshua Clayton <stillcompiling@gmail.com>
Date2017-06-02 22:40 +0200
Subject[PATCH v12 2/6] doc: dt: document altera-passive-serial binding
Message-ID<tO1wu-5YJ-29@gated-at.bofh.it>
In reply to#1656531
Describe an altera-passive-serial devicetree entry, required features

Signed-off-by: Joshua Clayton <stillcompiling@gmail.com>
Acked-by: Rob Herring <robh@kernel.org>
---
 .../bindings/fpga/altera-passive-serial.txt        | 29 ++++++++++++++++++++++
 1 file changed, 29 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/fpga/altera-passive-serial.txt

diff --git a/Documentation/devicetree/bindings/fpga/altera-passive-serial.txt b/Documentation/devicetree/bindings/fpga/altera-passive-serial.txt
new file mode 100644
index 000000000000..48478bc07e29
--- /dev/null
+++ b/Documentation/devicetree/bindings/fpga/altera-passive-serial.txt
@@ -0,0 +1,29 @@
+Altera Passive Serial SPI FPGA Manager
+
+Altera FPGAs support a method of loading the bitstream over what is
+referred to as "passive serial".
+The passive serial link is not technically SPI, and might require extra
+circuits in order to play nicely with other SPI slaves on the same bus.
+
+See https://www.altera.com/literature/hb/cyc/cyc_c51013.pdf
+
+Required properties:
+- compatible: Must be one of the following:
+	"altr,fpga-passive-serial",
+	"altr,fpga-arria10-passive-serial"
+- reg: SPI chip select of the FPGA
+- nconfig-gpios: config pin (referred to as nCONFIG in the manual)
+- nstat-gpios: status pin (referred to as nSTATUS in the manual)
+
+Optional properties:
+- confd-gpios: confd pin (referred to as CONF_DONE in the manual)
+
+Example:
+	fpga: fpga@0 {
+		compatible = "altr,fpga-passive-serial";
+		spi-max-frequency = <20000000>;
+		reg = <0>;
+		nconfig-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>;
+		nstat-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>;
+		confd-gpios = <&gpio4 12 GPIO_ACTIVE_LOW>;
+	};
-- 
2.11.0

[toc] | [prev] | [next] | [standalone]

#1657657 — Re: [PATCH v12 2/6] doc: dt: document altera-passive-serial binding

FromAlan Tull <atull@kernel.org>
Date2017-06-05 17:20 +0200
SubjectRe: [PATCH v12 2/6] doc: dt: document altera-passive-serial binding
Message-ID<tP1Xr-4zX-11@gated-at.bofh.it>
In reply to#1656535
On Fri, Jun 2, 2017 at 3:30 PM, Joshua Clayton <stillcompiling@gmail.com> wrote:
> Describe an altera-passive-serial devicetree entry, required features
>
> Signed-off-by: Joshua Clayton <stillcompiling@gmail.com>
> Acked-by: Rob Herring <robh@kernel.org>

Signed-off-by: Alan Tull <atull@kernel.org>

> ---
>  .../bindings/fpga/altera-passive-serial.txt        | 29 ++++++++++++++++++++++
>  1 file changed, 29 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/fpga/altera-passive-serial.txt
>
> diff --git a/Documentation/devicetree/bindings/fpga/altera-passive-serial.txt b/Documentation/devicetree/bindings/fpga/altera-passive-serial.txt
> new file mode 100644
> index 000000000000..48478bc07e29
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/fpga/altera-passive-serial.txt
> @@ -0,0 +1,29 @@
> +Altera Passive Serial SPI FPGA Manager
> +
> +Altera FPGAs support a method of loading the bitstream over what is
> +referred to as "passive serial".
> +The passive serial link is not technically SPI, and might require extra
> +circuits in order to play nicely with other SPI slaves on the same bus.
> +
> +See https://www.altera.com/literature/hb/cyc/cyc_c51013.pdf
> +
> +Required properties:
> +- compatible: Must be one of the following:
> +       "altr,fpga-passive-serial",
> +       "altr,fpga-arria10-passive-serial"
> +- reg: SPI chip select of the FPGA
> +- nconfig-gpios: config pin (referred to as nCONFIG in the manual)
> +- nstat-gpios: status pin (referred to as nSTATUS in the manual)
> +
> +Optional properties:
> +- confd-gpios: confd pin (referred to as CONF_DONE in the manual)
> +
> +Example:
> +       fpga: fpga@0 {
> +               compatible = "altr,fpga-passive-serial";
> +               spi-max-frequency = <20000000>;
> +               reg = <0>;
> +               nconfig-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>;
> +               nstat-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>;
> +               confd-gpios = <&gpio4 12 GPIO_ACTIVE_LOW>;
> +       };
> --
> 2.11.0
>

[toc] | [prev] | [next] | [standalone]

#1656538 — [PATCH v12 4/6] ARM: dts: imx6q-evi: support altera-ps-spi

FromJoshua Clayton <stillcompiling@gmail.com>
Date2017-06-02 22:40 +0200
Subject[PATCH v12 4/6] ARM: dts: imx6q-evi: support altera-ps-spi
Message-ID<tO1wu-5YJ-35@gated-at.bofh.it>
In reply to#1656531
Add support for Altera FPGA connected to an spi port
to the evi devicetree file

Signed-off-by: Joshua Clayton <stillcompiling@gmail.com>
---
 arch/arm/boot/dts/imx6q-evi.dts | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/arch/arm/boot/dts/imx6q-evi.dts b/arch/arm/boot/dts/imx6q-evi.dts
index 24fe093a66db..59aebbc95671 100644
--- a/arch/arm/boot/dts/imx6q-evi.dts
+++ b/arch/arm/boot/dts/imx6q-evi.dts
@@ -82,6 +82,15 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1cs>;
 	status = "okay";
+
+	fpga: fpga@0 {
+		compatible = "altr,fpga-passive-serial";
+		spi-max-frequency = <20000000>;
+		reg = <0>;
+		pinctrl-0 = <&pinctrl_fpgaspi>;
+		nconfig-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>;
+		nstat-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>;
+	};
 };
 
 &ecspi3 {
@@ -313,6 +322,13 @@
 		>;
 	};
 
+	pinctrl_fpgaspi: fpgaspigrp {
+		fsl,pins = <
+			MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x1b0b0
+			MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0
+		>;
+	};
+
 	pinctrl_gpminand: gpminandgrp {
 		fsl,pins = <
 			MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
-- 
2.11.0

[toc] | [prev] | [next] | [standalone]

#1657653 — Re: [PATCH v12 4/6] ARM: dts: imx6q-evi: support altera-ps-spi

FromAlan Tull <atull@kernel.org>
Date2017-06-05 17:20 +0200
SubjectRe: [PATCH v12 4/6] ARM: dts: imx6q-evi: support altera-ps-spi
Message-ID<tP1Xr-4zX-1@gated-at.bofh.it>
In reply to#1656538
On Fri, Jun 2, 2017 at 3:30 PM, Joshua Clayton <stillcompiling@gmail.com> wrote:
> Add support for Altera FPGA connected to an spi port
> to the evi devicetree file
>
> Signed-off-by: Joshua Clayton <stillcompiling@gmail.com>

Signed-off-by: Alan Tull <atull@kernel.org>

> ---
>  arch/arm/boot/dts/imx6q-evi.dts | 16 ++++++++++++++++
>  1 file changed, 16 insertions(+)
>
> diff --git a/arch/arm/boot/dts/imx6q-evi.dts b/arch/arm/boot/dts/imx6q-evi.dts
> index 24fe093a66db..59aebbc95671 100644
> --- a/arch/arm/boot/dts/imx6q-evi.dts
> +++ b/arch/arm/boot/dts/imx6q-evi.dts
> @@ -82,6 +82,15 @@
>         pinctrl-names = "default";
>         pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1cs>;
>         status = "okay";
> +
> +       fpga: fpga@0 {
> +               compatible = "altr,fpga-passive-serial";
> +               spi-max-frequency = <20000000>;
> +               reg = <0>;
> +               pinctrl-0 = <&pinctrl_fpgaspi>;
> +               nconfig-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>;
> +               nstat-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>;
> +       };
>  };
>
>  &ecspi3 {
> @@ -313,6 +322,13 @@
>                 >;
>         };
>
> +       pinctrl_fpgaspi: fpgaspigrp {
> +               fsl,pins = <
> +                       MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x1b0b0
> +                       MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0
> +               >;
> +       };
> +
>         pinctrl_gpminand: gpminandgrp {
>                 fsl,pins = <
>                         MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
> --
> 2.11.0
>

[toc] | [prev] | [next] | [standalone]

Page 1 of 2  [1] 2  Next page →

Back to top | Article view | linux.kernel

csiph-web