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[PATCH 00/10] ARC plat-eznps upstream cont.

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  [PATCH 00/10] ARC plat-eznps upstream cont. Noam Camus <noamca@mellanox.com> - 2017-05-25 04:40 +0200
    [PATCH 02/10] ARC: send ipi to all cpus sharing task mm in case of page fault Noam Camus <noamca@mellanox.com> - 2017-05-25 04:40 +0200
      Re: [PATCH 02/10] ARC: send ipi to all cpus sharing task mm in case  of page fault Alexey Brodkin <Alexey.Brodkin@synopsys.com> - 2017-05-25 13:40 +0200
    [PATCH 08/10] ARC: [plat-eznps] spinlock aware for MTM Noam Camus <noamca@mellanox.com> - 2017-05-25 04:40 +0200
    [PATCH 06/10] ARC: [plat-eznps] Fix TLB Errata Noam Camus <noamca@mellanox.com> - 2017-05-25 04:40 +0200
      Re: [PATCH 06/10] ARC: [plat-eznps] Fix TLB Errata Alexey Brodkin <Alexey.Brodkin@synopsys.com> - 2017-05-25 13:10 +0200
        RE: [PATCH 06/10] ARC: [plat-eznps] Fix TLB Errata Noam Camus <noamca@mellanox.com> - 2017-05-25 13:20 +0200
        Re: [PATCH 06/10] ARC: [plat-eznps] Fix TLB Errata Vineet Gupta <Vineet.Gupta1@synopsys.com> - 2017-06-01 23:20 +0200
    [PATCH 10/10] ARC: [plat-eznps] Handle memory error as an exception Noam Camus <noamca@mellanox.com> - 2017-05-25 04:40 +0200
      Re: [PATCH 10/10] ARC: [plat-eznps] Handle memory error as an  exception Alexey Brodkin <Alexey.Brodkin@synopsys.com> - 2017-05-25 13:20 +0200
        RE: [PATCH 10/10] ARC: [plat-eznps] Handle memory error as an  exception Noam Camus <noamca@mellanox.com> - 2017-05-25 13:30 +0200
          Re: [PATCH 10/10] ARC: [plat-eznps] Handle memory error as an  exception Alexey Brodkin <Alexey.Brodkin@synopsys.com> - 2017-05-25 13:40 +0200
            RE: [PATCH 10/10] ARC: [plat-eznps] Handle memory error as an  exception Noam Camus <noamca@mellanox.com> - 2017-05-25 14:10 +0200
              Re: [PATCH 10/10] ARC: [plat-eznps] Handle memory error as an  exception Alexey Brodkin <Alexey.Brodkin@synopsys.com> - 2017-05-25 14:10 +0200
            Re: [PATCH 10/10] ARC: [plat-eznps] Handle memory error as an  exception Vineet Gupta <Vineet.Gupta1@synopsys.com> - 2017-06-07 00:00 +0200
    [PATCH 04/10] ARC: typos fix in kernel/entry-compact.S Noam Camus <noamca@mellanox.com> - 2017-05-25 04:40 +0200
      Re: [PATCH 04/10] ARC: typos fix in kernel/entry-compact.S Alexey Brodkin <Alexey.Brodkin@synopsys.com> - 2017-05-25 13:10 +0200

#1650129 — [PATCH 00/10] ARC plat-eznps upstream cont.

From: Noam Camus <noamca@mellanox.com>

With this patch set I continue the effort of upstreaming the
eznps platform for arch/arc.

it combine of patches for typos and other for HW erratas and some
for performance.
All selected as ones that may be obvious for merge with arc next.

This was based on for-curr branch as the mos updated one I found
at this point of time. 

Liav Rehana (2):
  ARC: typo fix in mm/fault.c
  ARC: typos fix in kernel/entry-compact.S

Noam Camus (8):
  ARC: set level of log per CPU during boot to be debug level
  ARC: send ipi to all cpus sharing task mm in case of page fault
  ARC: [plat-eznps] typo fix at Kconfig
  ARC: [plat-eznps] Fix TLB Errata
  ARC: [plat-eznps] disabled stall counter due to a HW bug
  ARC: [plat-eznps] spinlock aware for MTM
  ARC: [plat-eznps] use schd.wft instruction instead of sleep at idle
    task
  ARC: [plat-eznps] Handle memory error as an exception

 arch/arc/include/asm/cacheflush.h       |    3 +-
 arch/arc/include/asm/spinlock.h         |    6 +++++
 arch/arc/kernel/entry-compact.S         |   33 ++++++++++++++++++++----------
 arch/arc/kernel/process.c               |    7 ++++++
 arch/arc/kernel/setup.c                 |    6 ++--
 arch/arc/kernel/smp.c                   |    4 +-
 arch/arc/mm/cache.c                     |   14 ++++++++++--
 arch/arc/mm/fault.c                     |    2 +-
 arch/arc/mm/tlb.c                       |    4 +-
 arch/arc/mm/tlbex.S                     |   10 +++++++++
 arch/arc/plat-eznps/Kconfig             |   15 ++++++++++++-
 arch/arc/plat-eznps/include/plat/ctop.h |    1 +
 arch/arc/plat-eznps/mtm.c               |    2 -
 13 files changed, 80 insertions(+), 27 deletions(-)

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#1650130 — [PATCH 02/10] ARC: send ipi to all cpus sharing task mm in case of page fault

From: Noam Camus <noamca@mellanox.com>

This patch is derived due to performance issue.
The use case is a page fault that resides on more than the local cpu.
Trying to broadcast all CPUs results on performance degradation.
So we try to avoid this by sending only to the relevant CPUs.

Signed-off-by: Noam Camus <noamca@mellanox.com>
---
 arch/arc/include/asm/cacheflush.h |    3 ++-
 arch/arc/mm/cache.c               |   12 ++++++++++--
 arch/arc/mm/tlb.c                 |    2 +-
 3 files changed, 13 insertions(+), 4 deletions(-)

diff --git a/arch/arc/include/asm/cacheflush.h b/arch/arc/include/asm/cacheflush.h
index fc662f4..716dba1 100644
--- a/arch/arc/include/asm/cacheflush.h
+++ b/arch/arc/include/asm/cacheflush.h
@@ -33,7 +33,8 @@
 
 void flush_icache_range(unsigned long kstart, unsigned long kend);
 void __sync_icache_dcache(phys_addr_t paddr, unsigned long vaddr, int len);
-void __inv_icache_page(phys_addr_t paddr, unsigned long vaddr);
+void __inv_icache_page(struct vm_area_struct *vma,
+		       phys_addr_t paddr, unsigned long vaddr);
 void __flush_dcache_page(phys_addr_t paddr, unsigned long vaddr);
 
 #define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
diff --git a/arch/arc/mm/cache.c b/arch/arc/mm/cache.c
index 7d3e79b..e1ea57f 100644
--- a/arch/arc/mm/cache.c
+++ b/arch/arc/mm/cache.c
@@ -934,9 +934,17 @@ void __sync_icache_dcache(phys_addr_t paddr, unsigned long vaddr, int len)
 }
 
 /* wrapper to compile time eliminate alignment checks in flush loop */
-void __inv_icache_page(phys_addr_t paddr, unsigned long vaddr)
+void __inv_icache_page(struct vm_area_struct *vma,
+		       phys_addr_t paddr, unsigned long vaddr)
 {
-	__ic_line_inv_vaddr(paddr, vaddr, PAGE_SIZE);
+	struct ic_inv_args ic_inv = {
+		.paddr	= paddr,
+		.vaddr	= vaddr,
+		.sz	= PAGE_SIZE
+	};
+
+	on_each_cpu_mask(mm_cpumask(vma->vm_mm),
+			 __ic_line_inv_vaddr_helper, &ic_inv, 1);
 }
 
 /*
diff --git a/arch/arc/mm/tlb.c b/arch/arc/mm/tlb.c
index c5e70d8..a095608 100644
--- a/arch/arc/mm/tlb.c
+++ b/arch/arc/mm/tlb.c
@@ -626,7 +626,7 @@ void update_mmu_cache(struct vm_area_struct *vma, unsigned long vaddr_unaligned,
 
 			/* invalidate any existing icache lines (U-mapping) */
 			if (vma->vm_flags & VM_EXEC)
-				__inv_icache_page(paddr, vaddr);
+				__inv_icache_page(vma, paddr, vaddr);
 		}
 	}
 }
-- 
1.7.1

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#1650410 — Re: [PATCH 02/10] ARC: send ipi to all cpus sharing task mm in case of page fault

Hi Noam,

On Thu, 2017-05-25 at 05:34 +0300, Noam Camus wrote:
> From: Noam Camus <noamca@mellanox.com>
> 
> This patch is derived due to performance issue.
> The use case is a page fault that resides on more than the local cpu.
> Trying to broadcast all CPUs results on performance degradation.
> So we try to avoid this by sending only to the relevant CPUs.
> 
> Signed-off-by: Noam Camus <noamca@mellanox.com>

Really nice catch!

Reviewed-by: Alexey Brodkin <abrodkin@synopsys.com>

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#1650131 — [PATCH 08/10] ARC: [plat-eznps] spinlock aware for MTM

From: Noam Camus <noamca@mellanox.com>

This way when we execute "ex" during trying to hold lock we can switch to
other HW thread and utilize the core intead of just spinning on a lock.

We noticed about 10% improvement of execution time with hackbench test.

Signed-off-by: Noam Camus <noamca@mellanox.com>
---
 arch/arc/include/asm/spinlock.h |    6 ++++++
 1 files changed, 6 insertions(+), 0 deletions(-)

diff --git a/arch/arc/include/asm/spinlock.h b/arch/arc/include/asm/spinlock.h
index 233d5ff..0a54ce7 100644
--- a/arch/arc/include/asm/spinlock.h
+++ b/arch/arc/include/asm/spinlock.h
@@ -252,9 +252,15 @@ static inline void arch_spin_lock(arch_spinlock_t *lock)
 
 	__asm__ __volatile__(
 	"1:	ex  %0, [%1]		\n"
+#ifdef CONFIG_EZNPS_MTM_EXT
+	"	.word %3		\n"
+#endif
 	"	breq  %0, %2, 1b	\n"
 	: "+&r" (val)
 	: "r"(&(lock->slock)), "ir"(__ARCH_SPIN_LOCK_LOCKED__)
+#ifdef CONFIG_EZNPS_MTM_EXT
+	, "i"(CTOP_INST_SCHD_RW)
+#endif
 	: "memory");
 
 	/*
-- 
1.7.1

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#1650132 — [PATCH 06/10] ARC: [plat-eznps] Fix TLB Errata

From: Noam Camus <noamca@mellanox.com>

Due to a HW bug in NPS400 we get from time to time false TLB miss.
Workaround this by validating each miss.

Signed-off-by: Noam Camus <noamca@mellanox.com>
---
 arch/arc/mm/tlbex.S |   10 ++++++++++
 1 files changed, 10 insertions(+), 0 deletions(-)

diff --git a/arch/arc/mm/tlbex.S b/arch/arc/mm/tlbex.S
index b30e4e3..1d48723 100644
--- a/arch/arc/mm/tlbex.S
+++ b/arch/arc/mm/tlbex.S
@@ -274,6 +274,13 @@ ex_saved_reg1:
 .macro COMMIT_ENTRY_TO_MMU
 #if (CONFIG_ARC_MMU_VER < 4)
 
+#ifdef CONFIG_EZNPS_MTM_EXT
+	/* verify if entry for this vaddr+ASID already exists */
+	sr    TLBProbe, [ARC_REG_TLBCOMMAND]
+	lr    r0, [ARC_REG_TLBINDEX]
+	bbit0 r0, 31, 88f
+#endif
+
 	/* Get free TLB slot: Set = computed from vaddr, way = random */
 	sr  TLBGetIndex, [ARC_REG_TLBCOMMAND]
 
@@ -287,6 +294,9 @@ ex_saved_reg1:
 #else
 	sr TLBInsertEntry, [ARC_REG_TLBCOMMAND]
 #endif
+#ifdef CONFIG_EZNPS_MTM_EXT
+88:
+#endif
 .endm
 
 
-- 
1.7.1

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#1650369 — Re: [PATCH 06/10] ARC: [plat-eznps] Fix TLB Errata

Hi Noam,

On Thu, 2017-05-25 at 05:34 +0300, Noam Camus wrote:
> From: Noam Camus <noamca@mellanox.com>
> 
> Due to a HW bug in NPS400 we get from time to time false TLB miss.
> Workaround this by validating each miss.
> 
> Signed-off-by: Noam Camus <noamca@mellanox.com>
> ---
>  arch/arc/mm/tlbex.S |   10 ++++++++++
>  1 files changed, 10 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arc/mm/tlbex.S b/arch/arc/mm/tlbex.S
> index b30e4e3..1d48723 100644
> --- a/arch/arc/mm/tlbex.S
> +++ b/arch/arc/mm/tlbex.S
> @@ -274,6 +274,13 @@ ex_saved_reg1:
>  .macro COMMIT_ENTRY_TO_MMU
>  #if (CONFIG_ARC_MMU_VER < 4)
>  
> +#ifdef CONFIG_EZNPS_MTM_EXT
> +	/* verify if entry for this vaddr+ASID already exists */
> +	sr    TLBProbe, [ARC_REG_TLBCOMMAND]
> +	lr    r0, [ARC_REG_TLBINDEX]
> +	bbit0 r0, 31, 88f
> +#endif

That's funny. I think we used to have something like that in the past.


>  	/* Get free TLB slot: Set = computed from vaddr, way = random */
>  	sr  TLBGetIndex, [ARC_REG_TLBCOMMAND]
>  
> @@ -287,6 +294,9 @@ ex_saved_reg1:
>  #else
>  	sr TLBInsertEntry, [ARC_REG_TLBCOMMAND]
>  #endif
> +#ifdef CONFIG_EZNPS_MTM_EXT
> +88:
> +#endif

Not sure if label itself required wrapping in ifdefs. It just makes code bulkier
and harder to read.

-Alexey

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#1650375 — RE: [PATCH 06/10] ARC: [plat-eznps] Fix TLB Errata

>From: Alexey Brodkin [mailto:Alexey.Brodkin@synopsys.com] 
>Sent: Thursday, May 25, 2017 14:01 PM

...
>>  	/* Get free TLB slot: Set = computed from vaddr, way = random */
>>  	sr  TLBGetIndex, [ARC_REG_TLBCOMMAND]
>>  
>> @@ -287,6 +294,9 @@ ex_saved_reg1:
>>  #else
>>  	sr TLBInsertEntry, [ARC_REG_TLBCOMMAND]
>>  #endif
>> +#ifdef CONFIG_EZNPS_MTM_EXT
>> +88:
>> +#endif

>Not sure if label itself required wrapping in ifdefs. It just makes code bulkier and harder to read.
I will remove the wrapping.

-Noam

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#1655767 — Re: [PATCH 06/10] ARC: [plat-eznps] Fix TLB Errata

On 05/25/2017 04:00 AM, Alexey Brodkin wrote:
> Hi Noam,
> 
> On Thu, 2017-05-25 at 05:34 +0300, Noam Camus wrote:
>> From: Noam Camus <noamca@mellanox.com>
>>
>> Due to a HW bug in NPS400 we get from time to time false TLB miss.
>> Workaround this by validating each miss.
>>
>> Signed-off-by: Noam Camus <noamca@mellanox.com>
>> ---
>>   arch/arc/mm/tlbex.S |   10 ++++++++++
>>   1 files changed, 10 insertions(+), 0 deletions(-)
>>
>> diff --git a/arch/arc/mm/tlbex.S b/arch/arc/mm/tlbex.S
>> index b30e4e3..1d48723 100644
>> --- a/arch/arc/mm/tlbex.S
>> +++ b/arch/arc/mm/tlbex.S
>> @@ -274,6 +274,13 @@ ex_saved_reg1:
>>   .macro COMMIT_ENTRY_TO_MMU
>>   #if (CONFIG_ARC_MMU_VER < 4)
>>   
>> +#ifdef CONFIG_EZNPS_MTM_EXT
>> +	/* verify if entry for this vaddr+ASID already exists */
>> +	sr    TLBProbe, [ARC_REG_TLBCOMMAND]
>> +	lr    r0, [ARC_REG_TLBINDEX]
>> +	bbit0 r0, 31, 88f
>> +#endif
> 
> That's funny. I think we used to have something like that in the past.

Not here as this is fast path TLB refill handler and landign here implies entry 
was *not* present, unless there's a hardware bug, hence this patch.

Perhaps you are remembering the slow path TLB update code (tlb.c) which has always 
had this - as mm code can call update_mmu_cache() in various cases and in soem of 
those, the entry can be already present so for ARC700 cores we need to ensure that 
dups are not inserted !

>>   	/* Get free TLB slot: Set = computed from vaddr, way = random */
>>   	sr  TLBGetIndex, [ARC_REG_TLBCOMMAND]
>>   
>> @@ -287,6 +294,9 @@ ex_saved_reg1:
>>   #else
>>   	sr TLBInsertEntry, [ARC_REG_TLBCOMMAND]
>>   #endif
>> +#ifdef CONFIG_EZNPS_MTM_EXT
>> +88:
>> +#endif
> 
> Not sure if label itself required wrapping in ifdefs. It just makes code bulkier
> and harder to read.

I agree !

FWIW, after this patch, COMMIT_ENTRY_TO_MMU is totally unreadable - perhaps one of 
us needs to break it up into MMU ver specific implementations. But at any rate 
that can be after this patch.

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#1650133 — [PATCH 10/10] ARC: [plat-eznps] Handle memory error as an exception

From: Noam Camus <noamca@mellanox.com>

This commit adds the configuration CONFIG_EZNPS_MEM_ERROR.
If set, it will cause the kernel to handle user memory error
as a machine check exception.
It is required in order to align the NPS simulator memory
error handling to the one of the NPS400 real chip behavior.

Signed-off-by: Elad Kanfi <eladkan@mellanox.com>
Signed-off-by: Noam Camus <noamca@mellanox.com>
---
 arch/arc/kernel/entry-compact.S |   11 +++++++++++
 arch/arc/plat-eznps/Kconfig     |   11 +++++++++++
 2 files changed, 22 insertions(+), 0 deletions(-)

diff --git a/arch/arc/kernel/entry-compact.S b/arch/arc/kernel/entry-compact.S
index f285dbb..d152d36 100644
--- a/arch/arc/kernel/entry-compact.S
+++ b/arch/arc/kernel/entry-compact.S
@@ -203,6 +203,17 @@ END(handle_interrupt_level2)
 ; ---------------------------------------------
 ENTRY(mem_service)
 
+#if defined(CONFIG_EZNPS_MEM_ERROR)
+        ; SW workaround to cover up on a difference between
+        ; NPS real chip and simulator behaviors.
+        ; NPS real chip will activate a machine check exception
+        ; in case of memory error, while the simulator will
+        ; trigger a level 2 interrupt. Therefor this code section
+        ; should be reached only in simulation mode.
+        ; DEAD END: display Regs and HALT
+
+	j EV_MachineCheck
+#endif
 	INTERRUPT_PROLOGUE 2
 
 	mov r0, ilink2
diff --git a/arch/arc/plat-eznps/Kconfig b/arch/arc/plat-eznps/Kconfig
index feaa471..c5f946c 100644
--- a/arch/arc/plat-eznps/Kconfig
+++ b/arch/arc/plat-eznps/Kconfig
@@ -32,3 +32,14 @@ config EZNPS_MTM_EXT
 	  any of them seem like CPU from Linux point of view.
 	  All threads within same core share the execution unit of the
 	  core and HW scheduler round robin between them.
+
+config EZNPS_MEM_ERROR
+       bool "ARC-EZchip Memory error as an exception"
+       depends on ARC_PLAT_EZNPS
+       default n
+       help
+         On the real chip of the NPS, user memory errors are handled
+         as a machine check exception, whereas on simulator platform
+         for NPS, it handled as an interrupt level 2 (like legacy arc
+         real chip architecture).This configuration will cause the kernel
+         to handle memory error as a machine check exception.
-- 
1.7.1

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#1650376 — Re: [PATCH 10/10] ARC: [plat-eznps] Handle memory error as an exception

Hi Noam,

On Thu, 2017-05-25 at 05:34 +0300, Noam Camus wrote:
> From: Noam Camus <noamca@mellanox.com>
> 
> This commit adds the configuration CONFIG_EZNPS_MEM_ERROR.
> If set, it will cause the kernel to handle user memory error
> as a machine check exception.
> It is required in order to align the NPS simulator memory
> error handling to the one of the NPS400 real chip behavior.
> 
> Signed-off-by: Elad Kanfi <eladkan@mellanox.com>
> Signed-off-by: Noam Camus <noamca@mellanox.com>
> ---
>  arch/arc/kernel/entry-compact.S |   11 +++++++++++
>  arch/arc/plat-eznps/Kconfig     |   11 +++++++++++
>  2 files changed, 22 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arc/kernel/entry-compact.S b/arch/arc/kernel/entry-compact.S
> index f285dbb..d152d36 100644
> --- a/arch/arc/kernel/entry-compact.S
> +++ b/arch/arc/kernel/entry-compact.S
> @@ -203,6 +203,17 @@ END(handle_interrupt_level2)
>  ; ---------------------------------------------
>  ENTRY(mem_service)
>  
> +#if defined(CONFIG_EZNPS_MEM_ERROR)
> +        ; SW workaround to cover up on a difference between
> +        ; NPS real chip and simulator behaviors.
> +        ; NPS real chip will activate a machine check exception
> +        ; in case of memory error, while the simulator will
> +        ; trigger a level 2 interrupt. Therefor this code section
> +        ; should be reached only in simulation mode.
> +        ; DEAD END: display Regs and HALT

I'm not really buying that.

Why don't you just make simulator behaving exactly as your real chip?

Adding those stubs for some corner-cases here and there complicate code,
affect maintainability etc.

-Alexey

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#1650379 — RE: [PATCH 10/10] ARC: [plat-eznps] Handle memory error as an exception

> From: Alexey Brodkin [mailto:Alexey.Brodkin@synopsys.com] 
> Sent: Thursday, May 25, 2017 14:15 PM

>> 
>> diff --git a/arch/arc/kernel/entry-compact.S 
>> b/arch/arc/kernel/entry-compact.S index f285dbb..d152d36 100644
>> --- a/arch/arc/kernel/entry-compact.S
>> +++ b/arch/arc/kernel/entry-compact.S
>> @@ -203,6 +203,17 @@ END(handle_interrupt_level2)
>>  ; ---------------------------------------------
>>  ENTRY(mem_service)
>>  
>> +#if defined(CONFIG_EZNPS_MEM_ERROR)
>> +        ; SW workaround to cover up on a difference between
>> +        ; NPS real chip and simulator behaviors.
>> +        ; NPS real chip will activate a machine check exception
>> +        ; in case of memory error, while the simulator will
>> +        ; trigger a level 2 interrupt. Therefor this code section
>> +        ; should be reached only in simulation mode.
>> +        ; DEAD END: display Regs and HALT

>I'm not really buying that.

>Why don't you just make simulator behaving exactly as your real chip?
I can't change simulator core behavior. nSIM is a Synopsys proprietary code.

>Adding those stubs for some corner-cases here and there complicate code, affect maintainability etc.
I agree, any suggestions to still have this but with reduced cost?

-Noam

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#1650403 — Re: [PATCH 10/10] ARC: [plat-eznps] Handle memory error as an exception

Hi Noam,

On Thu, 2017-05-25 at 11:26 +0000, Noam Camus wrote:
> > 
> > From: Alexey Brodkin [mailto:Alexey.Brodkin@synopsys.com] 
> > Sent: Thursday, May 25, 2017 14:15 PM
> 
> > 
> > > 
> > > 
> > > diff --git a/arch/arc/kernel/entry-compact.S 
> > > b/arch/arc/kernel/entry-compact.S index f285dbb..d152d36 100644
> > > --- a/arch/arc/kernel/entry-compact.S
> > > +++ b/arch/arc/kernel/entry-compact.S
> > > @@ -203,6 +203,17 @@ END(handle_interrupt_level2)
> > >  ; ---------------------------------------------
> > >  ENTRY(mem_service)
> > >  
> > > +#if defined(CONFIG_EZNPS_MEM_ERROR)
> > > +        ; SW workaround to cover up on a difference between
> > > +        ; NPS real chip and simulator behaviors.
> > > +        ; NPS real chip will activate a machine check exception
> > > +        ; in case of memory error, while the simulator will
> > > +        ; trigger a level 2 interrupt. Therefor this code section
> > > +        ; should be reached only in simulation mode.
> > > +        ; DEAD END: display Regs and HALT
> 
> > 
> > I'm not really buying that.
> 
> > 
> > Why don't you just make simulator behaving exactly as your real chip?
> I can't change simulator core behavior. nSIM is a Synopsys proprietary code.

Well probably it worth discussing with nSIM team if they may have any suggestions
on how to align nSIM behavior with your real HW?

-Alexey

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#1650431 — RE: [PATCH 10/10] ARC: [plat-eznps] Handle memory error as an exception

>From: Alexey Brodkin [mailto:Alexey.Brodkin@synopsys.com] 
>Sent: Thursday, May 25, 2017 14:31 PM
...
>> > Why don't you just make simulator behaving exactly as your real chip?
>> I can't change simulator core behavior. nSIM is a Synopsys proprietary code.

>Well probably it worth discussing with nSIM team if they may have any suggestions on how to align nSIM behavior with your real HW?
We already talked with them, nothing we can do at this point.
What about turning mem_service into weak symbol and have my own platform copy (just like we do with res_service)?

-Noam 

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#1650435 — Re: [PATCH 10/10] ARC: [plat-eznps] Handle memory error as an exception

Hi Noam,

On Thu, 2017-05-25 at 12:03 +0000, Noam Camus wrote:
> > 
> > From: Alexey Brodkin [mailto:Alexey.Brodkin@synopsys.com] 
> > Sent: Thursday, May 25, 2017 14:31 PM
> ...
> > 
> > > 
> > > > 
> > > > Why don't you just make simulator behaving exactly as your real chip?
> > > I can't change simulator core behavior. nSIM is a Synopsys proprietary code.
> 
> > 
> > Well probably it worth discussing with nSIM team if they may have any suggestions on how to align nSIM behavior with your real HW?
> We already talked with them, nothing we can do at this point.
> What about turning mem_service into weak symbol and have my own platform copy (just like we do with res_service)?

That looks nicer to me.
Let's wait for Vineet's opinion on that.

-Alexey

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#1659246 — Re: [PATCH 10/10] ARC: [plat-eznps] Handle memory error as an exception

On 05/25/2017 04:30 AM, Alexey Brodkin wrote:
> Hi Noam,
> 
> On Thu, 2017-05-25 at 11:26 +0000, Noam Camus wrote:
>>> From: Alexey Brodkin [mailto:Alexey.Brodkin@synopsys.com]
>>> Sent: Thursday, May 25, 2017 14:15 PM
>>>>
>>>> diff --git a/arch/arc/kernel/entry-compact.S
>>>> b/arch/arc/kernel/entry-compact.S index f285dbb..d152d36 100644
>>>> --- a/arch/arc/kernel/entry-compact.S
>>>> +++ b/arch/arc/kernel/entry-compact.S
>>>> @@ -203,6 +203,17 @@ END(handle_interrupt_level2)
>>>>   ; ---------------------------------------------
>>>>   ENTRY(mem_service)
>>>>   
>>>> +#if defined(CONFIG_EZNPS_MEM_ERROR)
>>>> +        ; SW workaround to cover up on a difference between
>>>> +        ; NPS real chip and simulator behaviors.
>>>> +        ; NPS real chip will activate a machine check exception
>>>> +        ; in case of memory error, while the simulator will
>>>> +        ; trigger a level 2 interrupt. Therefor this code section
>>>> +        ; should be reached only in simulation mode.
>>>> +        ; DEAD END: display Regs and HALT
>>> I'm not really buying that.
>>> Why don't you just make simulator behaving exactly as your real chip?
>> I can't change simulator core behavior. nSIM is a Synopsys proprietary code.
> Well probably it worth discussing with nSIM team if they may have any suggestions
> on how to align nSIM behavior with your real HW?

For the record we can't change nSIM since the NPS behavioral is not aligned with 
stock ARC700.

stock ARC700 triggers an L2 interrupt for user space bus errors - weird but that 
is what it is and what kernel currently supports (as verified by IPPK folks when 
doing DDR controller testing from user space).

NPS triggers does machine check which is not correct hence this workaround !

-Vineet

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#1650134 — [PATCH 04/10] ARC: typos fix in kernel/entry-compact.S

From: Liav Rehana <liavr@mellanox.com>

Signed-off-by: Liav Rehana <liavr@mellanox.com>
Signed-off-by: Noam Camus <noamca@mellanox.com>
---
 arch/arc/kernel/entry-compact.S |   22 +++++++++++-----------
 1 files changed, 11 insertions(+), 11 deletions(-)

diff --git a/arch/arc/kernel/entry-compact.S b/arch/arc/kernel/entry-compact.S
index 9211707..f285dbb 100644
--- a/arch/arc/kernel/entry-compact.S
+++ b/arch/arc/kernel/entry-compact.S
@@ -25,12 +25,12 @@
  *
  * vineetg: Nov 2009 (Everything needed for TIF_RESTORE_SIGMASK)
  *  -do_signal()invoked upon TIF_RESTORE_SIGMASK as well
- *  -Wrappers for sys_{,rt_}sigsuspend() nolonger needed as they don't
+ *  -Wrappers for sys_{,rt_}sigsuspend() no longer needed as they don't
  *   need ptregs anymore
  *
  * Vineetg: Oct 2009
  *  -In a rare scenario, Process gets a Priv-V exception and gets scheduled
- *   out. Since we don't do FAKE RTIE for Priv-V, CPU excpetion state remains
+ *   out. Since we don't do FAKE RTIE for Priv-V, CPU exception state remains
  *   active (AE bit enabled).  This causes a double fault for a subseq valid
  *   exception. Thus FAKE RTIE needed in low level Priv-Violation handler.
  *   Instr Error could also cause similar scenario, so same there as well.
@@ -59,7 +59,7 @@
  */
 
 #include <linux/errno.h>
-#include <linux/linkage.h>	/* {EXTRY,EXIT} */
+#include <linux/linkage.h>	/* {ENTRY,EXIT} */
 #include <asm/entry.h>
 #include <asm/irqflags.h>
 
@@ -80,8 +80,8 @@
 	.align 4
 
 /* Each entry in the vector table must occupy 2 words. Since it is a jump
- * across sections (.vector to .text) we are gauranteed that 'j somewhere'
- * will use the 'j limm' form of the intrsuction as long as somewhere is in
+ * across sections (.vector to .text) we are guaranteed that 'j somewhere'
+ * will use the 'j limm' form of the instruction as long as somewhere is in
  * a section other than .vector.
  */
 
@@ -105,13 +105,13 @@ VECTOR   handle_interrupt_level1 ; Other devices
 
 ; ******************** Exceptions **********************
 VECTOR   EV_MachineCheck         ; 0x100, Fatal Machine check   (0x20)
-VECTOR   EV_TLBMissI             ; 0x108, Intruction TLB miss   (0x21)
+VECTOR   EV_TLBMissI             ; 0x108, Instruction TLB miss  (0x21)
 VECTOR   EV_TLBMissD             ; 0x110, Data TLB miss         (0x22)
 VECTOR   EV_TLBProtV             ; 0x118, Protection Violation  (0x23)
 				 ;         or Misaligned Access
 VECTOR   EV_PrivilegeV           ; 0x120, Privilege Violation   (0x24)
 VECTOR   EV_Trap                 ; 0x128, Trap exception        (0x25)
-VECTOR   EV_Extension            ; 0x130, Extn Intruction Excp  (0x26)
+VECTOR   EV_Extension            ; 0x130, Extn Instruction Excp (0x26)
 
 .rept   24
 VECTOR   reserved                ; Reserved Exceptions
@@ -199,7 +199,7 @@ END(handle_interrupt_level2)
 
 ; ---------------------------------------------
 ; User Mode Memory Bus Error Interrupt Handler
-; (Kernel mode memory errors handled via seperate exception vectors)
+; (Kernel mode memory errors handled via separate exception vectors)
 ; ---------------------------------------------
 ENTRY(mem_service)
 
@@ -273,7 +273,7 @@ ENTRY(EV_TLBProtV)
 	;------ (5) Type of Protection Violation? ----------
 	;
 	; ProtV Hardware Exception is triggered for Access Faults of 2 types
-	;   -Access Violaton	: 00_23_(00|01|02|03)_00
+	;   -Access Violation	: 00_23_(00|01|02|03)_00
 	;			         x  r  w  r+w
 	;   -Unaligned Access	: 00_23_04_00
 	;
@@ -327,7 +327,7 @@ END(call_do_page_fault)
 
 .Lrestore_regs:
 
-	# Interrpts are actually disabled from this point on, but will get
+	# Interrupts are actually disabled from this point on, but will get
 	# reenabled after we return from interrupt/exception.
 	# But irq tracer needs to be told now...
 	TRACE_ASM_IRQ_ENABLE
@@ -335,7 +335,7 @@ END(call_do_page_fault)
 	lr	r10, [status32]
 
 	; Restore REG File. In case multiple Events outstanding,
-	; use the same priorty as rtie: EXCPN, L2 IRQ, L1 IRQ, None
+	; use the same priority as rtie: EXCPN, L2 IRQ, L1 IRQ, None
 	; Note that we use realtime STATUS32 (not pt_regs->status32) to
 	; decide that.
 
-- 
1.7.1

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#1650373 — Re: [PATCH 04/10] ARC: typos fix in kernel/entry-compact.S

Hi Noam,

On Thu, 2017-05-25 at 05:34 +0300, Noam Camus wrote:
> From: Liav Rehana <liavr@mellanox.com>
> 
> Signed-off-by: Liav Rehana <liavr@mellanox.com>
> Signed-off-by: Noam Camus <noamca@mellanox.com>
> ---
>  arch/arc/kernel/entry-compact.S |   22 +++++++++++-----------
>  1 files changed, 11 insertions(+), 11 deletions(-)

Reviewed-by: Alexey Brodkin <abrodkin@synopsys.com>

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