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Groups > linux.kernel > #1643776 > unrolled thread

[PATCH v3 0/6] clk: sunxi-ng: Add support for A83T CCU

Started byChen-Yu Tsai <wens@csie.org>
First post2017-05-18 06:00 +0200
Last post2017-05-18 10:00 +0200
Articles 5 — 2 participants

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Contents

  [PATCH v3 0/6] clk: sunxi-ng: Add support for A83T CCU Chen-Yu Tsai <wens@csie.org> - 2017-05-18 06:00 +0200
    [PATCH v3 4/6] ARM: sun8i: a83t: Add CCU device nodes Chen-Yu Tsai <wens@csie.org> - 2017-05-18 06:10 +0200
    [PATCH v3 2/6] clk: sunxi-ng: Support multiple variable pre-dividers Chen-Yu Tsai <wens@csie.org> - 2017-05-18 06:10 +0200
    Re: [PATCH v3 3/6] clk: sunxi-ng: Add driver for A83T CCU Maxime Ripard <maxime.ripard@free-electrons.com> - 2017-05-18 09:40 +0200
      Re: [PATCH v3 3/6] clk: sunxi-ng: Add driver for A83T CCU Chen-Yu Tsai <wens@csie.org> - 2017-05-18 10:00 +0200

#1643776 — [PATCH v3 0/6] clk: sunxi-ng: Add support for A83T CCU

FromChen-Yu Tsai <wens@csie.org>
Date2017-05-18 06:00 +0200
Subject[PATCH v3 0/6] clk: sunxi-ng: Add support for A83T CCU
Message-ID<tIkLv-4ef-9@gated-at.bofh.it>
Hi everyone,

This is v3 of my A83T CCU series. This is for 4.13.

Changes since v2:

  - Dropped patches "clk: Provide option to query hardware for clk phase"
    and "clk: sunxi-ng: Add class of phase clocks supporting MMC new timing
    modes".
    
  - Dropped support for MMC new timing mode. This will be added later with
    MMC support. The goal for this series is to get clk support for the A83t
    in. This is long overdue.

  - Explicitly include ccu_mux.h and select SUNXI_CCU_MUX

Changes since v1:

  - Dropped two patches that were merged

  - Added clk core flag to disable caching of clock phases

  - Added support for multiple variable pre-dividers

  - Merged "pll-periph-ahb1" pre-divider clock into "ahb1" clock
    with multiple variable pre-dividers

  - Introduced new class of phase clocks that return -ENOTSUPP
    when the clock is in new timing mode

  - Force mmc2 clock to new timing mode

  - Added back mmc2 output and sample clocks

  - Fixed bit ops for forcing audio PLL configuration

  - Added requirement for "losc" clock in device tree binding

  - Stripped leading 0 in device node name

  - Updated subject prefixes for various patches

Patch 1 adds a compatible string for the A83T CCU to the sunxi-ccu
bindings.

Patch 2 adds support for multiple variable pre-dividers to the sunxi-ng
mux class.

Patch 3 adds the driver for the A83T CCU.

Patch 4 adds the CCU device nodes, and fixes up any existing clock
phandles in the dtsi, without using the macros.

Patch 5 sets the clock accuracy for the main oscillator.

Patch 6 is for the next -rc2, switch the clock indices from raw numbers
to macros we introduced with the driver. This will be updated if more
peripherals are introduced in the same cycle.

Let me know what you think.

Cover letter excerpt from v1:

This is yet another series that adds support for the A83T CCU.
The A83T CCU has a mix of new styled (like the A80) clocks at
old (like A3x) offsets. Some differences include:

  - D1/D2 style PLL clocks
  - divisible audio module clocks
  - new timing mode for mmc2 module clock


Regards
ChenYu


Chen-Yu Tsai (6):
  dt-bindings: clock: sunxi-ccu: Add compatible string for A83T CCU
  clk: sunxi-ng: Support multiple variable pre-dividers
  clk: sunxi-ng: Add driver for A83T CCU
  ARM: sun8i: a83t: Add CCU device nodes
  ARM: sun8i: a83t: Set clock accuracy for 24MHz oscillator
  ARM: sun8i: a83t: Switch to CCU device tree binding macros

 .../devicetree/bindings/clock/sunxi-ccu.txt        |   2 +
 arch/arm/boot/dts/sun8i-a83t.dtsi                  |  19 +-
 drivers/clk/sunxi-ng/Kconfig                       |  11 +
 drivers/clk/sunxi-ng/Makefile                      |   1 +
 drivers/clk/sunxi-ng/ccu-sun50i-a64.c              |  10 +-
 drivers/clk/sunxi-ng/ccu-sun6i-a31.c               |  10 +-
 drivers/clk/sunxi-ng/ccu-sun8i-a23.c               |  10 +-
 drivers/clk/sunxi-ng/ccu-sun8i-a33.c               |  10 +-
 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c              | 910 +++++++++++++++++++++
 drivers/clk/sunxi-ng/ccu-sun8i-a83t.h              |  64 ++
 drivers/clk/sunxi-ng/ccu-sun8i-h3.c                |  10 +-
 drivers/clk/sunxi-ng/ccu-sun8i-r.c                 |  10 +-
 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c               |  10 +-
 drivers/clk/sunxi-ng/ccu_mux.c                     |  15 +-
 drivers/clk/sunxi-ng/ccu_mux.h                     |  13 +-
 include/dt-bindings/clock/sun8i-a83t-ccu.h         | 140 ++++
 include/dt-bindings/reset/sun8i-a83t-ccu.h         |  98 +++
 17 files changed, 1294 insertions(+), 49 deletions(-)
 create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c
 create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-a83t.h
 create mode 100644 include/dt-bindings/clock/sun8i-a83t-ccu.h
 create mode 100644 include/dt-bindings/reset/sun8i-a83t-ccu.h

-- 
2.11.0

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#1643778 — [PATCH v3 4/6] ARM: sun8i: a83t: Add CCU device nodes

FromChen-Yu Tsai <wens@csie.org>
Date2017-05-18 06:10 +0200
Subject[PATCH v3 4/6] ARM: sun8i: a83t: Add CCU device nodes
Message-ID<tIkVb-4yB-19@gated-at.bofh.it>
In reply to#1643776
Now that we have support for the A83T CCU, add a device node for it,
and replace any existing placeholder clock phandles with the correct
ones.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 arch/arm/boot/dts/sun8i-a83t.dtsi | 15 +++++++++++++--
 1 file changed, 13 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi
index c0a1e4f74b89..c9a5d07b2ada 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -162,13 +162,23 @@
 		#size-cells = <1>;
 		ranges;
 
+		ccu: clock@1c20000 {
+			compatible = "allwinner,sun8i-a83t-ccu";
+			reg = <0x01c20000 0x400>;
+			clocks = <&osc24M>, <&osc16Md512>;
+			clock-names = "hosc", "losc";
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+		};
+
 		pio: pinctrl@1c20800 {
 			compatible = "allwinner,sun8i-a83t-pinctrl";
 			interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 			reg = <0x01c20800 0x400>;
-			clocks = <&osc24M>;
+			clocks = <&ccu 45>, <&osc24M>, <&osc16Md512>;
+			clock-names = "apb", "hosc", "losc";
 			gpio-controller;
 			interrupt-controller;
 			#interrupt-cells = <3>;
@@ -214,7 +224,8 @@
 			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
 			reg-shift = <2>;
 			reg-io-width = <4>;
-			clocks = <&osc24M>;
+			clocks = <&ccu 53>;
+			resets = <&ccu 40>;
 			status = "disabled";
 		};
 
-- 
2.11.0

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#1643779 — [PATCH v3 2/6] clk: sunxi-ng: Support multiple variable pre-dividers

FromChen-Yu Tsai <wens@csie.org>
Date2017-05-18 06:10 +0200
Subject[PATCH v3 2/6] clk: sunxi-ng: Support multiple variable pre-dividers
Message-ID<tIkVb-4yB-13@gated-at.bofh.it>
In reply to#1643776
On the A83T, the AHB1 clock has a shared pre-divider on the two
PLL-PERIPH clock parents. To support such instances of shared
pre-dividers, this patch extends the mux clock type to support
multiple variable pre-dividers.

As the pre-dividers are only used to calculate the rate, but
do not participate in the factorization process, this is fairly
straightforward.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 10 +++++-----
 drivers/clk/sunxi-ng/ccu-sun6i-a31.c  | 10 +++++-----
 drivers/clk/sunxi-ng/ccu-sun8i-a23.c  | 10 +++++-----
 drivers/clk/sunxi-ng/ccu-sun8i-a33.c  | 10 +++++-----
 drivers/clk/sunxi-ng/ccu-sun8i-h3.c   | 10 +++++-----
 drivers/clk/sunxi-ng/ccu-sun8i-r.c    | 10 +++++-----
 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c  | 10 +++++-----
 drivers/clk/sunxi-ng/ccu_mux.c        | 15 ++++++++-------
 drivers/clk/sunxi-ng/ccu_mux.h        | 13 ++++++++-----
 9 files changed, 51 insertions(+), 47 deletions(-)

diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
index f54114c607df..2bb4cabf802f 100644
--- a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
+++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
@@ -211,6 +211,9 @@ static SUNXI_CCU_M(axi_clk, "axi", "cpux", 0x050, 0, 2, 0);
 
 static const char * const ahb1_parents[] = { "osc32k", "osc24M",
 					     "axi", "pll-periph0" };
+static const struct ccu_mux_var_prediv ahb1_predivs[] = {
+	{ .index = 3, .shift = 6, .width = 2 },
+};
 static struct ccu_div ahb1_clk = {
 	.div		= _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
 
@@ -218,11 +221,8 @@ static struct ccu_div ahb1_clk = {
 		.shift	= 12,
 		.width	= 2,
 
-		.variable_prediv	= {
-			.index	= 3,
-			.shift	= 6,
-			.width	= 2,
-		},
+		.var_predivs	= ahb1_predivs,
+		.n_var_predivs	= ARRAY_SIZE(ahb1_predivs),
 	},
 
 	.common		= {
diff --git a/drivers/clk/sunxi-ng/ccu-sun6i-a31.c b/drivers/clk/sunxi-ng/ccu-sun6i-a31.c
index df97e25aec76..4d6078fca9ac 100644
--- a/drivers/clk/sunxi-ng/ccu-sun6i-a31.c
+++ b/drivers/clk/sunxi-ng/ccu-sun6i-a31.c
@@ -195,6 +195,9 @@ static SUNXI_CCU_DIV_TABLE(axi_clk, "axi", "cpu",
 
 static const char * const ahb1_parents[] = { "osc32k", "osc24M",
 					     "axi", "pll-periph" };
+static const struct ccu_mux_var_prediv ahb1_predivs[] = {
+	{ .index = 3, .shift = 6, .width = 2 },
+};
 
 static struct ccu_div ahb1_clk = {
 	.div		= _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
@@ -203,11 +206,8 @@ static struct ccu_div ahb1_clk = {
 		.shift	= 12,
 		.width	= 2,
 
-		.variable_prediv	= {
-			.index	= 3,
-			.shift	= 6,
-			.width	= 2,
-		},
+		.var_predivs	= ahb1_predivs,
+		.n_var_predivs	= ARRAY_SIZE(ahb1_predivs),
 	},
 
 	.common		= {
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-a23.c b/drivers/clk/sunxi-ng/ccu-sun8i-a23.c
index 5c6d37bdf247..8a753ed0426d 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-a23.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-a23.c
@@ -169,6 +169,9 @@ static SUNXI_CCU_M(axi_clk, "axi", "cpux", 0x050, 0, 2, 0);
 
 static const char * const ahb1_parents[] = { "osc32k", "osc24M",
 					     "axi" , "pll-periph" };
+static const struct ccu_mux_var_prediv ahb1_predivs[] = {
+	{ .index = 3, .shift = 6, .width = 2 },
+};
 static struct ccu_div ahb1_clk = {
 	.div		= _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
 
@@ -176,11 +179,8 @@ static struct ccu_div ahb1_clk = {
 		.shift	= 12,
 		.width	= 2,
 
-		.variable_prediv	= {
-			.index	= 3,
-			.shift	= 6,
-			.width	= 2,
-		},
+		.var_predivs	= ahb1_predivs,
+		.n_var_predivs	= ARRAY_SIZE(ahb1_predivs),
 	},
 
 	.common		= {
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-a33.c b/drivers/clk/sunxi-ng/ccu-sun8i-a33.c
index 8d38e6510e29..10b38dc46f75 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-a33.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-a33.c
@@ -180,6 +180,9 @@ static SUNXI_CCU_M(axi_clk, "axi", "cpux", 0x050, 0, 2, 0);
 
 static const char * const ahb1_parents[] = { "osc32k", "osc24M",
 					     "axi" , "pll-periph" };
+static const struct ccu_mux_var_prediv ahb1_predivs[] = {
+	{ .index = 3, .shift = 6, .width = 2 },
+};
 static struct ccu_div ahb1_clk = {
 	.div		= _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
 
@@ -187,11 +190,8 @@ static struct ccu_div ahb1_clk = {
 		.shift	= 12,
 		.width	= 2,
 
-		.variable_prediv	= {
-			.index	= 3,
-			.shift	= 6,
-			.width	= 2,
-		},
+		.var_predivs	= ahb1_predivs,
+		.n_var_predivs	= ARRAY_SIZE(ahb1_predivs),
 	},
 
 	.common		= {
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
index 4cbc1b701b7c..62e4f0d2b2fc 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
@@ -141,6 +141,9 @@ static SUNXI_CCU_M(axi_clk, "axi", "cpux", 0x050, 0, 2, 0);
 
 static const char * const ahb1_parents[] = { "osc32k", "osc24M",
 					     "axi" , "pll-periph0" };
+static const struct ccu_mux_var_prediv ahb1_predivs[] = {
+	{ .index = 3, .shift = 6, .width = 2 },
+};
 static struct ccu_div ahb1_clk = {
 	.div		= _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
 
@@ -148,11 +151,8 @@ static struct ccu_div ahb1_clk = {
 		.shift	= 12,
 		.width	= 2,
 
-		.variable_prediv	= {
-			.index	= 3,
-			.shift	= 6,
-			.width	= 2,
-		},
+		.var_predivs	= ahb1_predivs,
+		.n_var_predivs	= ARRAY_SIZE(ahb1_predivs),
 	},
 
 	.common		= {
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-r.c b/drivers/clk/sunxi-ng/ccu-sun8i-r.c
index 119f47b568ea..de02be75785c 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-r.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-r.c
@@ -27,6 +27,9 @@
 
 static const char * const ar100_parents[] = { "osc32k", "osc24M",
 					     "pll-periph0", "iosc" };
+static const struct ccu_mux_var_prediv ar100_predivs[] = {
+	{ .index = 2, .shift = 8, .width = 5 },
+};
 
 static struct ccu_div ar100_clk = {
 	.div		= _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
@@ -35,11 +38,8 @@ static struct ccu_div ar100_clk = {
 		.shift	= 16,
 		.width	= 2,
 
-		.variable_prediv	= {
-			.index	= 2,
-			.shift	= 8,
-			.width	= 5,
-		},
+		.var_predivs	= ar100_predivs,
+		.n_var_predivs	= ARRAY_SIZE(ar100_predivs),
 	},
 
 	.common		= {
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c b/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c
index 6297add857b5..a34a78d7fb28 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c
@@ -132,6 +132,9 @@ static SUNXI_CCU_M(axi_clk, "axi", "cpu", 0x050, 0, 2, 0);
 
 static const char * const ahb1_parents[] = { "osc32k", "osc24M",
 					     "axi", "pll-periph0" };
+static const struct ccu_mux_var_prediv ahb1_predivs[] = {
+	{ .index = 3, .shift = 6, .width = 2 },
+};
 static struct ccu_div ahb1_clk = {
 	.div		= _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
 
@@ -139,11 +142,8 @@ static struct ccu_div ahb1_clk = {
 		.shift	= 12,
 		.width	= 2,
 
-		.variable_prediv	= {
-			.index	= 3,
-			.shift	= 6,
-			.width	= 2,
-		},
+		.var_predivs	= ahb1_predivs,
+		.n_var_predivs	= ARRAY_SIZE(ahb1_predivs),
 	},
 
 	.common		= {
diff --git a/drivers/clk/sunxi-ng/ccu_mux.c b/drivers/clk/sunxi-ng/ccu_mux.c
index c6bb1f523232..b1eaafac9f23 100644
--- a/drivers/clk/sunxi-ng/ccu_mux.c
+++ b/drivers/clk/sunxi-ng/ccu_mux.c
@@ -46,13 +46,14 @@ void ccu_mux_helper_adjust_parent_for_prediv(struct ccu_common *common,
 				prediv = cm->fixed_predivs[i].div;
 
 	if (common->features & CCU_FEATURE_VARIABLE_PREDIV)
-		if (parent_index == cm->variable_prediv.index) {
-			u8 div;
-
-			div = reg >> cm->variable_prediv.shift;
-			div &= (1 << cm->variable_prediv.width) - 1;
-			prediv = div + 1;
-		}
+		for (i = 0; i < cm->n_var_predivs; i++)
+			if (parent_index == cm->var_predivs[i].index) {
+				u8 div;
+
+				div = reg >> cm->var_predivs[i].shift;
+				div &= (1 << cm->var_predivs[i].width) - 1;
+				prediv = div + 1;
+			}
 
 	*parent_rate = *parent_rate / prediv;
 }
diff --git a/drivers/clk/sunxi-ng/ccu_mux.h b/drivers/clk/sunxi-ng/ccu_mux.h
index 47aba3a48245..044262245c07 100644
--- a/drivers/clk/sunxi-ng/ccu_mux.h
+++ b/drivers/clk/sunxi-ng/ccu_mux.h
@@ -10,6 +10,12 @@ struct ccu_mux_fixed_prediv {
 	u16	div;
 };
 
+struct ccu_mux_var_prediv {
+	u8	index;
+	u8	shift;
+	u8	width;
+};
+
 struct ccu_mux_internal {
 	u8		shift;
 	u8		width;
@@ -18,11 +24,8 @@ struct ccu_mux_internal {
 	const struct ccu_mux_fixed_prediv	*fixed_predivs;
 	u8		n_predivs;
 
-	struct {
-		u8	index;
-		u8	shift;
-		u8	width;
-	} variable_prediv;
+	const struct ccu_mux_var_prediv		*var_predivs;
+	u8		n_var_predivs;
 };
 
 #define _SUNXI_CCU_MUX_TABLE(_shift, _width, _table)	\
-- 
2.11.0

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#1643904 — Re: [PATCH v3 3/6] clk: sunxi-ng: Add driver for A83T CCU

FromMaxime Ripard <maxime.ripard@free-electrons.com>
Date2017-05-18 09:40 +0200
SubjectRe: [PATCH v3 3/6] clk: sunxi-ng: Add driver for A83T CCU
Message-ID<tIocp-75A-3@gated-at.bofh.it>
In reply to#1643776

[Multipart message — attachments visible in raw view] — view raw

On Thu, May 18, 2017 at 11:58:06AM +0800, Chen-Yu Tsai wrote:
> +/*
> + * MMC2 supports both old and new timing modes. When the new timing
> + * mode is active, the output clock rate is halved by two. Here we
> + * treat it as a variable pre-divider. Note that the pre-divider is
> + * _not_ included in the possible factors during a set clock rate
> + * operation. It is only read out.
> + */
> +#define SUN8I_A83T_MMC2_REG	0x090
> +static const struct ccu_mux_var_prediv mmc2_new_timing_predivs[] = {
> +	{ .index = 0, .shift = 30, .width = 1 },
> +	{ .index = 1, .shift = 30, .width = 1 },
> +};
> +static struct ccu_mp mmc2_clk = {
> +	.enable	= BIT(31),
> +	.m	= _SUNXI_CCU_DIV(0, 4),
> +	.p	= _SUNXI_CCU_DIV(16, 2),
> +	.mux	= {
> +		.shift	= 24,
> +		.width	= 2,
> +		.var_predivs	= mmc2_new_timing_predivs,
> +		.n_var_predivs	= ARRAY_SIZE(mmc2_new_timing_predivs),
> +	},
> +	.common		= {
> +		.reg		= 0x090,
> +		.hw.init	= CLK_HW_INIT_PARENTS("mmc2",
> +						      mod0_default_parents,
> +						      &ccu_mp_ops,
> +						      CLK_GET_RATE_NOCACHE),
> +	},
> +};
> +
> +static SUNXI_CCU_PHASE(mmc2_sample_clk, "mmc2-sample", "mmc2",
> +		       0x090, 20, 3, 0);
> +static SUNXI_CCU_PHASE(mmc2_output_clk, "mmc2-output", "mmc2",
> +		       0x090, 8, 3, 0);

I'm sorry to be a pain for this, but we're in the exact same situation
for the A83T than the A33 or the H3. There's no reason we'd do
something different with the MMC clocks only on the A83T.

What I'd like to happen is:
  1) Get the A83T ccu driver in, without *any* of the new mode
     handling.
  2) Work on the new mode for the A33, A83T and H3 (and the other I
     might have forgotten).

This issue really isn't A83 specific, there's no reason to come up
with A83 specific code.

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

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#1643920 — Re: [PATCH v3 3/6] clk: sunxi-ng: Add driver for A83T CCU

FromChen-Yu Tsai <wens@csie.org>
Date2017-05-18 10:00 +0200
SubjectRe: [PATCH v3 3/6] clk: sunxi-ng: Add driver for A83T CCU
Message-ID<tIovM-7em-11@gated-at.bofh.it>
In reply to#1643904
On Thu, May 18, 2017 at 3:39 PM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> On Thu, May 18, 2017 at 11:58:06AM +0800, Chen-Yu Tsai wrote:
>> +/*
>> + * MMC2 supports both old and new timing modes. When the new timing
>> + * mode is active, the output clock rate is halved by two. Here we
>> + * treat it as a variable pre-divider. Note that the pre-divider is
>> + * _not_ included in the possible factors during a set clock rate
>> + * operation. It is only read out.
>> + */
>> +#define SUN8I_A83T_MMC2_REG  0x090
>> +static const struct ccu_mux_var_prediv mmc2_new_timing_predivs[] = {
>> +     { .index = 0, .shift = 30, .width = 1 },
>> +     { .index = 1, .shift = 30, .width = 1 },
>> +};
>> +static struct ccu_mp mmc2_clk = {
>> +     .enable = BIT(31),
>> +     .m      = _SUNXI_CCU_DIV(0, 4),
>> +     .p      = _SUNXI_CCU_DIV(16, 2),
>> +     .mux    = {
>> +             .shift  = 24,
>> +             .width  = 2,
>> +             .var_predivs    = mmc2_new_timing_predivs,
>> +             .n_var_predivs  = ARRAY_SIZE(mmc2_new_timing_predivs),
>> +     },
>> +     .common         = {
>> +             .reg            = 0x090,
>> +             .hw.init        = CLK_HW_INIT_PARENTS("mmc2",
>> +                                                   mod0_default_parents,
>> +                                                   &ccu_mp_ops,
>> +                                                   CLK_GET_RATE_NOCACHE),
>> +     },
>> +};
>> +
>> +static SUNXI_CCU_PHASE(mmc2_sample_clk, "mmc2-sample", "mmc2",
>> +                    0x090, 20, 3, 0);
>> +static SUNXI_CCU_PHASE(mmc2_output_clk, "mmc2-output", "mmc2",
>> +                    0x090, 8, 3, 0);
>
> I'm sorry to be a pain for this, but we're in the exact same situation
> for the A83T than the A33 or the H3. There's no reason we'd do
> something different with the MMC clocks only on the A83T.
>
> What I'd like to happen is:
>   1) Get the A83T ccu driver in, without *any* of the new mode
>      handling.
>   2) Work on the new mode for the A33, A83T and H3 (and the other I
>      might have forgotten).
>
> This issue really isn't A83 specific, there's no reason to come up
> with A83 specific code.

So to recap, you want mmc2_clk without the new pre-dividers here.
Then we add them for _all_ SoCs that have the old/new mode switch
at the same time. Is that correct?

This really isn't A83T specific code. It's just one way to handle
the extra divider for the new timing mode. Obviously we will add the
functions to query and set the timing mode bit, but that will be
generic. If you want all code related to the new mode in one patch,
then I understand.

ChenYu

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