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Re: [PATCH v3 3/6] clk: sunxi-ng: Add driver for A83T CCU

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On Thu, May 18, 2017 at 3:39 PM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> On Thu, May 18, 2017 at 11:58:06AM +0800, Chen-Yu Tsai wrote:
>> +/*
>> + * MMC2 supports both old and new timing modes. When the new timing
>> + * mode is active, the output clock rate is halved by two. Here we
>> + * treat it as a variable pre-divider. Note that the pre-divider is
>> + * _not_ included in the possible factors during a set clock rate
>> + * operation. It is only read out.
>> + */
>> +#define SUN8I_A83T_MMC2_REG  0x090
>> +static const struct ccu_mux_var_prediv mmc2_new_timing_predivs[] = {
>> +     { .index = 0, .shift = 30, .width = 1 },
>> +     { .index = 1, .shift = 30, .width = 1 },
>> +};
>> +static struct ccu_mp mmc2_clk = {
>> +     .enable = BIT(31),
>> +     .m      = _SUNXI_CCU_DIV(0, 4),
>> +     .p      = _SUNXI_CCU_DIV(16, 2),
>> +     .mux    = {
>> +             .shift  = 24,
>> +             .width  = 2,
>> +             .var_predivs    = mmc2_new_timing_predivs,
>> +             .n_var_predivs  = ARRAY_SIZE(mmc2_new_timing_predivs),
>> +     },
>> +     .common         = {
>> +             .reg            = 0x090,
>> +             .hw.init        = CLK_HW_INIT_PARENTS("mmc2",
>> +                                                   mod0_default_parents,
>> +                                                   &ccu_mp_ops,
>> +                                                   CLK_GET_RATE_NOCACHE),
>> +     },
>> +};
>> +
>> +static SUNXI_CCU_PHASE(mmc2_sample_clk, "mmc2-sample", "mmc2",
>> +                    0x090, 20, 3, 0);
>> +static SUNXI_CCU_PHASE(mmc2_output_clk, "mmc2-output", "mmc2",
>> +                    0x090, 8, 3, 0);
>
> I'm sorry to be a pain for this, but we're in the exact same situation
> for the A83T than the A33 or the H3. There's no reason we'd do
> something different with the MMC clocks only on the A83T.
>
> What I'd like to happen is:
>   1) Get the A83T ccu driver in, without *any* of the new mode
>      handling.
>   2) Work on the new mode for the A33, A83T and H3 (and the other I
>      might have forgotten).
>
> This issue really isn't A83 specific, there's no reason to come up
> with A83 specific code.

So to recap, you want mmc2_clk without the new pre-dividers here.
Then we add them for _all_ SoCs that have the old/new mode switch
at the same time. Is that correct?

This really isn't A83T specific code. It's just one way to handle
the extra divider for the new timing mode. Obviously we will add the
functions to query and set the timing mode bit, but that will be
generic. If you want all code related to the new mode in one patch,
then I understand.

ChenYu

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[PATCH v3 0/6] clk: sunxi-ng: Add support for A83T CCU Chen-Yu Tsai <wens@csie.org> - 2017-05-18 06:00 +0200
  [PATCH v3 4/6] ARM: sun8i: a83t: Add CCU device nodes Chen-Yu Tsai <wens@csie.org> - 2017-05-18 06:10 +0200
  [PATCH v3 2/6] clk: sunxi-ng: Support multiple variable pre-dividers Chen-Yu Tsai <wens@csie.org> - 2017-05-18 06:10 +0200
  Re: [PATCH v3 3/6] clk: sunxi-ng: Add driver for A83T CCU Maxime Ripard <maxime.ripard@free-electrons.com> - 2017-05-18 09:40 +0200
    Re: [PATCH v3 3/6] clk: sunxi-ng: Add driver for A83T CCU Chen-Yu Tsai <wens@csie.org> - 2017-05-18 10:00 +0200

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