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Re: [PATCH v2 1/5] pinctrl: qcom: Add ipq8074 pinctrl driver

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  Re: [PATCH v2 1/5] pinctrl: qcom: Add ipq8074 pinctrl driver Bjorn Andersson <bjorn.andersson@linaro.org> - 2017-05-14 06:30 +0200
    Re: [PATCH v2 1/5] pinctrl: qcom: Add ipq8074 pinctrl driver Varadarajan Narayanan <varada@codeaurora.org> - 2017-05-15 11:10 +0200
      Re: [PATCH v2 1/5] pinctrl: qcom: Add ipq8074 pinctrl driver Varadarajan Narayanan <varada@codeaurora.org> - 2017-05-15 13:30 +0200
        Re: [PATCH v2 1/5] pinctrl: qcom: Add ipq8074 pinctrl driver Bjorn Andersson <bjorn.andersson@linaro.org> - 2017-05-17 21:50 +0200
          Re: [PATCH v2 1/5] pinctrl: qcom: Add ipq8074 pinctrl driver Varadarajan Narayanan <varada@codeaurora.org> - 2017-05-18 10:40 +0200
      Re: [PATCH v2 1/5] pinctrl: qcom: Add ipq8074 pinctrl driver Bjorn Andersson <bjorn.andersson@linaro.org> - 2017-05-17 21:40 +0200
        Re: [PATCH v2 1/5] pinctrl: qcom: Add ipq8074 pinctrl driver Varadarajan Narayanan <varada@codeaurora.org> - 2017-05-18 10:40 +0200
          Re: [PATCH v2 1/5] pinctrl: qcom: Add ipq8074 pinctrl driver Bjorn Andersson <bjorn.andersson@linaro.org> - 2017-05-20 08:00 +0200
            Re: [PATCH v2 1/5] pinctrl: qcom: Add ipq8074 pinctrl driver Linus Walleij <linus.walleij@linaro.org> - 2017-05-23 11:30 +0200

#1641056 — Re: [PATCH v2 1/5] pinctrl: qcom: Add ipq8074 pinctrl driver

On Thu 11 May 03:33 PDT 2017, Varadarajan Narayanan wrote:

> 
> 
> On 5/11/2017 4:13 AM, Bjorn Andersson wrote:
> > On Thu 04 May 04:53 PDT 2017, Varadarajan Narayanan wrote:
> > 
[..]
> > > +enum ipq8074_functions {
> > 
> > Please keep these sorted alphabetically.
> 
> Ok
> 
> > > +	msm_mux_gpio,
> > > +	msm_mux_qpic_pad,
> > > +	msm_mux_blsp5_i2c,
> > > +	msm_mux_blsp5_spi,
> > > +	msm_mux_wci20,
> > 
> > What does "20" mean here?
> 
> This is for Wireless Coex Interface. The same functionality can be muxed on
> to different GPIOs. WCI2, is the 2nd edition of the WCI standard and 0, 1
> are for the muxing to different GPIOs (alternate muxes).
> 

In other Qualcomm platforms the alternative muxes are denoted by letters
(a,b,c...). Would you mind picking up this naming scheme, or do you see
any problems with that? (E.g. wci2a in this case)


Btw, do you need any additional configuration for selecting alternative
muxing or is that automagical these days?

> > > +	msm_mux_blsp3_spi3,
> > > +	msm_mux_burn0,
> > > +	msm_mux_pcm_zsi0,
> > > +	msm_mux_blsp5_uart,
> > > +	msm_mux_mac12,
> > 
> > What does "12" mean here?
> 
> The SoC has three MAC cores. Each core has two pins for the smart antenna
> feature. macXY indicates the function select for MAC no. X and smart antenna
> no. Y.
> 

Ok

> > > +	msm_mux_blsp3_spi0,
> > > +	msm_mux_burn1,
> > > +	msm_mux_mac01,
> > > +	msm_mux_qdss_cti_trig_out_b0,
> > > +	msm_mux_qdss_cti_trig_in_b0,
> > > +	msm_mux_qpic_pad4,
> > 
> > What are qpic_pad and qpic_pad0 through qpic_pad8? Different functions,
> > alternative muxings...?
> 
> This is for the NAND and LCD display. The pins listed are the 9 data pins.
> 

Then you can describe them all as "qpic_pad" (or simply "qpic"?). (It's
possible to reference a partial group in the DTS, if that's necessary)

> > > +	msm_mux_blsp4_uart0,
> > > +	msm_mux_blsp4_i2c0,
> > > +	msm_mux_blsp4_spi0,
> > > +	msm_mux_mac21,
> > > +	msm_mux_qdss_cti_trig_out_b1,
> > > +	msm_mux_qpic_pad5,
> > > +	msm_mux_qdss_cti_trig_in_b1,
> > > +	msm_mux_qpic_pad6,
> > > +	msm_mux_qpic_pad7,
> > > +	msm_mux_cxc0,
> > > +	msm_mux_mac13,
> > > +	msm_mux_qdss_cti_trig_in_a1,
> > > +	msm_mux_qdss_cti_trig_out_a1,
> > > +	msm_mux_wci22,
> > > +	msm_mux_qdss_cti_trig_in_a0,
> > > +	msm_mux_qpic_pad1,
> > > +	msm_mux_qdss_cti_trig_out_a0,
> > > +	msm_mux_qpic_pad2,
> > > +	msm_mux_qpic_pad3,
> > > +	msm_mux_qdss_traceclk_b,
> > > +	msm_mux_qpic_pad0,
> > > +	msm_mux_qdss_tracectl_b,
> > > +	msm_mux_qpic_pad8,
> > > +	msm_mux_pcm_zsi1,
> > > +	msm_mux_qdss_tracedata_b,
> > > +	msm_mux_led0,
> > > +	msm_mux_pwm04,
> > 
> > What does "04" mean here?
> 
> There are 4 Pulse Width Modulation channels, pwmXY is pwm channel X and pin
> Y.

So Y is alternative mux? Can we use letters for this as well?

> > 
> > > +	msm_mux_led1,
> > > +	msm_mux_pwm14,
> > > +	msm_mux_led2,
> > > +	msm_mux_pwm24,
> > > +	msm_mux_pwm00,
> > > +	msm_mux_blsp4_uart1,
> > 
> > Are uart0 vs uart1 alternative muxes?
> 
> These are two different uarts available at two independent pins.
> 

Ok, then I'm happy with the naming of this :)

Thanks,
Bjorn

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#1641414

On 5/14/2017 9:53 AM, Bjorn Andersson wrote:
> On Thu 11 May 03:33 PDT 2017, Varadarajan Narayanan wrote:
> 
>> On 5/11/2017 4:13 AM, Bjorn Andersson wrote:
>>> On Thu 04 May 04:53 PDT 2017, Varadarajan Narayanan wrote:
>>>
> [..]
>>>> +enum ipq8074_functions {
>>>
>>> Please keep these sorted alphabetically.
>>
>> Ok
>>
>>>> +	msm_mux_gpio,
>>>> +	msm_mux_qpic_pad,
>>>> +	msm_mux_blsp5_i2c,
>>>> +	msm_mux_blsp5_spi,
>>>> +	msm_mux_wci20,
>>>
>>> What does "20" mean here?
>>
>> This is for Wireless Coex Interface. The same functionality can be muxed on
>> to different GPIOs. WCI2, is the 2nd edition of the WCI standard and 0, 1
>> are for the muxing to different GPIOs (alternate muxes).
>>
> 
> In other Qualcomm platforms the alternative muxes are denoted by letters
> (a,b,c...). Would you mind picking up this naming scheme, or do you see
> any problems with that? (E.g. wci2a in this case)

Ok

> Btw, do you need any additional configuration for selecting alternative
> muxing or is that automagical these days?

No additional configuration is needed.

>>>> +	msm_mux_blsp3_spi3,
>>>> +	msm_mux_burn0,
>>>> +	msm_mux_pcm_zsi0,
>>>> +	msm_mux_blsp5_uart,
>>>> +	msm_mux_mac12,
>>>
>>> What does "12" mean here?
>>
>> The SoC has three MAC cores. Each core has two pins for the smart antenna
>> feature. macXY indicates the function select for MAC no. X and smart antenna
>> no. Y.
>>
> 
> Ok
> 
>>>> +	msm_mux_blsp3_spi0,
>>>> +	msm_mux_burn1,
>>>> +	msm_mux_mac01,
>>>> +	msm_mux_qdss_cti_trig_out_b0,
>>>> +	msm_mux_qdss_cti_trig_in_b0,
>>>> +	msm_mux_qpic_pad4,
>>>
>>> What are qpic_pad and qpic_pad0 through qpic_pad8? Different functions,
>>> alternative muxings...?
>>
>> This is for the NAND and LCD display. The pins listed are the 9 data pins.
>>
> 
> Then you can describe them all as "qpic_pad" (or simply "qpic"?). (It's
> possible to reference a partial group in the DTS, if that's necessary)

There are two sets of 9 pins, either of which can go to NAND or LCD.
Will rename qpic_pad as qpic_a and qpic_pad[0-8] as qpic_b.
Is that ok?

>>>> +	msm_mux_blsp4_uart0,
>>>> +	msm_mux_blsp4_i2c0,
>>>> +	msm_mux_blsp4_spi0,
>>>> +	msm_mux_mac21,
>>>> +	msm_mux_qdss_cti_trig_out_b1,
>>>> +	msm_mux_qpic_pad5,
>>>> +	msm_mux_qdss_cti_trig_in_b1,
>>>> +	msm_mux_qpic_pad6,
>>>> +	msm_mux_qpic_pad7,
>>>> +	msm_mux_cxc0,
>>>> +	msm_mux_mac13,
>>>> +	msm_mux_qdss_cti_trig_in_a1,
>>>> +	msm_mux_qdss_cti_trig_out_a1,
>>>> +	msm_mux_wci22,
>>>> +	msm_mux_qdss_cti_trig_in_a0,
>>>> +	msm_mux_qpic_pad1,
>>>> +	msm_mux_qdss_cti_trig_out_a0,
>>>> +	msm_mux_qpic_pad2,
>>>> +	msm_mux_qpic_pad3,
>>>> +	msm_mux_qdss_traceclk_b,
>>>> +	msm_mux_qpic_pad0,
>>>> +	msm_mux_qdss_tracectl_b,
>>>> +	msm_mux_qpic_pad8,
>>>> +	msm_mux_pcm_zsi1,
>>>> +	msm_mux_qdss_tracedata_b,
>>>> +	msm_mux_led0,
>>>> +	msm_mux_pwm04,
>>>
>>> What does "04" mean here?
>>
>> There are 4 Pulse Width Modulation channels, pwmXY is pwm channel X and pin
>> Y.
> 
> So Y is alternative mux? Can we use letters for this as well?

Ok

>>>> +	msm_mux_led1,
>>>> +	msm_mux_pwm14,
>>>> +	msm_mux_led2,
>>>> +	msm_mux_pwm24,
>>>> +	msm_mux_pwm00,
>>>> +	msm_mux_blsp4_uart1,
>>>
>>> Are uart0 vs uart1 alternative muxes?
>>
>> These are two different uarts available at two independent pins.
>>
> 
> Ok, then I'm happy with the naming of this :)
> 
> Thanks,
> Bjorn
> 

Thanks
Varada
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora 
Forum, a Linux Foundation Collaborative Project

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#1641568

On 5/15/2017 2:35 PM, Varadarajan Narayanan wrote:
> On 5/14/2017 9:53 AM, Bjorn Andersson wrote:
>> On Thu 11 May 03:33 PDT 2017, Varadarajan Narayanan wrote:
>>
>>> On 5/11/2017 4:13 AM, Bjorn Andersson wrote:
>>>> On Thu 04 May 04:53 PDT 2017, Varadarajan Narayanan wrote:
>>>>
>> [..]
>>>>> +enum ipq8074_functions {
>>>>
>>>> Please keep these sorted alphabetically.
>>>
>>> Ok
>>>
>>>>> +    msm_mux_gpio,
>>>>> +    msm_mux_qpic_pad,
>>>>> +    msm_mux_blsp5_i2c,
>>>>> +    msm_mux_blsp5_spi,
>>>>> +    msm_mux_wci20,
>>>>
>>>> What does "20" mean here?
>>>
>>> This is for Wireless Coex Interface. The same functionality can be 
>>> muxed on
>>> to different GPIOs. WCI2, is the 2nd edition of the WCI standard and 
>>> 0, 1
>>> are for the muxing to different GPIOs (alternate muxes).
>>>
>>
>> In other Qualcomm platforms the alternative muxes are denoted by letters
>> (a,b,c...). Would you mind picking up this naming scheme, or do you see
>> any problems with that? (E.g. wci2a in this case)
> 
> Ok
> 
>> Btw, do you need any additional configuration for selecting alternative
>> muxing or is that automagical these days?
> 
> No additional configuration is needed.
> 
>>>>> +    msm_mux_blsp3_spi3,
>>>>> +    msm_mux_burn0,
>>>>> +    msm_mux_pcm_zsi0,
>>>>> +    msm_mux_blsp5_uart,
>>>>> +    msm_mux_mac12,
>>>>
>>>> What does "12" mean here?
>>>
>>> The SoC has three MAC cores. Each core has two pins for the smart 
>>> antenna
>>> feature. macXY indicates the function select for MAC no. X and smart 
>>> antenna
>>> no. Y.
>>>
>>
>> Ok
>>
>>>>> +    msm_mux_blsp3_spi0,
>>>>> +    msm_mux_burn1,
>>>>> +    msm_mux_mac01,
>>>>> +    msm_mux_qdss_cti_trig_out_b0,
>>>>> +    msm_mux_qdss_cti_trig_in_b0,
>>>>> +    msm_mux_qpic_pad4,
>>>>
>>>> What are qpic_pad and qpic_pad0 through qpic_pad8? Different functions,
>>>> alternative muxings...?
>>>
>>> This is for the NAND and LCD display. The pins listed are the 9 data 
>>> pins.
>>>
>>
>> Then you can describe them all as "qpic_pad" (or simply "qpic"?). (It's
>> possible to reference a partial group in the DTS, if that's necessary)
> 
> There are two sets of 9 pins, either of which can go to NAND or LCD.
> Will rename qpic_pad as qpic_a and qpic_pad[0-8] as qpic_b.
> Is that ok?
> 
>>>>> +    msm_mux_blsp4_uart0,
>>>>> +    msm_mux_blsp4_i2c0,
>>>>> +    msm_mux_blsp4_spi0,
>>>>> +    msm_mux_mac21,
>>>>> +    msm_mux_qdss_cti_trig_out_b1,
>>>>> +    msm_mux_qpic_pad5,
>>>>> +    msm_mux_qdss_cti_trig_in_b1,
>>>>> +    msm_mux_qpic_pad6,
>>>>> +    msm_mux_qpic_pad7,
>>>>> +    msm_mux_cxc0,
>>>>> +    msm_mux_mac13,
>>>>> +    msm_mux_qdss_cti_trig_in_a1,
>>>>> +    msm_mux_qdss_cti_trig_out_a1,
>>>>> +    msm_mux_wci22,
>>>>> +    msm_mux_qdss_cti_trig_in_a0,
>>>>> +    msm_mux_qpic_pad1,
>>>>> +    msm_mux_qdss_cti_trig_out_a0,
>>>>> +    msm_mux_qpic_pad2,
>>>>> +    msm_mux_qpic_pad3,
>>>>> +    msm_mux_qdss_traceclk_b,
>>>>> +    msm_mux_qpic_pad0,
>>>>> +    msm_mux_qdss_tracectl_b,
>>>>> +    msm_mux_qpic_pad8,
>>>>> +    msm_mux_pcm_zsi1,
>>>>> +    msm_mux_qdss_tracedata_b,
>>>>> +    msm_mux_led0,
>>>>> +    msm_mux_pwm04,
>>>>
>>>> What does "04" mean here?
>>>
>>> There are 4 Pulse Width Modulation channels, pwmXY is pwm channel X 
>>> and pin
>>> Y.
>>
>> So Y is alternative mux? Can we use letters for this as well?
> 
> Ok

Sorry, actually they are not alternative muxes. There are 4 different 
PWM instances. Each PWM instance can handle 'n' different GPIOs (for 
example, that can be connected to LED etc.).

Thanks
Varada

>>>>> +    msm_mux_led1,
>>>>> +    msm_mux_pwm14,
>>>>> +    msm_mux_led2,
>>>>> +    msm_mux_pwm24,
>>>>> +    msm_mux_pwm00,
>>>>> +    msm_mux_blsp4_uart1,
>>>>
>>>> Are uart0 vs uart1 alternative muxes?
>>>
>>> These are two different uarts available at two independent pins.
>>>
>>
>> Ok, then I'm happy with the naming of this :)
>>
>> Thanks,
>> Bjorn
>>
> 
> Thanks
> Varada

-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora 
Forum, a Linux Foundation Collaborative Project

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#1643601

On Mon 15 May 04:24 PDT 2017, Varadarajan Narayanan wrote:

> 
> 
> On 5/15/2017 2:35 PM, Varadarajan Narayanan wrote:
> > On 5/14/2017 9:53 AM, Bjorn Andersson wrote:
> > > On Thu 11 May 03:33 PDT 2017, Varadarajan Narayanan wrote:
> > > 
> > > > On 5/11/2017 4:13 AM, Bjorn Andersson wrote:
> > > > > On Thu 04 May 04:53 PDT 2017, Varadarajan Narayanan wrote:
> > > > > 
> > > [..]
> > > > > > +enum ipq8074_functions {
> > > > > 
> > > > > Please keep these sorted alphabetically.
> > > > 
> > > > Ok
> > > > 
> > > > > > +    msm_mux_gpio,
> > > > > > +    msm_mux_qpic_pad,
> > > > > > +    msm_mux_blsp5_i2c,
> > > > > > +    msm_mux_blsp5_spi,
> > > > > > +    msm_mux_wci20,
> > > > > 
> > > > > What does "20" mean here?
> > > > 
> > > > This is for Wireless Coex Interface. The same functionality can
> > > > be muxed on
> > > > to different GPIOs. WCI2, is the 2nd edition of the WCI standard
> > > > and 0, 1
> > > > are for the muxing to different GPIOs (alternate muxes).
> > > > 
> > > 
> > > In other Qualcomm platforms the alternative muxes are denoted by letters
> > > (a,b,c...). Would you mind picking up this naming scheme, or do you see
> > > any problems with that? (E.g. wci2a in this case)
> > 
> > Ok
> > 
> > > Btw, do you need any additional configuration for selecting alternative
> > > muxing or is that automagical these days?
> > 
> > No additional configuration is needed.
> > 
> > > > > > +    msm_mux_blsp3_spi3,
> > > > > > +    msm_mux_burn0,
> > > > > > +    msm_mux_pcm_zsi0,
> > > > > > +    msm_mux_blsp5_uart,
> > > > > > +    msm_mux_mac12,
> > > > > 
> > > > > What does "12" mean here?
> > > > 
> > > > The SoC has three MAC cores. Each core has two pins for the
> > > > smart antenna
> > > > feature. macXY indicates the function select for MAC no. X and
> > > > smart antenna
> > > > no. Y.
> > > > 
> > > 
> > > Ok
> > > 
> > > > > > +    msm_mux_blsp3_spi0,
> > > > > > +    msm_mux_burn1,
> > > > > > +    msm_mux_mac01,
> > > > > > +    msm_mux_qdss_cti_trig_out_b0,
> > > > > > +    msm_mux_qdss_cti_trig_in_b0,
> > > > > > +    msm_mux_qpic_pad4,
> > > > > 
> > > > > What are qpic_pad and qpic_pad0 through qpic_pad8? Different functions,
> > > > > alternative muxings...?
> > > > 
> > > > This is for the NAND and LCD display. The pins listed are the 9
> > > > data pins.
> > > > 
> > > 
> > > Then you can describe them all as "qpic_pad" (or simply "qpic"?). (It's
> > > possible to reference a partial group in the DTS, if that's necessary)
> > 
> > There are two sets of 9 pins, either of which can go to NAND or LCD.
> > Will rename qpic_pad as qpic_a and qpic_pad[0-8] as qpic_b.
> > Is that ok?
> > 
> > > > > > +    msm_mux_blsp4_uart0,
> > > > > > +    msm_mux_blsp4_i2c0,
> > > > > > +    msm_mux_blsp4_spi0,
> > > > > > +    msm_mux_mac21,
> > > > > > +    msm_mux_qdss_cti_trig_out_b1,
> > > > > > +    msm_mux_qpic_pad5,
> > > > > > +    msm_mux_qdss_cti_trig_in_b1,
> > > > > > +    msm_mux_qpic_pad6,
> > > > > > +    msm_mux_qpic_pad7,
> > > > > > +    msm_mux_cxc0,
> > > > > > +    msm_mux_mac13,
> > > > > > +    msm_mux_qdss_cti_trig_in_a1,
> > > > > > +    msm_mux_qdss_cti_trig_out_a1,
> > > > > > +    msm_mux_wci22,
> > > > > > +    msm_mux_qdss_cti_trig_in_a0,
> > > > > > +    msm_mux_qpic_pad1,
> > > > > > +    msm_mux_qdss_cti_trig_out_a0,
> > > > > > +    msm_mux_qpic_pad2,
> > > > > > +    msm_mux_qpic_pad3,
> > > > > > +    msm_mux_qdss_traceclk_b,
> > > > > > +    msm_mux_qpic_pad0,
> > > > > > +    msm_mux_qdss_tracectl_b,
> > > > > > +    msm_mux_qpic_pad8,
> > > > > > +    msm_mux_pcm_zsi1,
> > > > > > +    msm_mux_qdss_tracedata_b,
> > > > > > +    msm_mux_led0,
> > > > > > +    msm_mux_pwm04,
> > > > > 
> > > > > What does "04" mean here?
> > > > 
> > > > There are 4 Pulse Width Modulation channels, pwmXY is pwm
> > > > channel X and pin
> > > > Y.
> > > 
> > > So Y is alternative mux? Can we use letters for this as well?
> > 
> > Ok
> 
> Sorry, actually they are not alternative muxes. There are 4 different PWM
> instances. Each PWM instance can handle 'n' different GPIOs (for example,
> that can be connected to LED etc.).
> 

So we have 4 PWMs and the output from a single PWM can muxed to drive
the output of 4 pins?

Then skip the last digit and just go pwm0, ... pwm3 and include all four
pins that can be part of each instance. As the pingroup configuration is
per pin in the TLMM it's possible to configure subsets of the pins in a
group.

Regards,
Bjorn

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#1643962

On 5/18/2017 1:17 AM, Bjorn Andersson wrote:
> On Mon 15 May 04:24 PDT 2017, Varadarajan Narayanan wrote:
> 
>>
>>
>> On 5/15/2017 2:35 PM, Varadarajan Narayanan wrote:
>>> On 5/14/2017 9:53 AM, Bjorn Andersson wrote:
>>>> On Thu 11 May 03:33 PDT 2017, Varadarajan Narayanan wrote:
>>>>
>>>>> On 5/11/2017 4:13 AM, Bjorn Andersson wrote:
>>>>>> On Thu 04 May 04:53 PDT 2017, Varadarajan Narayanan wrote:
>>>>>>
>>>> [..]
>>>>>>> +enum ipq8074_functions {
>>>>>>
>>>>>> Please keep these sorted alphabetically.
>>>>>
>>>>> Ok
>>>>>
>>>>>>> +    msm_mux_gpio,
>>>>>>> +    msm_mux_qpic_pad,
>>>>>>> +    msm_mux_blsp5_i2c,
>>>>>>> +    msm_mux_blsp5_spi,
>>>>>>> +    msm_mux_wci20,
>>>>>>
>>>>>> What does "20" mean here?
>>>>>
>>>>> This is for Wireless Coex Interface. The same functionality can
>>>>> be muxed on
>>>>> to different GPIOs. WCI2, is the 2nd edition of the WCI standard
>>>>> and 0, 1
>>>>> are for the muxing to different GPIOs (alternate muxes).
>>>>>
>>>>
>>>> In other Qualcomm platforms the alternative muxes are denoted by letters
>>>> (a,b,c...). Would you mind picking up this naming scheme, or do you see
>>>> any problems with that? (E.g. wci2a in this case)
>>>
>>> Ok
>>>
>>>> Btw, do you need any additional configuration for selecting alternative
>>>> muxing or is that automagical these days?
>>>
>>> No additional configuration is needed.
>>>
>>>>>>> +    msm_mux_blsp3_spi3,
>>>>>>> +    msm_mux_burn0,
>>>>>>> +    msm_mux_pcm_zsi0,
>>>>>>> +    msm_mux_blsp5_uart,
>>>>>>> +    msm_mux_mac12,
>>>>>>
>>>>>> What does "12" mean here?
>>>>>
>>>>> The SoC has three MAC cores. Each core has two pins for the
>>>>> smart antenna
>>>>> feature. macXY indicates the function select for MAC no. X and
>>>>> smart antenna
>>>>> no. Y.
>>>>>
>>>>
>>>> Ok
>>>>
>>>>>>> +    msm_mux_blsp3_spi0,
>>>>>>> +    msm_mux_burn1,
>>>>>>> +    msm_mux_mac01,
>>>>>>> +    msm_mux_qdss_cti_trig_out_b0,
>>>>>>> +    msm_mux_qdss_cti_trig_in_b0,
>>>>>>> +    msm_mux_qpic_pad4,
>>>>>>
>>>>>> What are qpic_pad and qpic_pad0 through qpic_pad8? Different functions,
>>>>>> alternative muxings...?
>>>>>
>>>>> This is for the NAND and LCD display. The pins listed are the 9
>>>>> data pins.
>>>>>
>>>>
>>>> Then you can describe them all as "qpic_pad" (or simply "qpic"?). (It's
>>>> possible to reference a partial group in the DTS, if that's necessary)
>>>
>>> There are two sets of 9 pins, either of which can go to NAND or LCD.
>>> Will rename qpic_pad as qpic_a and qpic_pad[0-8] as qpic_b.
>>> Is that ok?
>>>
>>>>>>> +    msm_mux_blsp4_uart0,
>>>>>>> +    msm_mux_blsp4_i2c0,
>>>>>>> +    msm_mux_blsp4_spi0,
>>>>>>> +    msm_mux_mac21,
>>>>>>> +    msm_mux_qdss_cti_trig_out_b1,
>>>>>>> +    msm_mux_qpic_pad5,
>>>>>>> +    msm_mux_qdss_cti_trig_in_b1,
>>>>>>> +    msm_mux_qpic_pad6,
>>>>>>> +    msm_mux_qpic_pad7,
>>>>>>> +    msm_mux_cxc0,
>>>>>>> +    msm_mux_mac13,
>>>>>>> +    msm_mux_qdss_cti_trig_in_a1,
>>>>>>> +    msm_mux_qdss_cti_trig_out_a1,
>>>>>>> +    msm_mux_wci22,
>>>>>>> +    msm_mux_qdss_cti_trig_in_a0,
>>>>>>> +    msm_mux_qpic_pad1,
>>>>>>> +    msm_mux_qdss_cti_trig_out_a0,
>>>>>>> +    msm_mux_qpic_pad2,
>>>>>>> +    msm_mux_qpic_pad3,
>>>>>>> +    msm_mux_qdss_traceclk_b,
>>>>>>> +    msm_mux_qpic_pad0,
>>>>>>> +    msm_mux_qdss_tracectl_b,
>>>>>>> +    msm_mux_qpic_pad8,
>>>>>>> +    msm_mux_pcm_zsi1,
>>>>>>> +    msm_mux_qdss_tracedata_b,
>>>>>>> +    msm_mux_led0,
>>>>>>> +    msm_mux_pwm04,
>>>>>>
>>>>>> What does "04" mean here?
>>>>>
>>>>> There are 4 Pulse Width Modulation channels, pwmXY is pwm
>>>>> channel X and pin
>>>>> Y.
>>>>
>>>> So Y is alternative mux? Can we use letters for this as well?
>>>
>>> Ok
>>
>> Sorry, actually they are not alternative muxes. There are 4 different PWM
>> instances. Each PWM instance can handle 'n' different GPIOs (for example,
>> that can be connected to LED etc.).
>>
> 
> So we have 4 PWMs and the output from a single PWM can muxed to drive
> the output of 4 pins?
> 
> Then skip the last digit and just go pwm0, ... pwm3 and include all four
> pins that can be part of each instance. As the pingroup configuration is
> per pin in the TLMM it's possible to configure subsets of the pins in a
> group.

Ok

Thanks
Varada

> Regards,
> Bjorn
> 

-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora 
Forum, a Linux Foundation Collaborative Project

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#1643593

On Mon 15 May 02:05 PDT 2017, Varadarajan Narayanan wrote:

> On 5/14/2017 9:53 AM, Bjorn Andersson wrote:
> > On Thu 11 May 03:33 PDT 2017, Varadarajan Narayanan wrote:
> > 
> > > On 5/11/2017 4:13 AM, Bjorn Andersson wrote:
> > > > On Thu 04 May 04:53 PDT 2017, Varadarajan Narayanan wrote:
[..]
> > > > > +	msm_mux_qpic_pad4,
> > > > 
> > > > What are qpic_pad and qpic_pad0 through qpic_pad8? Different functions,
> > > > alternative muxings...?
> > > 
> > > This is for the NAND and LCD display. The pins listed are the 9 data pins.
> > > 
> > 
> > Then you can describe them all as "qpic_pad" (or simply "qpic"?). (It's
> > possible to reference a partial group in the DTS, if that's necessary)
> 
> There are two sets of 9 pins, either of which can go to NAND or LCD.
> Will rename qpic_pad as qpic_a and qpic_pad[0-8] as qpic_b.
> Is that ok?
> 

So you have NAND and LCD hardware muxed to either "a" or "b" and then
you mux either "a" or "b" out onto actual pins?

How is this first mux configured?


I think the a/b scheme sounds reasonable, if above is how it works.

Regards,
Bjorn

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#1643956

On 5/18/2017 1:03 AM, Bjorn Andersson wrote:
> On Mon 15 May 02:05 PDT 2017, Varadarajan Narayanan wrote:
> 
>> On 5/14/2017 9:53 AM, Bjorn Andersson wrote:
>>> On Thu 11 May 03:33 PDT 2017, Varadarajan Narayanan wrote:
>>>
>>>> On 5/11/2017 4:13 AM, Bjorn Andersson wrote:
>>>>> On Thu 04 May 04:53 PDT 2017, Varadarajan Narayanan wrote:
> [..]
>>>>>> +	msm_mux_qpic_pad4,
>>>>>
>>>>> What are qpic_pad and qpic_pad0 through qpic_pad8? Different functions,
>>>>> alternative muxings...?
>>>>
>>>> This is for the NAND and LCD display. The pins listed are the 9 data pins.
>>>>
>>>
>>> Then you can describe them all as "qpic_pad" (or simply "qpic"?). (It's
>>> possible to reference a partial group in the DTS, if that's necessary)
>>
>> There are two sets of 9 pins, either of which can go to NAND or LCD.
>> Will rename qpic_pad as qpic_a and qpic_pad[0-8] as qpic_b.
>> Is that ok?
>>
> 
> So you have NAND and LCD hardware muxed to either "a" or "b" and then
> you mux either "a" or "b" out onto actual pins?
> 
> How is this first mux configured?
> 
> I think the a/b scheme sounds reasonable, if above is how it works.

Sorry, I was wrong. I had misread the documentation.

There are 18 pins. 15 pins are common between LCD and NAND. The QPIC 
controller arbitrates between LCD and NAND. Of the remaining 4, 2 are 
for NAND and 2 are for LCD exclusively. We plan to group the qpic pins 
into 3 groups namely, qpic_common, qpic_nand and qpic_lcd. Is that ok?

Thanks
Varada

> 
> Regards,
> Bjorn
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> 

-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora 
Forum, a Linux Foundation Collaborative Project

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#1646056

On Thu 18 May 01:39 PDT 2017, Varadarajan Narayanan wrote:

> 
> 
> On 5/18/2017 1:03 AM, Bjorn Andersson wrote:
> > On Mon 15 May 02:05 PDT 2017, Varadarajan Narayanan wrote:
> > 
> > > On 5/14/2017 9:53 AM, Bjorn Andersson wrote:
> > > > On Thu 11 May 03:33 PDT 2017, Varadarajan Narayanan wrote:
> > > > 
> > > > > On 5/11/2017 4:13 AM, Bjorn Andersson wrote:
> > > > > > On Thu 04 May 04:53 PDT 2017, Varadarajan Narayanan wrote:
> > [..]
> > > > > > > +	msm_mux_qpic_pad4,
> > > > > > 
> > > > > > What are qpic_pad and qpic_pad0 through qpic_pad8? Different functions,
> > > > > > alternative muxings...?
> > > > > 
> > > > > This is for the NAND and LCD display. The pins listed are the 9 data pins.
> > > > > 
> > > > 
> > > > Then you can describe them all as "qpic_pad" (or simply "qpic"?). (It's
> > > > possible to reference a partial group in the DTS, if that's necessary)
> > > 
> > > There are two sets of 9 pins, either of which can go to NAND or LCD.
> > > Will rename qpic_pad as qpic_a and qpic_pad[0-8] as qpic_b.
> > > Is that ok?
> > > 
> > 
> > So you have NAND and LCD hardware muxed to either "a" or "b" and then
> > you mux either "a" or "b" out onto actual pins?
> > 
> > How is this first mux configured?
> > 
> > I think the a/b scheme sounds reasonable, if above is how it works.
> 
> Sorry, I was wrong. I had misread the documentation.
> 
> There are 18 pins. 15 pins are common between LCD and NAND. The QPIC
> controller arbitrates between LCD and NAND. Of the remaining 4, 2 are for
> NAND and 2 are for LCD exclusively. We plan to group the qpic pins into 3
> groups namely, qpic_common, qpic_nand and qpic_lcd. Is that ok?
> 

If you consider that you are defining the available functions for this
pinmuxer and then define the sets of pins exposing these available
functions it does make sense to just name it "qpic".

I think that naming them _common, _lcd and _nand is just adding
confusion when it comes to writing the dts files.


@Linus, do you have a different preference here?

Regards,
Bjorn

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#1647875

On Sat, May 20, 2017 at 7:54 AM, Bjorn Andersson
<bjorn.andersson@linaro.org> wrote:
> On Thu 18 May 01:39 PDT 2017, Varadarajan Narayanan wrote:

>> There are 18 pins. 15 pins are common between LCD and NAND. The QPIC
>> controller arbitrates between LCD and NAND. Of the remaining 4, 2 are for
>> NAND and 2 are for LCD exclusively. We plan to group the qpic pins into 3
>> groups namely, qpic_common, qpic_nand and qpic_lcd. Is that ok?
>>
>
> If you consider that you are defining the available functions for this
> pinmuxer and then define the sets of pins exposing these available
> functions it does make sense to just name it "qpic".
>
> I think that naming them _common, _lcd and _nand is just adding
> confusion when it comes to writing the dts files.
>
> @Linus, do you have a different preference here?

No I pretty much trust the driver maintainer to know this best.

Yours,
Linus Walleij

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