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Groups > linux.kernel > #1635750 > unrolled thread
| Started by | Icenowy Zheng <icenowy@aosc.io> |
|---|---|
| First post | 2017-05-04 16:00 +0200 |
| Last post | 2017-05-11 16:50 +0200 |
| Articles | 16 — 4 participants |
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[PATCH v2 00/10] Initial Allwinner R40 support Icenowy Zheng <icenowy@aosc.io> - 2017-05-04 16:00 +0200
Re: [PATCH v2 03/10] pinctrl: sunxi: add A20 support to A10 driver Maxime Ripard <maxime.ripard@free-electrons.com> - 2017-05-04 16:10 +0200
Re: [PATCH v2 03/10] pinctrl: sunxi: add A20 support to A10 driver Icenowy Zheng <icenowy@aosc.io> - 2017-05-04 16:10 +0200
Re: [PATCH v2 03/10] pinctrl: sunxi: add A20 support to A10 driver Icenowy Zheng <icenowy@aosc.io> - 2017-05-04 16:50 +0200
Re: [PATCH v2 03/10] pinctrl: sunxi: add A20 support to A10 driver Maxime Ripard <maxime.ripard@free-electrons.com> - 2017-05-05 21:50 +0200
Re: [PATCH v2 03/10] pinctrl: sunxi: add A20 support to A10 driver Maxime Ripard <maxime.ripard@free-electrons.com> - 2017-05-04 16:50 +0200
[PATCH v2 07/10] dt-bindings: add compatible string for Allwinner R40 CCU Icenowy Zheng <icenowy@aosc.io> - 2017-05-04 16:20 +0200
Re: [PATCH v2 07/10] dt-bindings: add compatible string for Allwinner R40 CCU Rob Herring <robh@kernel.org> - 2017-05-08 18:50 +0200
[PATCH v2 06/10] pinctrl: sunxi: add support of R40 to A10 pinctrl driver Icenowy Zheng <icenowy@aosc.io> - 2017-05-04 16:20 +0200
[PATCH v2 03/10] pinctrl: sunxi: add A20 support to A10 driver Icenowy Zheng <icenowy@aosc.io> - 2017-05-04 16:20 +0200
[PATCH v2 05/10] dt-bindings: add compatible string for Allwinner R40 pinctrl Icenowy Zheng <icenowy@aosc.io> - 2017-05-04 16:20 +0200
Re: [PATCH v2 05/10] dt-bindings: add compatible string for Allwinner R40 pinctrl Rob Herring <robh@kernel.org> - 2017-05-08 18:50 +0200
Re: [PATCH v2 08/10] clk: sunxi-ng: support R40 SoC Maxime Ripard <maxime.ripard@free-electrons.com> - 2017-05-04 16:30 +0200
Re: [PATCH v2 09/10] ARM: dts: sun8i: Add basic dtsi file for Allwinner R40 Maxime Ripard <maxime.ripard@free-electrons.com> - 2017-05-04 16:40 +0200
[PATCH v2 09/10] ARM: dts: sun8i: Add basic dtsi file for Allwinner R40 Icenowy Zheng <icenowy@aosc.io> - 2017-05-04 17:30 +0200
Re: [PATCH v2 04/10] pinctrl: sunxi: switch A20's pinctrl driver to use the A10 version Linus Walleij <linus.walleij@linaro.org> - 2017-05-11 16:50 +0200
| From | Icenowy Zheng <icenowy@aosc.io> |
|---|---|
| Date | 2017-05-04 16:00 +0200 |
| Subject | [PATCH v2 00/10] Initial Allwinner R40 support |
| Message-ID | <tDpsu-4bq-9@gated-at.bofh.it> |
This is the first non-RFC version of this patchset, which added basical
support including I2C, UART and MMC to the mainline Linux.
The pinctrl driver of A20 is also merged into the one of A10 before
R40 support is added into the A10 driver.
Chen-Yu Tsai (2):
ARM: dts: sun8i: Add basic dtsi file for Allwinner R40
ARM: dts: sun8i: Add board dts file for Banana Pi M2 Ultra
Icenowy Zheng (8):
arm: sunxi: add support for R40 SoC
pinctrl: sunxi: add definitions for add A20 and R40 support to A10
driver
pinctrl: sunxi: add A20 support to A10 driver
pinctrl: sunxi: switch A20's pinctrl driver to use the A10 version
dt-bindings: add compatible string for Allwinner R40 pinctrl
pinctrl: sunxi: add support of R40 to A10 pinctrl driver
dt-bindings: add compatible string for Allwinner R40 CCU
clk: sunxi-ng: support R40 SoC
Documentation/arm/sunxi/README | 4 +
Documentation/devicetree/bindings/arm/sunxi.txt | 1 +
.../devicetree/bindings/clock/sunxi-ccu.txt | 1 +
.../bindings/pinctrl/allwinner,sunxi-pinctrl.txt | 1 +
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts | 161 +++
arch/arm/boot/dts/sun8i-r40.dtsi | 404 +++++++
arch/arm/mach-sunxi/sunxi.c | 1 +
drivers/clk/sunxi-ng/Kconfig | 10 +
drivers/clk/sunxi-ng/Makefile | 1 +
drivers/clk/sunxi-ng/ccu-sun8i-r40.c | 1153 ++++++++++++++++++++
drivers/clk/sunxi-ng/ccu-sun8i-r40.h | 68 ++
drivers/pinctrl/sunxi/Kconfig | 6 +-
drivers/pinctrl/sunxi/Makefile | 1 -
drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c | 449 ++++++--
drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c | 1056 ------------------
drivers/pinctrl/sunxi/pinctrl-sunxi.h | 3 +
include/dt-bindings/clock/sun8i-r40-ccu.h | 191 ++++
include/dt-bindings/reset/sun8i-r40-ccu.h | 129 +++
19 files changed, 2495 insertions(+), 1146 deletions(-)
create mode 100644 arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
create mode 100644 arch/arm/boot/dts/sun8i-r40.dtsi
create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-r40.c
create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-r40.h
delete mode 100644 drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c
create mode 100644 include/dt-bindings/clock/sun8i-r40-ccu.h
create mode 100644 include/dt-bindings/reset/sun8i-r40-ccu.h
--
2.12.2
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| From | Maxime Ripard <maxime.ripard@free-electrons.com> |
|---|---|
| Date | 2017-05-04 16:10 +0200 |
| Subject | Re: [PATCH v2 03/10] pinctrl: sunxi: add A20 support to A10 driver |
| Message-ID | <tDpC9-4uB-1@gated-at.bofh.it> |
| In reply to | #1635750 |
[Multipart message — attachments visible in raw view] — view raw
On Thu, May 04, 2017 at 09:49:59PM +0800, Icenowy Zheng wrote:
> static const struct of_device_id sun4i_a10_pinctrl_match[] = {
> - { .compatible = "allwinner,sun4i-a10-pinctrl", },
> + {
> + .compatible = "allwinner,sun4i-a10-pinctrl",
> + .data = (void *)PINCTRL_SUN4I_A10
> + },
> + {
> + .compatible = "allwinner,sun7i-a20-pinctrl",
> + .data = (void *)PINCTRL_SUN7I_A20
> + },
> {}
> };
This means you're going to have two drivers probing for the same
device: this driver, and the old one. This is not ok, and probably
introduces some corner cases.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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| From | Icenowy Zheng <icenowy@aosc.io> |
|---|---|
| Date | 2017-05-04 16:10 +0200 |
| Subject | Re: [PATCH v2 03/10] pinctrl: sunxi: add A20 support to A10 driver |
| Message-ID | <tDpCa-4uB-33@gated-at.bofh.it> |
| In reply to | #1635751 |
于 2017年5月4日 GMT+08:00 下午10:02:20, Maxime Ripard <maxime.ripard@free-electrons.com> 写到:
>On Thu, May 04, 2017 at 09:49:59PM +0800, Icenowy Zheng wrote:
>> static const struct of_device_id sun4i_a10_pinctrl_match[] = {
>> - { .compatible = "allwinner,sun4i-a10-pinctrl", },
>> + {
>> + .compatible = "allwinner,sun4i-a10-pinctrl",
>> + .data = (void *)PINCTRL_SUN4I_A10
>> + },
>> + {
>> + .compatible = "allwinner,sun7i-a20-pinctrl",
>> + .data = (void *)PINCTRL_SUN7I_A20
>> + },
>> {}
>> };
>
>This means you're going to have two drivers probing for the same
>device: this driver, and the old one. This is not ok, and probably
>introduces some corner cases.
The A20 driver is dropped in the next commit.
>
>Maxime
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| From | Icenowy Zheng <icenowy@aosc.io> |
|---|---|
| Date | 2017-05-04 16:50 +0200 |
| Subject | Re: [PATCH v2 03/10] pinctrl: sunxi: add A20 support to A10 driver |
| Message-ID | <tDqeR-4Lv-3@gated-at.bofh.it> |
| In reply to | #1635759 |
于 2017年5月4日 GMT+08:00 下午10:41:52, Maxime Ripard <maxime.ripard@free-electrons.com> 写到:
>On Thu, May 04, 2017 at 10:03:26PM +0800, Icenowy Zheng wrote:
>>
>>
>> 于 2017年5月4日 GMT+08:00 下午10:02:20, Maxime Ripard
><maxime.ripard@free-electrons.com> 写到:
>> >On Thu, May 04, 2017 at 09:49:59PM +0800, Icenowy Zheng wrote:
>> >> static const struct of_device_id sun4i_a10_pinctrl_match[] = {
>> >> - { .compatible = "allwinner,sun4i-a10-pinctrl", },
>> >> + {
>> >> + .compatible = "allwinner,sun4i-a10-pinctrl",
>> >> + .data = (void *)PINCTRL_SUN4I_A10
>> >> + },
>> >> + {
>> >> + .compatible = "allwinner,sun7i-a20-pinctrl",
>> >> + .data = (void *)PINCTRL_SUN7I_A20
>> >> + },
>> >> {}
>> >> };
>> >
>> >This means you're going to have two drivers probing for the same
>> >device: this driver, and the old one. This is not ok, and probably
>> >introduces some corner cases.
>>
>> The A20 driver is dropped in the next commit.
>
>Yes, and that is an issue for bisectability. Anyone that will checkout
>between those two commits will have a broken kernel, and that is not
>ok. Any commit should be in a working state.
Squash them together?
>
>Maxime
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| From | Maxime Ripard <maxime.ripard@free-electrons.com> |
|---|---|
| Date | 2017-05-05 21:50 +0200 |
| Subject | Re: [PATCH v2 03/10] pinctrl: sunxi: add A20 support to A10 driver |
| Message-ID | <tDRoJ-69K-3@gated-at.bofh.it> |
| In reply to | #1635804 |
[Multipart message — attachments visible in raw view] — view raw
On Thu, May 04, 2017 at 10:45:11PM +0800, Icenowy Zheng wrote:
>
>
> 于 2017年5月4日 GMT+08:00 下午10:41:52, Maxime Ripard <maxime.ripard@free-electrons.com> 写到:
> >On Thu, May 04, 2017 at 10:03:26PM +0800, Icenowy Zheng wrote:
> >>
> >>
> >> 于 2017年5月4日 GMT+08:00 下午10:02:20, Maxime Ripard
> ><maxime.ripard@free-electrons.com> 写到:
> >> >On Thu, May 04, 2017 at 09:49:59PM +0800, Icenowy Zheng wrote:
> >> >> static const struct of_device_id sun4i_a10_pinctrl_match[] = {
> >> >> - { .compatible = "allwinner,sun4i-a10-pinctrl", },
> >> >> + {
> >> >> + .compatible = "allwinner,sun4i-a10-pinctrl",
> >> >> + .data = (void *)PINCTRL_SUN4I_A10
> >> >> + },
> >> >> + {
> >> >> + .compatible = "allwinner,sun7i-a20-pinctrl",
> >> >> + .data = (void *)PINCTRL_SUN7I_A20
> >> >> + },
> >> >> {}
> >> >> };
> >> >
> >> >This means you're going to have two drivers probing for the same
> >> >device: this driver, and the old one. This is not ok, and probably
> >> >introduces some corner cases.
> >>
> >> The A20 driver is dropped in the next commit.
> >
> >Yes, and that is an issue for bisectability. Anyone that will checkout
> >between those two commits will have a broken kernel, and that is not
> >ok. Any commit should be in a working state.
>
> Squash them together?
I would simply remove the A20's def_bool in that patch.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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| From | Maxime Ripard <maxime.ripard@free-electrons.com> |
|---|---|
| Date | 2017-05-04 16:50 +0200 |
| Subject | Re: [PATCH v2 03/10] pinctrl: sunxi: add A20 support to A10 driver |
| Message-ID | <tDqeR-4Lv-5@gated-at.bofh.it> |
| In reply to | #1635759 |
[Multipart message — attachments visible in raw view] — view raw
On Thu, May 04, 2017 at 10:03:26PM +0800, Icenowy Zheng wrote:
>
>
> 于 2017年5月4日 GMT+08:00 下午10:02:20, Maxime Ripard <maxime.ripard@free-electrons.com> 写到:
> >On Thu, May 04, 2017 at 09:49:59PM +0800, Icenowy Zheng wrote:
> >> static const struct of_device_id sun4i_a10_pinctrl_match[] = {
> >> - { .compatible = "allwinner,sun4i-a10-pinctrl", },
> >> + {
> >> + .compatible = "allwinner,sun4i-a10-pinctrl",
> >> + .data = (void *)PINCTRL_SUN4I_A10
> >> + },
> >> + {
> >> + .compatible = "allwinner,sun7i-a20-pinctrl",
> >> + .data = (void *)PINCTRL_SUN7I_A20
> >> + },
> >> {}
> >> };
> >
> >This means you're going to have two drivers probing for the same
> >device: this driver, and the old one. This is not ok, and probably
> >introduces some corner cases.
>
> The A20 driver is dropped in the next commit.
Yes, and that is an issue for bisectability. Anyone that will checkout
between those two commits will have a broken kernel, and that is not
ok. Any commit should be in a working state.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
[toc] | [prev] | [next] | [standalone]
| From | Icenowy Zheng <icenowy@aosc.io> |
|---|---|
| Date | 2017-05-04 16:20 +0200 |
| Subject | [PATCH v2 07/10] dt-bindings: add compatible string for Allwinner R40 CCU |
| Message-ID | <tDpLQ-4yP-13@gated-at.bofh.it> |
| In reply to | #1635750 |
Allwinner R40 has a clock controlling unit like the ones on other Allwinner SoCs after sun6i, and can also use a CCU-based driver. Add a compatible string for it. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> --- Documentation/devicetree/bindings/clock/sunxi-ccu.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt index e9c5a1d9834a..b2ae26428423 100644 --- a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt +++ b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt @@ -8,6 +8,7 @@ Required properties : - "allwinner,sun8i-a33-ccu" - "allwinner,sun8i-h3-ccu" - "allwinner,sun8i-h3-r-ccu" + - "allwinner,sun8i-r40-ccu" - "allwinner,sun8i-v3s-ccu" - "allwinner,sun9i-a80-ccu" - "allwinner,sun50i-a64-ccu" -- 2.12.2
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| From | Rob Herring <robh@kernel.org> |
|---|---|
| Date | 2017-05-08 18:50 +0200 |
| Subject | Re: [PATCH v2 07/10] dt-bindings: add compatible string for Allwinner R40 CCU |
| Message-ID | <tEU1b-6nV-1@gated-at.bofh.it> |
| In reply to | #1635767 |
On Thu, May 04, 2017 at 09:50:03PM +0800, Icenowy Zheng wrote: > Allwinner R40 has a clock controlling unit like the ones on other > Allwinner SoCs after sun6i, and can also use a CCU-based driver. > > Add a compatible string for it. > > Signed-off-by: Icenowy Zheng <icenowy@aosc.io> > --- > Documentation/devicetree/bindings/clock/sunxi-ccu.txt | 1 + > 1 file changed, 1 insertion(+) Acked-by: Rob Herring <robh@kernel.org>
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| From | Icenowy Zheng <icenowy@aosc.io> |
|---|---|
| Date | 2017-05-04 16:20 +0200 |
| Subject | [PATCH v2 06/10] pinctrl: sunxi: add support of R40 to A10 pinctrl driver |
| Message-ID | <tDpLQ-4yP-19@gated-at.bofh.it> |
| In reply to | #1635750 |
R40 is said to be an upgrade of A20, and its pin configuration is also
similar to A20 (and thus similar to A10).
Add support for R40 to the A10 pinctrl driver.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
drivers/pinctrl/sunxi/Kconfig | 2 +-
drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c | 272 +++++++++++++++++++++---------
2 files changed, 197 insertions(+), 77 deletions(-)
diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig
index 624d84e6c936..9d01da3b90bd 100644
--- a/drivers/pinctrl/sunxi/Kconfig
+++ b/drivers/pinctrl/sunxi/Kconfig
@@ -7,7 +7,7 @@ config PINCTRL_SUNXI
select GPIOLIB
config PINCTRL_SUN4I_A10
- def_bool MACH_SUN4I || MACH_SUN7I
+ def_bool MACH_SUN4I || MACH_SUN7I || MACH_SUN8I
select PINCTRL_SUNXI
config PINCTRL_SUN5I
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c b/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c
index 159580c04b14..0f6ca8391ea7 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c
@@ -26,7 +26,8 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION(0x3, "spi1"), /* CS0 */
SUNXI_FUNCTION(0x4, "uart2"), /* RTS */
SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* GRXD3 */
- PINCTRL_SUN7I_A20)),
+ PINCTRL_SUN7I_A20 |
+ PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
@@ -34,7 +35,8 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION(0x3, "spi1"), /* CLK */
SUNXI_FUNCTION(0x4, "uart2"), /* CTS */
SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* GRXD2 */
- PINCTRL_SUN7I_A20)),
+ PINCTRL_SUN7I_A20 |
+ PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
@@ -42,7 +44,8 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION(0x3, "spi1"), /* MOSI */
SUNXI_FUNCTION(0x4, "uart2"), /* TX */
SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* GRXD1 */
- PINCTRL_SUN7I_A20)),
+ PINCTRL_SUN7I_A20 |
+ PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
@@ -50,65 +53,75 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION(0x3, "spi1"), /* MISO */
SUNXI_FUNCTION(0x4, "uart2"), /* RX */
SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* GRXD0 */
- PINCTRL_SUN7I_A20)),
+ PINCTRL_SUN7I_A20 |
+ PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac"), /* ETXD3 */
SUNXI_FUNCTION(0x3, "spi1"), /* CS1 */
SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* GTXD3 */
- PINCTRL_SUN7I_A20)),
+ PINCTRL_SUN7I_A20 |
+ PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac"), /* ETXD2 */
SUNXI_FUNCTION(0x3, "spi3"), /* CS0 */
SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* GTXD2 */
- PINCTRL_SUN7I_A20)),
+ PINCTRL_SUN7I_A20 |
+ PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac"), /* ETXD1 */
SUNXI_FUNCTION(0x3, "spi3"), /* CLK */
SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* GTXD1 */
- PINCTRL_SUN7I_A20)),
+ PINCTRL_SUN7I_A20 |
+ PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac"), /* ETXD0 */
SUNXI_FUNCTION(0x3, "spi3"), /* MOSI */
SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* GTXD0 */
- PINCTRL_SUN7I_A20)),
+ PINCTRL_SUN7I_A20 |
+ PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 8),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac"), /* ERXCK */
SUNXI_FUNCTION(0x3, "spi3"), /* MISO */
SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* GRXCK */
- PINCTRL_SUN7I_A20)),
+ PINCTRL_SUN7I_A20 |
+ PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac"), /* ERXERR */
SUNXI_FUNCTION(0x3, "spi3"), /* CS1 */
SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* GNULL / ERXERR */
- PINCTRL_SUN7I_A20),
+ PINCTRL_SUN7I_A20 |
+ PINCTRL_SUN8I_R40),
SUNXI_FUNCTION_VARIANT(0x6, "i2s1", /* MCLK */
- PINCTRL_SUN7I_A20)),
+ PINCTRL_SUN7I_A20 |
+ PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 10),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac"), /* ERXDV */
SUNXI_FUNCTION(0x4, "uart1"), /* TX */
SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* GRXDV */
- PINCTRL_SUN7I_A20)),
+ PINCTRL_SUN7I_A20 |
+ PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 11),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac"), /* EMDC */
SUNXI_FUNCTION(0x4, "uart1"), /* RX */
SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* EMDC */
- PINCTRL_SUN7I_A20)),
+ PINCTRL_SUN7I_A20 |
+ PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 12),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
@@ -116,7 +129,8 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION(0x3, "uart6"), /* TX */
SUNXI_FUNCTION(0x4, "uart1"), /* RTS */
SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* EMDIO */
- PINCTRL_SUN7I_A20)),
+ PINCTRL_SUN7I_A20 |
+ PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 13),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
@@ -124,7 +138,8 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION(0x3, "uart6"), /* RX */
SUNXI_FUNCTION(0x4, "uart1"), /* CTS */
SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* GTXCTL / ETXEN */
- PINCTRL_SUN7I_A20)),
+ PINCTRL_SUN7I_A20 |
+ PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 14),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
@@ -132,9 +147,11 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION(0x3, "uart7"), /* TX */
SUNXI_FUNCTION(0x4, "uart1"), /* DTR */
SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* GNULL / ETXCK */
- PINCTRL_SUN7I_A20),
+ PINCTRL_SUN7I_A20 |
+ PINCTRL_SUN8I_R40),
SUNXI_FUNCTION_VARIANT(0x6, "i2s1", /* BCLK */
- PINCTRL_SUN7I_A20)),
+ PINCTRL_SUN7I_A20 |
+ PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 15),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
@@ -142,9 +159,11 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION(0x3, "uart7"), /* RX */
SUNXI_FUNCTION(0x4, "uart1"), /* DSR */
SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* GTXCK / ECRS */
- PINCTRL_SUN7I_A20),
+ PINCTRL_SUN7I_A20 |
+ PINCTRL_SUN8I_R40),
SUNXI_FUNCTION_VARIANT(0x6, "i2s1", /* LRCK */
- PINCTRL_SUN7I_A20)),
+ PINCTRL_SUN7I_A20 |
+ PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 16),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
@@ -152,9 +171,11 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION(0x3, "can"), /* TX */
SUNXI_FUNCTION(0x4, "uart1"), /* DCD */
SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* GCLKIN / ECOL */
- PINCTRL_SUN7I_A20),
+ PINCTRL_SUN7I_A20 |
+ PINCTRL_SUN8I_R40),
SUNXI_FUNCTION_VARIANT(0x6, "i2s1", /* DO */
- PINCTRL_SUN7I_A20)),
+ PINCTRL_SUN7I_A20 |
+ PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 17),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
@@ -162,14 +183,19 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION(0x3, "can"), /* RX */
SUNXI_FUNCTION(0x4, "uart1"), /* RING */
SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* GNULL / ETXERR */
- PINCTRL_SUN7I_A20),
+ PINCTRL_SUN7I_A20 |
+ PINCTRL_SUN8I_R40),
SUNXI_FUNCTION_VARIANT(0x6, "i2s1", /* DI */
- PINCTRL_SUN7I_A20)),
+ PINCTRL_SUN7I_A20 |
+ PINCTRL_SUN8I_R40)),
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
- SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */
+ SUNXI_FUNCTION(0x2, "i2c0"), /* SCK */
+ SUNXI_FUNCTION_VARIANT(0x3,
+ "pll-lock-dbg",
+ PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
@@ -177,11 +203,19 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
- SUNXI_FUNCTION(0x2, "pwm")), /* PWM0 */
+ SUNXI_FUNCTION_VARIANT(0x2, "pwm", /* PWM0 */
+ PINCTRL_SUN4I_A10 |
+ PINCTRL_SUN7I_A20),
+ SUNXI_FUNCTION_VARIANT(0x3, "pwm", /* PWM0 */
+ PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
- SUNXI_FUNCTION(0x2, "ir0"), /* TX */
+ SUNXI_FUNCTION_VARIANT(0x2, "ir0", /* TX */
+ PINCTRL_SUN4I_A10 |
+ PINCTRL_SUN7I_A20),
+ SUNXI_FUNCTION_VARIANT(0x3, "pwm0", /* PWM1 */
+ PINCTRL_SUN8I_R40),
/*
* The SPDIF block is not referenced at all in the A10 user
* manual. However it is described in the code leaked and the
@@ -205,7 +239,8 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION_VARIANT(0x2, "i2s", /* MCLK */
PINCTRL_SUN4I_A10),
SUNXI_FUNCTION_VARIANT(0x2, "i2s0", /* MCLK */
- PINCTRL_SUN7I_A20),
+ PINCTRL_SUN7I_A20 |
+ PINCTRL_SUN8I_R40),
SUNXI_FUNCTION(0x3, "ac97")), /* MCLK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
@@ -213,7 +248,8 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION_VARIANT(0x2, "i2s", /* BCLK */
PINCTRL_SUN4I_A10),
SUNXI_FUNCTION_VARIANT(0x2, "i2s0", /* BCLK */
- PINCTRL_SUN7I_A20),
+ PINCTRL_SUN7I_A20 |
+ PINCTRL_SUN8I_R40),
SUNXI_FUNCTION(0x3, "ac97")), /* BCLK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
@@ -221,7 +257,8 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION_VARIANT(0x2, "i2s", /* LRCK */
PINCTRL_SUN4I_A10),
SUNXI_FUNCTION_VARIANT(0x2, "i2s0", /* LRCK */
- PINCTRL_SUN7I_A20),
+ PINCTRL_SUN7I_A20 |
+ PINCTRL_SUN8I_R40),
SUNXI_FUNCTION(0x3, "ac97")), /* SYNC */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 8),
SUNXI_FUNCTION(0x0, "gpio_in"),
@@ -229,7 +266,8 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION_VARIANT(0x2, "i2s", /* DO0 */
PINCTRL_SUN4I_A10),
SUNXI_FUNCTION_VARIANT(0x2, "i2s0", /* DO0 */
- PINCTRL_SUN7I_A20),
+ PINCTRL_SUN7I_A20 |
+ PINCTRL_SUN8I_R40),
SUNXI_FUNCTION(0x3, "ac97")), /* DO */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
@@ -237,31 +275,41 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION_VARIANT(0x2, "i2s", /* DO1 */
PINCTRL_SUN4I_A10),
SUNXI_FUNCTION_VARIANT(0x2, "i2s0", /* DO1 */
- PINCTRL_SUN7I_A20)),
+ PINCTRL_SUN7I_A20 |
+ PINCTRL_SUN8I_R40),
+ SUNXI_FUNCTION_VARIANT(0x4, "pwm", /* PWM6 */
+ PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 10),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION_VARIANT(0x2, "i2s", /* DO2 */
PINCTRL_SUN4I_A10),
SUNXI_FUNCTION_VARIANT(0x2, "i2s0", /* DO2 */
- PINCTRL_SUN7I_A20)),
+ PINCTRL_SUN7I_A20 |
+ PINCTRL_SUN8I_R40),
+ SUNXI_FUNCTION_VARIANT(0x4, "pwm", /* PWM7 */
+ PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 11),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION_VARIANT(0x2, "i2s", /* DO3 */
PINCTRL_SUN4I_A10),
SUNXI_FUNCTION_VARIANT(0x2, "i2s0", /* DO3 */
- PINCTRL_SUN7I_A20)),
+ PINCTRL_SUN7I_A20 |
+ PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 12),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION_VARIANT(0x2, "i2s", /* DI */
PINCTRL_SUN4I_A10),
SUNXI_FUNCTION_VARIANT(0x2, "i2s0", /* DI */
- PINCTRL_SUN7I_A20),
+ PINCTRL_SUN7I_A20 |
+ PINCTRL_SUN8I_R40),
SUNXI_FUNCTION(0x3, "ac97"), /* DI */
/* Undocumented mux function on A10 - See SPDIF MCLK above */
- SUNXI_FUNCTION(0x4, "spdif")), /* SPDIF IN */
+ SUNXI_FUNCTION_VARIANT(0x4, "spdif", /* SPDIF IN */
+ PINCTRL_SUN4I_A10 |
+ PINCTRL_SUN7I_A20)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 13),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
@@ -308,7 +356,9 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart0"), /* TX */
- SUNXI_FUNCTION(0x3, "ir1")), /* TX */
+ SUNXI_FUNCTION_VARIANT(0x3, "ir1", /* TX */
+ PINCTRL_SUN4I_A10 |
+ PINCTRL_SUN7I_A20)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 23),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
@@ -341,7 +391,9 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
- SUNXI_FUNCTION(0x2, "nand0")), /* NRE# */
+ SUNXI_FUNCTION(0x2, "nand0"), /* NRE# */
+ SUNXI_FUNCTION_VARIANT(0x3, "mmc2", /* DS */
+ PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
@@ -375,19 +427,27 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
- SUNXI_FUNCTION(0x2, "nand0")), /* NDQ4 */
+ SUNXI_FUNCTION(0x2, "nand0"), /* NDQ4 */
+ SUNXI_FUNCTION_VARIANT(0x3, "mmc2", /* D4 */
+ PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
- SUNXI_FUNCTION(0x2, "nand0")), /* NDQ5 */
+ SUNXI_FUNCTION(0x2, "nand0"), /* NDQ5 */
+ SUNXI_FUNCTION_VARIANT(0x3, "mmc2", /* D5 */
+ PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
- SUNXI_FUNCTION(0x2, "nand0")), /* NDQ6 */
+ SUNXI_FUNCTION(0x2, "nand0"), /* NDQ6 */
+ SUNXI_FUNCTION_VARIANT(0x3, "mmc2", /* D6 */
+ PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
- SUNXI_FUNCTION(0x2, "nand0")), /* NDQ7 */
+ SUNXI_FUNCTION(0x2, "nand0"), /* NDQ7 */
+ SUNXI_FUNCTION_VARIANT(0x3, "mmc2", /* D7 */
+ PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
@@ -427,7 +487,9 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 24),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
- SUNXI_FUNCTION(0x2, "nand0")), /* NDQS */
+ SUNXI_FUNCTION(0x2, "nand0"), /* NDQS */
+ SUNXI_FUNCTION_VARIANT(0x3, "mmc2", /* RST */
+ PINCTRL_SUN8I_R40)),
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
@@ -728,14 +790,18 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION(0x2, "ts1"), /* D5 */
SUNXI_FUNCTION(0x3, "csi1"), /* D5 */
SUNXI_FUNCTION(0x4, "uart3"), /* CTS */
- SUNXI_FUNCTION(0x5, "csi0")), /* D13 */
+ SUNXI_FUNCTION(0x5, "csi0"), /* D13 */
+ SUNXI_FUNCTION_VARIANT(0x6, "bist", /* RESULT0 */
+ PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "ts1"), /* D6 */
SUNXI_FUNCTION(0x3, "csi1"), /* D6 */
SUNXI_FUNCTION(0x4, "uart4"), /* TX */
- SUNXI_FUNCTION(0x5, "csi0")), /* D14 */
+ SUNXI_FUNCTION(0x5, "csi0"), /* D14 */
+ SUNXI_FUNCTION_VARIANT(0x6, "bist", /* RESULT1 */
+ PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
@@ -805,7 +871,9 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATAD2 */
PINCTRL_SUN4I_A10),
SUNXI_FUNCTION(0x4, "uart5"), /* TX */
- SUNXI_FUNCTION(0x5, "ms"), /* BS */
+ SUNXI_FUNCTION_VARIANT(0x5, "ms", /* BS */
+ PINCTRL_SUN4I_A10 |
+ PINCTRL_SUN7I_A20),
SUNXI_FUNCTION_IRQ(0x6, 6), /* EINT6 */
SUNXI_FUNCTION(0x7, "csi1")), /* D6 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 7),
@@ -815,7 +883,9 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATAD3 */
PINCTRL_SUN4I_A10),
SUNXI_FUNCTION(0x4, "uart5"), /* RX */
- SUNXI_FUNCTION(0x5, "ms"), /* CLK */
+ SUNXI_FUNCTION_VARIANT(0x5, "ms", /* CLK */
+ PINCTRL_SUN4I_A10 |
+ PINCTRL_SUN7I_A20),
SUNXI_FUNCTION_IRQ(0x6, 7), /* EINT7 */
SUNXI_FUNCTION(0x7, "csi1")), /* D7 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 8),
@@ -825,9 +895,12 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATAD4 */
PINCTRL_SUN4I_A10),
SUNXI_FUNCTION_VARIANT(0x3, "emac", /* ERXD3 */
- PINCTRL_SUN7I_A20),
+ PINCTRL_SUN7I_A20 |
+ PINCTRL_SUN8I_R40),
SUNXI_FUNCTION(0x4, "keypad"), /* IN0 */
- SUNXI_FUNCTION(0x5, "ms"), /* D0 */
+ SUNXI_FUNCTION_VARIANT(0x5, "ms", /* D0 */
+ PINCTRL_SUN4I_A10 |
+ PINCTRL_SUN7I_A20),
SUNXI_FUNCTION_IRQ(0x6, 8), /* EINT8 */
SUNXI_FUNCTION(0x7, "csi1")), /* D8 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 9),
@@ -837,9 +910,12 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATAD5 */
PINCTRL_SUN4I_A10),
SUNXI_FUNCTION_VARIANT(0x3, "emac", /* ERXD2 */
- PINCTRL_SUN7I_A20),
+ PINCTRL_SUN7I_A20 |
+ PINCTRL_SUN8I_R40),
SUNXI_FUNCTION(0x4, "keypad"), /* IN1 */
- SUNXI_FUNCTION(0x5, "ms"), /* D1 */
+ SUNXI_FUNCTION_VARIANT(0x5, "ms", /* D1 */
+ PINCTRL_SUN4I_A10 |
+ PINCTRL_SUN7I_A20),
SUNXI_FUNCTION_IRQ(0x6, 9), /* EINT9 */
SUNXI_FUNCTION(0x7, "csi1")), /* D9 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 10),
@@ -849,9 +925,12 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATAD6 */
PINCTRL_SUN4I_A10),
SUNXI_FUNCTION_VARIANT(0x3, "emac", /* ERXD1 */
- PINCTRL_SUN7I_A20),
+ PINCTRL_SUN7I_A20 |
+ PINCTRL_SUN8I_R40),
SUNXI_FUNCTION(0x4, "keypad"), /* IN2 */
- SUNXI_FUNCTION(0x5, "ms"), /* D2 */
+ SUNXI_FUNCTION_VARIANT(0x5, "ms", /* D2 */
+ PINCTRL_SUN4I_A10 |
+ PINCTRL_SUN7I_A20),
SUNXI_FUNCTION_IRQ(0x6, 10), /* EINT10 */
SUNXI_FUNCTION(0x7, "csi1")), /* D10 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 11),
@@ -861,9 +940,12 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATAD7 */
PINCTRL_SUN4I_A10),
SUNXI_FUNCTION_VARIANT(0x3, "emac", /* ERXD0 */
- PINCTRL_SUN7I_A20),
+ PINCTRL_SUN7I_A20 |
+ PINCTRL_SUN8I_R40),
SUNXI_FUNCTION(0x4, "keypad"), /* IN3 */
- SUNXI_FUNCTION(0x5, "ms"), /* D3 */
+ SUNXI_FUNCTION_VARIANT(0x5, "ms", /* D3 */
+ PINCTRL_SUN4I_A10 |
+ PINCTRL_SUN7I_A20),
SUNXI_FUNCTION_IRQ(0x6, 11), /* EINT11 */
SUNXI_FUNCTION(0x7, "csi1")), /* D11 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 12),
@@ -892,7 +974,8 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATAD10 */
PINCTRL_SUN4I_A10),
SUNXI_FUNCTION_VARIANT(0x3, "emac", /* ETXD3 */
- PINCTRL_SUN7I_A20),
+ PINCTRL_SUN7I_A20 |
+ PINCTRL_SUN8I_R40),
SUNXI_FUNCTION(0x4, "keypad"), /* IN4 */
SUNXI_FUNCTION(0x5, "sim"), /* VPPEN */
SUNXI_FUNCTION_IRQ(0x6, 14), /* EINT14 */
@@ -904,7 +987,8 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATAD11 */
PINCTRL_SUN4I_A10),
SUNXI_FUNCTION_VARIANT(0x3, "emac", /* ETXD2 */
- PINCTRL_SUN7I_A20),
+ PINCTRL_SUN7I_A20 |
+ PINCTRL_SUN8I_R40),
SUNXI_FUNCTION(0x4, "keypad"), /* IN5 */
SUNXI_FUNCTION(0x5, "sim"), /* VPPPP */
SUNXI_FUNCTION_IRQ(0x6, 15), /* EINT15 */
@@ -916,7 +1000,10 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATAD12 */
PINCTRL_SUN4I_A10),
SUNXI_FUNCTION_VARIANT(0x3, "emac", /* ETXD1 */
- PINCTRL_SUN7I_A20),
+ PINCTRL_SUN7I_A20 |
+ PINCTRL_SUN8I_R40),
+ SUNXI_FUNCTION_VARIANT(0x5, "sim", /* DET */
+ PINCTRL_SUN8I_R40),
SUNXI_FUNCTION(0x4, "keypad"), /* IN6 */
SUNXI_FUNCTION_IRQ(0x6, 16), /* EINT16 */
SUNXI_FUNCTION(0x7, "csi1")), /* D16 */
@@ -927,7 +1014,8 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATAD13 */
PINCTRL_SUN4I_A10),
SUNXI_FUNCTION_VARIANT(0x3, "emac", /* ETXD0 */
- PINCTRL_SUN7I_A20),
+ PINCTRL_SUN7I_A20 |
+ PINCTRL_SUN8I_R40),
SUNXI_FUNCTION(0x4, "keypad"), /* IN7 */
SUNXI_FUNCTION(0x5, "sim"), /* VCCEN */
SUNXI_FUNCTION_IRQ(0x6, 17), /* EINT17 */
@@ -939,7 +1027,8 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATAD14 */
PINCTRL_SUN4I_A10),
SUNXI_FUNCTION_VARIANT(0x3, "emac", /* ERXCK */
- PINCTRL_SUN7I_A20),
+ PINCTRL_SUN7I_A20 |
+ PINCTRL_SUN8I_R40),
SUNXI_FUNCTION(0x4, "keypad"), /* OUT0 */
SUNXI_FUNCTION(0x5, "sim"), /* SCK */
SUNXI_FUNCTION_IRQ(0x6, 18), /* EINT18 */
@@ -951,7 +1040,8 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATAD15 */
PINCTRL_SUN4I_A10),
SUNXI_FUNCTION_VARIANT(0x3, "emac", /* ERXERR */
- PINCTRL_SUN7I_A20),
+ PINCTRL_SUN7I_A20 |
+ PINCTRL_SUN8I_R40),
SUNXI_FUNCTION(0x4, "keypad"), /* OUT1 */
SUNXI_FUNCTION(0x5, "sim"), /* SDA */
SUNXI_FUNCTION_IRQ(0x6, 19), /* EINT19 */
@@ -963,7 +1053,8 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATAOE */
PINCTRL_SUN4I_A10),
SUNXI_FUNCTION_VARIANT(0x3, "emac", /* ERXDV */
- PINCTRL_SUN7I_A20),
+ PINCTRL_SUN7I_A20 |
+ PINCTRL_SUN8I_R40),
SUNXI_FUNCTION(0x4, "can"), /* TX */
SUNXI_FUNCTION_IRQ(0x6, 20), /* EINT20 */
SUNXI_FUNCTION(0x7, "csi1")), /* D20 */
@@ -974,7 +1065,8 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATADREQ */
PINCTRL_SUN4I_A10),
SUNXI_FUNCTION_VARIANT(0x3, "emac", /* EMDC */
- PINCTRL_SUN7I_A20),
+ PINCTRL_SUN7I_A20 |
+ PINCTRL_SUN8I_R40),
SUNXI_FUNCTION(0x4, "can"), /* RX */
SUNXI_FUNCTION_IRQ(0x6, 21), /* EINT21 */
SUNXI_FUNCTION(0x7, "csi1")), /* D21 */
@@ -985,7 +1077,8 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATADACK */
PINCTRL_SUN4I_A10),
SUNXI_FUNCTION_VARIANT(0x3, "emac", /* EMDIO */
- PINCTRL_SUN7I_A20),
+ PINCTRL_SUN7I_A20 |
+ PINCTRL_SUN8I_R40),
SUNXI_FUNCTION(0x4, "keypad"), /* OUT2 */
SUNXI_FUNCTION(0x5, "mmc1"), /* CMD */
SUNXI_FUNCTION(0x7, "csi1")), /* D22 */
@@ -996,7 +1089,8 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATACS0 */
PINCTRL_SUN4I_A10),
SUNXI_FUNCTION_VARIANT(0x3, "emac", /* ETXEN */
- PINCTRL_SUN7I_A20),
+ PINCTRL_SUN7I_A20 |
+ PINCTRL_SUN8I_R40),
SUNXI_FUNCTION(0x4, "keypad"), /* OUT3 */
SUNXI_FUNCTION(0x5, "mmc1"), /* CLK */
SUNXI_FUNCTION(0x7, "csi1")), /* D23 */
@@ -1007,7 +1101,8 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATACS1 */
PINCTRL_SUN4I_A10),
SUNXI_FUNCTION_VARIANT(0x3, "emac", /* ETXCK */
- PINCTRL_SUN7I_A20),
+ PINCTRL_SUN7I_A20 |
+ PINCTRL_SUN8I_R40),
SUNXI_FUNCTION(0x4, "keypad"), /* OUT4 */
SUNXI_FUNCTION(0x5, "mmc1"), /* D0 */
SUNXI_FUNCTION(0x7, "csi1")), /* PCLK */
@@ -1018,7 +1113,8 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATAIORDY */
PINCTRL_SUN4I_A10),
SUNXI_FUNCTION_VARIANT(0x3, "emac", /* ECRS */
- PINCTRL_SUN7I_A20),
+ PINCTRL_SUN7I_A20 |
+ PINCTRL_SUN8I_R40),
SUNXI_FUNCTION(0x4, "keypad"), /* OUT5 */
SUNXI_FUNCTION(0x5, "mmc1"), /* D1 */
SUNXI_FUNCTION(0x7, "csi1")), /* FIELD */
@@ -1029,7 +1125,8 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATAIOR */
PINCTRL_SUN4I_A10),
SUNXI_FUNCTION_VARIANT(0x3, "emac", /* ECOL */
- PINCTRL_SUN7I_A20),
+ PINCTRL_SUN7I_A20 |
+ PINCTRL_SUN8I_R40),
SUNXI_FUNCTION(0x4, "keypad"), /* OUT6 */
SUNXI_FUNCTION(0x5, "mmc1"), /* D2 */
SUNXI_FUNCTION(0x7, "csi1")), /* HSYNC */
@@ -1040,7 +1137,8 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATAIOW */
PINCTRL_SUN4I_A10),
SUNXI_FUNCTION_VARIANT(0x3, "emac", /* ETXERR */
- PINCTRL_SUN7I_A20),
+ PINCTRL_SUN7I_A20 |
+ PINCTRL_SUN8I_R40),
SUNXI_FUNCTION(0x4, "keypad"), /* OUT7 */
SUNXI_FUNCTION(0x5, "mmc1"), /* D3 */
SUNXI_FUNCTION(0x7, "csi1")), /* VSYNC */
@@ -1049,23 +1147,27 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION_VARIANT(0x3, "i2c3", /* SCK */
- PINCTRL_SUN7I_A20)),
+ PINCTRL_SUN7I_A20 |
+ PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION_VARIANT(0x3, "i2c3", /* SDA */
- PINCTRL_SUN7I_A20)),
+ PINCTRL_SUN7I_A20 |
+ PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION_VARIANT(0x3, "i2c4", /* SCK */
- PINCTRL_SUN7I_A20)),
+ PINCTRL_SUN7I_A20 |
+ PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "pwm"), /* PWM1 */
SUNXI_FUNCTION_VARIANT(0x3, "i2c3", /* SDA */
- PINCTRL_SUN7I_A20)),
+ PINCTRL_SUN7I_A20 |
+ PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
@@ -1108,7 +1210,8 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION(0x2, "spi0"), /* MOSI */
SUNXI_FUNCTION(0x3, "uart6"), /* TX */
SUNXI_FUNCTION_VARIANT(0x4, "clk_out_a",
- PINCTRL_SUN7I_A20),
+ PINCTRL_SUN7I_A20 |
+ PINCTRL_SUN8I_R40),
SUNXI_FUNCTION_IRQ(0x6, 24)), /* EINT24 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 13),
SUNXI_FUNCTION(0x0, "gpio_in"),
@@ -1116,7 +1219,8 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION(0x2, "spi0"), /* MISO */
SUNXI_FUNCTION(0x3, "uart6"), /* RX */
SUNXI_FUNCTION_VARIANT(0x4, "clk_out_b",
- PINCTRL_SUN7I_A20),
+ PINCTRL_SUN7I_A20 |
+ PINCTRL_SUN8I_R40),
SUNXI_FUNCTION_IRQ(0x6, 25)), /* EINT25 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 14),
SUNXI_FUNCTION(0x0, "gpio_in"),
@@ -1161,13 +1265,25 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "ps2"), /* SCK0 */
SUNXI_FUNCTION(0x3, "uart7"), /* TX */
- SUNXI_FUNCTION(0x4, "hdmi")), /* HSCL */
+ SUNXI_FUNCTION_VARIANT(0x4,
+ "hdmi", /* HSCL */
+ PINCTRL_SUN4I_A10 |
+ PINCTRL_SUN7I_A20),
+ SUNXI_FUNCTION_VARIANT(0x6,
+ "pwm", /* PWM2 */
+ PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 21),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "ps2"), /* SDA0 */
SUNXI_FUNCTION(0x3, "uart7"), /* RX */
- SUNXI_FUNCTION(0x4, "hdmi")), /* HSDA */
+ SUNXI_FUNCTION_VARIANT(0x4,
+ "hdmi", /* HSDA */
+ PINCTRL_SUN4I_A10 |
+ PINCTRL_SUN7I_A20),
+ SUNXI_FUNCTION_VARIANT(0x6,
+ "pwm", /* PWM3 */
+ PINCTRL_SUN8I_R40)),
};
static const struct sunxi_pinctrl_desc sun4i_a10_pinctrl_data = {
@@ -1194,6 +1310,10 @@ static const struct of_device_id sun4i_a10_pinctrl_match[] = {
.compatible = "allwinner,sun7i-a20-pinctrl",
.data = (void *)PINCTRL_SUN7I_A20
},
+ {
+ .compatible = "allwinner,sun8i-r40-pinctrl",
+ .data = (void *)PINCTRL_SUN8I_R40
+ },
{}
};
--
2.12.2
[toc] | [prev] | [next] | [standalone]
| From | Icenowy Zheng <icenowy@aosc.io> |
|---|---|
| Date | 2017-05-04 16:20 +0200 |
| Subject | [PATCH v2 03/10] pinctrl: sunxi: add A20 support to A10 driver |
| Message-ID | <tDpC9-4uB-3@gated-at.bofh.it> |
| In reply to | #1635750 |
As A20 is designed as a pin-compatible upgrade of A10, their pin
controller are very similar, and can share one driver.
Add A20 support to the A10 driver.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c | 287 +++++++++++++++++++++++-------
1 file changed, 224 insertions(+), 63 deletions(-)
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c b/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c
index fb30b86a97ee..159580c04b14 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c
@@ -24,101 +24,147 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac"), /* ERXD3 */
SUNXI_FUNCTION(0x3, "spi1"), /* CS0 */
- SUNXI_FUNCTION(0x4, "uart2")), /* RTS */
+ SUNXI_FUNCTION(0x4, "uart2"), /* RTS */
+ SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* GRXD3 */
+ PINCTRL_SUN7I_A20)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac"), /* ERXD2 */
SUNXI_FUNCTION(0x3, "spi1"), /* CLK */
- SUNXI_FUNCTION(0x4, "uart2")), /* CTS */
+ SUNXI_FUNCTION(0x4, "uart2"), /* CTS */
+ SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* GRXD2 */
+ PINCTRL_SUN7I_A20)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac"), /* ERXD1 */
SUNXI_FUNCTION(0x3, "spi1"), /* MOSI */
- SUNXI_FUNCTION(0x4, "uart2")), /* TX */
+ SUNXI_FUNCTION(0x4, "uart2"), /* TX */
+ SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* GRXD1 */
+ PINCTRL_SUN7I_A20)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac"), /* ERXD0 */
SUNXI_FUNCTION(0x3, "spi1"), /* MISO */
- SUNXI_FUNCTION(0x4, "uart2")), /* RX */
+ SUNXI_FUNCTION(0x4, "uart2"), /* RX */
+ SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* GRXD0 */
+ PINCTRL_SUN7I_A20)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac"), /* ETXD3 */
- SUNXI_FUNCTION(0x3, "spi1")), /* CS1 */
+ SUNXI_FUNCTION(0x3, "spi1"), /* CS1 */
+ SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* GTXD3 */
+ PINCTRL_SUN7I_A20)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac"), /* ETXD2 */
- SUNXI_FUNCTION(0x3, "spi3")), /* CS0 */
+ SUNXI_FUNCTION(0x3, "spi3"), /* CS0 */
+ SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* GTXD2 */
+ PINCTRL_SUN7I_A20)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac"), /* ETXD1 */
- SUNXI_FUNCTION(0x3, "spi3")), /* CLK */
+ SUNXI_FUNCTION(0x3, "spi3"), /* CLK */
+ SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* GTXD1 */
+ PINCTRL_SUN7I_A20)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac"), /* ETXD0 */
- SUNXI_FUNCTION(0x3, "spi3")), /* MOSI */
+ SUNXI_FUNCTION(0x3, "spi3"), /* MOSI */
+ SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* GTXD0 */
+ PINCTRL_SUN7I_A20)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 8),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac"), /* ERXCK */
- SUNXI_FUNCTION(0x3, "spi3")), /* MISO */
+ SUNXI_FUNCTION(0x3, "spi3"), /* MISO */
+ SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* GRXCK */
+ PINCTRL_SUN7I_A20)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac"), /* ERXERR */
- SUNXI_FUNCTION(0x3, "spi3")), /* CS1 */
+ SUNXI_FUNCTION(0x3, "spi3"), /* CS1 */
+ SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* GNULL / ERXERR */
+ PINCTRL_SUN7I_A20),
+ SUNXI_FUNCTION_VARIANT(0x6, "i2s1", /* MCLK */
+ PINCTRL_SUN7I_A20)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 10),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac"), /* ERXDV */
- SUNXI_FUNCTION(0x4, "uart1")), /* TX */
+ SUNXI_FUNCTION(0x4, "uart1"), /* TX */
+ SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* GRXDV */
+ PINCTRL_SUN7I_A20)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 11),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac"), /* EMDC */
- SUNXI_FUNCTION(0x4, "uart1")), /* RX */
+ SUNXI_FUNCTION(0x4, "uart1"), /* RX */
+ SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* EMDC */
+ PINCTRL_SUN7I_A20)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 12),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac"), /* EMDIO */
SUNXI_FUNCTION(0x3, "uart6"), /* TX */
- SUNXI_FUNCTION(0x4, "uart1")), /* RTS */
+ SUNXI_FUNCTION(0x4, "uart1"), /* RTS */
+ SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* EMDIO */
+ PINCTRL_SUN7I_A20)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 13),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac"), /* ETXEN */
SUNXI_FUNCTION(0x3, "uart6"), /* RX */
- SUNXI_FUNCTION(0x4, "uart1")), /* CTS */
+ SUNXI_FUNCTION(0x4, "uart1"), /* CTS */
+ SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* GTXCTL / ETXEN */
+ PINCTRL_SUN7I_A20)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 14),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac"), /* ETXCK */
SUNXI_FUNCTION(0x3, "uart7"), /* TX */
- SUNXI_FUNCTION(0x4, "uart1")), /* DTR */
+ SUNXI_FUNCTION(0x4, "uart1"), /* DTR */
+ SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* GNULL / ETXCK */
+ PINCTRL_SUN7I_A20),
+ SUNXI_FUNCTION_VARIANT(0x6, "i2s1", /* BCLK */
+ PINCTRL_SUN7I_A20)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 15),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac"), /* ECRS */
SUNXI_FUNCTION(0x3, "uart7"), /* RX */
- SUNXI_FUNCTION(0x4, "uart1")), /* DSR */
+ SUNXI_FUNCTION(0x4, "uart1"), /* DSR */
+ SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* GTXCK / ECRS */
+ PINCTRL_SUN7I_A20),
+ SUNXI_FUNCTION_VARIANT(0x6, "i2s1", /* LRCK */
+ PINCTRL_SUN7I_A20)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 16),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac"), /* ECOL */
SUNXI_FUNCTION(0x3, "can"), /* TX */
- SUNXI_FUNCTION(0x4, "uart1")), /* DCD */
+ SUNXI_FUNCTION(0x4, "uart1"), /* DCD */
+ SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* GCLKIN / ECOL */
+ PINCTRL_SUN7I_A20),
+ SUNXI_FUNCTION_VARIANT(0x6, "i2s1", /* DO */
+ PINCTRL_SUN7I_A20)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 17),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac"), /* ETXERR */
SUNXI_FUNCTION(0x3, "can"), /* RX */
- SUNXI_FUNCTION(0x4, "uart1")), /* RING */
+ SUNXI_FUNCTION(0x4, "uart1"), /* RING */
+ SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* GNULL / ETXERR */
+ PINCTRL_SUN7I_A20),
+ SUNXI_FUNCTION_VARIANT(0x6, "i2s1", /* DI */
+ PINCTRL_SUN7I_A20)),
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
@@ -150,47 +196,77 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
- SUNXI_FUNCTION(0x2, "i2s"), /* MCLK */
+ /*
+ * On A10 there's only one I2S controller and the pin group
+ * is simply named "i2s". On A20 there's two and thus it's
+ * renamed to "i2s0". Deal with these name here, in order
+ * to satisfy existing device trees.
+ */
+ SUNXI_FUNCTION_VARIANT(0x2, "i2s", /* MCLK */
+ PINCTRL_SUN4I_A10),
+ SUNXI_FUNCTION_VARIANT(0x2, "i2s0", /* MCLK */
+ PINCTRL_SUN7I_A20),
SUNXI_FUNCTION(0x3, "ac97")), /* MCLK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
- SUNXI_FUNCTION(0x2, "i2s"), /* BCLK */
+ SUNXI_FUNCTION_VARIANT(0x2, "i2s", /* BCLK */
+ PINCTRL_SUN4I_A10),
+ SUNXI_FUNCTION_VARIANT(0x2, "i2s0", /* BCLK */
+ PINCTRL_SUN7I_A20),
SUNXI_FUNCTION(0x3, "ac97")), /* BCLK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
- SUNXI_FUNCTION(0x2, "i2s"), /* LRCK */
+ SUNXI_FUNCTION_VARIANT(0x2, "i2s", /* LRCK */
+ PINCTRL_SUN4I_A10),
+ SUNXI_FUNCTION_VARIANT(0x2, "i2s0", /* LRCK */
+ PINCTRL_SUN7I_A20),
SUNXI_FUNCTION(0x3, "ac97")), /* SYNC */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 8),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
- SUNXI_FUNCTION(0x2, "i2s"), /* DO0 */
+ SUNXI_FUNCTION_VARIANT(0x2, "i2s", /* DO0 */
+ PINCTRL_SUN4I_A10),
+ SUNXI_FUNCTION_VARIANT(0x2, "i2s0", /* DO0 */
+ PINCTRL_SUN7I_A20),
SUNXI_FUNCTION(0x3, "ac97")), /* DO */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
- SUNXI_FUNCTION(0x2, "i2s")), /* DO1 */
+ SUNXI_FUNCTION_VARIANT(0x2, "i2s", /* DO1 */
+ PINCTRL_SUN4I_A10),
+ SUNXI_FUNCTION_VARIANT(0x2, "i2s0", /* DO1 */
+ PINCTRL_SUN7I_A20)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 10),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
- SUNXI_FUNCTION(0x2, "i2s")), /* DO2 */
+ SUNXI_FUNCTION_VARIANT(0x2, "i2s", /* DO2 */
+ PINCTRL_SUN4I_A10),
+ SUNXI_FUNCTION_VARIANT(0x2, "i2s0", /* DO2 */
+ PINCTRL_SUN7I_A20)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 11),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
- SUNXI_FUNCTION(0x2, "i2s")), /* DO3 */
+ SUNXI_FUNCTION_VARIANT(0x2, "i2s", /* DO3 */
+ PINCTRL_SUN4I_A10),
+ SUNXI_FUNCTION_VARIANT(0x2, "i2s0", /* DO3 */
+ PINCTRL_SUN7I_A20)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 12),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
- SUNXI_FUNCTION(0x2, "i2s"), /* DI */
+ SUNXI_FUNCTION_VARIANT(0x2, "i2s", /* DI */
+ PINCTRL_SUN4I_A10),
+ SUNXI_FUNCTION_VARIANT(0x2, "i2s0", /* DI */
+ PINCTRL_SUN7I_A20),
SUNXI_FUNCTION(0x3, "ac97"), /* DI */
- /* Undocumented mux function - See SPDIF MCLK above */
+ /* Undocumented mux function on A10 - See SPDIF MCLK above */
SUNXI_FUNCTION(0x4, "spdif")), /* SPDIF IN */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 13),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi2"), /* CS1 */
- /* Undocumented mux function - See SPDIF MCLK above */
+ /* Undocumented mux function on A10 - See SPDIF MCLK above */
SUNXI_FUNCTION(0x4, "spdif")), /* SPDIF OUT */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 14),
SUNXI_FUNCTION(0x0, "gpio_in"),
@@ -672,7 +748,8 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd1"), /* D0 */
- SUNXI_FUNCTION(0x3, "pata"), /* ATAA0 */
+ SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATAA0 */
+ PINCTRL_SUN4I_A10),
SUNXI_FUNCTION(0x4, "uart3"), /* TX */
SUNXI_FUNCTION_IRQ(0x6, 0), /* EINT0 */
SUNXI_FUNCTION(0x7, "csi1")), /* D0 */
@@ -680,7 +757,8 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd1"), /* D1 */
- SUNXI_FUNCTION(0x3, "pata"), /* ATAA1 */
+ SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATAA1 */
+ PINCTRL_SUN4I_A10),
SUNXI_FUNCTION(0x4, "uart3"), /* RX */
SUNXI_FUNCTION_IRQ(0x6, 1), /* EINT1 */
SUNXI_FUNCTION(0x7, "csi1")), /* D1 */
@@ -688,7 +766,8 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd1"), /* D2 */
- SUNXI_FUNCTION(0x3, "pata"), /* ATAA2 */
+ SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATAA2 */
+ PINCTRL_SUN4I_A10),
SUNXI_FUNCTION(0x4, "uart3"), /* RTS */
SUNXI_FUNCTION_IRQ(0x6, 2), /* EINT2 */
SUNXI_FUNCTION(0x7, "csi1")), /* D2 */
@@ -696,7 +775,8 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd1"), /* D3 */
- SUNXI_FUNCTION(0x3, "pata"), /* ATAIRQ */
+ SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATAIRQ */
+ PINCTRL_SUN4I_A10),
SUNXI_FUNCTION(0x4, "uart3"), /* CTS */
SUNXI_FUNCTION_IRQ(0x6, 3), /* EINT3 */
SUNXI_FUNCTION(0x7, "csi1")), /* D3 */
@@ -704,7 +784,8 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd1"), /* D4 */
- SUNXI_FUNCTION(0x3, "pata"), /* ATAD0 */
+ SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATAD0 */
+ PINCTRL_SUN4I_A10),
SUNXI_FUNCTION(0x4, "uart4"), /* TX */
SUNXI_FUNCTION_IRQ(0x6, 4), /* EINT4 */
SUNXI_FUNCTION(0x7, "csi1")), /* D4 */
@@ -712,7 +793,8 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd1"), /* D5 */
- SUNXI_FUNCTION(0x3, "pata"), /* ATAD1 */
+ SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATAD1 */
+ PINCTRL_SUN4I_A10),
SUNXI_FUNCTION(0x4, "uart4"), /* RX */
SUNXI_FUNCTION_IRQ(0x6, 5), /* EINT5 */
SUNXI_FUNCTION(0x7, "csi1")), /* D5 */
@@ -720,7 +802,8 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd1"), /* D6 */
- SUNXI_FUNCTION(0x3, "pata"), /* ATAD2 */
+ SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATAD2 */
+ PINCTRL_SUN4I_A10),
SUNXI_FUNCTION(0x4, "uart5"), /* TX */
SUNXI_FUNCTION(0x5, "ms"), /* BS */
SUNXI_FUNCTION_IRQ(0x6, 6), /* EINT6 */
@@ -729,7 +812,8 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd1"), /* D7 */
- SUNXI_FUNCTION(0x3, "pata"), /* ATAD3 */
+ SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATAD3 */
+ PINCTRL_SUN4I_A10),
SUNXI_FUNCTION(0x4, "uart5"), /* RX */
SUNXI_FUNCTION(0x5, "ms"), /* CLK */
SUNXI_FUNCTION_IRQ(0x6, 7), /* EINT7 */
@@ -738,7 +822,10 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd1"), /* D8 */
- SUNXI_FUNCTION(0x3, "pata"), /* ATAD4 */
+ SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATAD4 */
+ PINCTRL_SUN4I_A10),
+ SUNXI_FUNCTION_VARIANT(0x3, "emac", /* ERXD3 */
+ PINCTRL_SUN7I_A20),
SUNXI_FUNCTION(0x4, "keypad"), /* IN0 */
SUNXI_FUNCTION(0x5, "ms"), /* D0 */
SUNXI_FUNCTION_IRQ(0x6, 8), /* EINT8 */
@@ -747,7 +834,10 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd1"), /* D9 */
- SUNXI_FUNCTION(0x3, "pata"), /* ATAD5 */
+ SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATAD5 */
+ PINCTRL_SUN4I_A10),
+ SUNXI_FUNCTION_VARIANT(0x3, "emac", /* ERXD2 */
+ PINCTRL_SUN7I_A20),
SUNXI_FUNCTION(0x4, "keypad"), /* IN1 */
SUNXI_FUNCTION(0x5, "ms"), /* D1 */
SUNXI_FUNCTION_IRQ(0x6, 9), /* EINT9 */
@@ -756,7 +846,10 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd1"), /* D10 */
- SUNXI_FUNCTION(0x3, "pata"), /* ATAD6 */
+ SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATAD6 */
+ PINCTRL_SUN4I_A10),
+ SUNXI_FUNCTION_VARIANT(0x3, "emac", /* ERXD1 */
+ PINCTRL_SUN7I_A20),
SUNXI_FUNCTION(0x4, "keypad"), /* IN2 */
SUNXI_FUNCTION(0x5, "ms"), /* D2 */
SUNXI_FUNCTION_IRQ(0x6, 10), /* EINT10 */
@@ -765,7 +858,10 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd1"), /* D11 */
- SUNXI_FUNCTION(0x3, "pata"), /* ATAD7 */
+ SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATAD7 */
+ PINCTRL_SUN4I_A10),
+ SUNXI_FUNCTION_VARIANT(0x3, "emac", /* ERXD0 */
+ PINCTRL_SUN7I_A20),
SUNXI_FUNCTION(0x4, "keypad"), /* IN3 */
SUNXI_FUNCTION(0x5, "ms"), /* D3 */
SUNXI_FUNCTION_IRQ(0x6, 11), /* EINT11 */
@@ -774,7 +870,8 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd1"), /* D12 */
- SUNXI_FUNCTION(0x3, "pata"), /* ATAD8 */
+ SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATAD8 */
+ PINCTRL_SUN4I_A10),
SUNXI_FUNCTION(0x4, "ps2"), /* SCK1 */
SUNXI_FUNCTION_IRQ(0x6, 12), /* EINT12 */
SUNXI_FUNCTION(0x7, "csi1")), /* D12 */
@@ -782,7 +879,8 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd1"), /* D13 */
- SUNXI_FUNCTION(0x3, "pata"), /* ATAD9 */
+ SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATAD9 */
+ PINCTRL_SUN4I_A10),
SUNXI_FUNCTION(0x4, "ps2"), /* SDA1 */
SUNXI_FUNCTION(0x5, "sim"), /* RST */
SUNXI_FUNCTION_IRQ(0x6, 13), /* EINT13 */
@@ -791,7 +889,10 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd1"), /* D14 */
- SUNXI_FUNCTION(0x3, "pata"), /* ATAD10 */
+ SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATAD10 */
+ PINCTRL_SUN4I_A10),
+ SUNXI_FUNCTION_VARIANT(0x3, "emac", /* ETXD3 */
+ PINCTRL_SUN7I_A20),
SUNXI_FUNCTION(0x4, "keypad"), /* IN4 */
SUNXI_FUNCTION(0x5, "sim"), /* VPPEN */
SUNXI_FUNCTION_IRQ(0x6, 14), /* EINT14 */
@@ -800,7 +901,10 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd1"), /* D15 */
- SUNXI_FUNCTION(0x3, "pata"), /* ATAD11 */
+ SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATAD11 */
+ PINCTRL_SUN4I_A10),
+ SUNXI_FUNCTION_VARIANT(0x3, "emac", /* ETXD2 */
+ PINCTRL_SUN7I_A20),
SUNXI_FUNCTION(0x4, "keypad"), /* IN5 */
SUNXI_FUNCTION(0x5, "sim"), /* VPPPP */
SUNXI_FUNCTION_IRQ(0x6, 15), /* EINT15 */
@@ -809,7 +913,10 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd1"), /* D16 */
- SUNXI_FUNCTION(0x3, "pata"), /* ATAD12 */
+ SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATAD12 */
+ PINCTRL_SUN4I_A10),
+ SUNXI_FUNCTION_VARIANT(0x3, "emac", /* ETXD1 */
+ PINCTRL_SUN7I_A20),
SUNXI_FUNCTION(0x4, "keypad"), /* IN6 */
SUNXI_FUNCTION_IRQ(0x6, 16), /* EINT16 */
SUNXI_FUNCTION(0x7, "csi1")), /* D16 */
@@ -817,7 +924,10 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd1"), /* D17 */
- SUNXI_FUNCTION(0x3, "pata"), /* ATAD13 */
+ SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATAD13 */
+ PINCTRL_SUN4I_A10),
+ SUNXI_FUNCTION_VARIANT(0x3, "emac", /* ETXD0 */
+ PINCTRL_SUN7I_A20),
SUNXI_FUNCTION(0x4, "keypad"), /* IN7 */
SUNXI_FUNCTION(0x5, "sim"), /* VCCEN */
SUNXI_FUNCTION_IRQ(0x6, 17), /* EINT17 */
@@ -826,7 +936,10 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd1"), /* D18 */
- SUNXI_FUNCTION(0x3, "pata"), /* ATAD14 */
+ SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATAD14 */
+ PINCTRL_SUN4I_A10),
+ SUNXI_FUNCTION_VARIANT(0x3, "emac", /* ERXCK */
+ PINCTRL_SUN7I_A20),
SUNXI_FUNCTION(0x4, "keypad"), /* OUT0 */
SUNXI_FUNCTION(0x5, "sim"), /* SCK */
SUNXI_FUNCTION_IRQ(0x6, 18), /* EINT18 */
@@ -835,7 +948,10 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd1"), /* D19 */
- SUNXI_FUNCTION(0x3, "pata"), /* ATAD15 */
+ SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATAD15 */
+ PINCTRL_SUN4I_A10),
+ SUNXI_FUNCTION_VARIANT(0x3, "emac", /* ERXERR */
+ PINCTRL_SUN7I_A20),
SUNXI_FUNCTION(0x4, "keypad"), /* OUT1 */
SUNXI_FUNCTION(0x5, "sim"), /* SDA */
SUNXI_FUNCTION_IRQ(0x6, 19), /* EINT19 */
@@ -844,7 +960,10 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd1"), /* D20 */
- SUNXI_FUNCTION(0x3, "pata"), /* ATAOE */
+ SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATAOE */
+ PINCTRL_SUN4I_A10),
+ SUNXI_FUNCTION_VARIANT(0x3, "emac", /* ERXDV */
+ PINCTRL_SUN7I_A20),
SUNXI_FUNCTION(0x4, "can"), /* TX */
SUNXI_FUNCTION_IRQ(0x6, 20), /* EINT20 */
SUNXI_FUNCTION(0x7, "csi1")), /* D20 */
@@ -852,7 +971,10 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd1"), /* D21 */
- SUNXI_FUNCTION(0x3, "pata"), /* ATADREQ */
+ SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATADREQ */
+ PINCTRL_SUN4I_A10),
+ SUNXI_FUNCTION_VARIANT(0x3, "emac", /* EMDC */
+ PINCTRL_SUN7I_A20),
SUNXI_FUNCTION(0x4, "can"), /* RX */
SUNXI_FUNCTION_IRQ(0x6, 21), /* EINT21 */
SUNXI_FUNCTION(0x7, "csi1")), /* D21 */
@@ -860,7 +982,10 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd1"), /* D22 */
- SUNXI_FUNCTION(0x3, "pata"), /* ATADACK */
+ SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATADACK */
+ PINCTRL_SUN4I_A10),
+ SUNXI_FUNCTION_VARIANT(0x3, "emac", /* EMDIO */
+ PINCTRL_SUN7I_A20),
SUNXI_FUNCTION(0x4, "keypad"), /* OUT2 */
SUNXI_FUNCTION(0x5, "mmc1"), /* CMD */
SUNXI_FUNCTION(0x7, "csi1")), /* D22 */
@@ -868,7 +993,10 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd1"), /* D23 */
- SUNXI_FUNCTION(0x3, "pata"), /* ATACS0 */
+ SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATACS0 */
+ PINCTRL_SUN4I_A10),
+ SUNXI_FUNCTION_VARIANT(0x3, "emac", /* ETXEN */
+ PINCTRL_SUN7I_A20),
SUNXI_FUNCTION(0x4, "keypad"), /* OUT3 */
SUNXI_FUNCTION(0x5, "mmc1"), /* CLK */
SUNXI_FUNCTION(0x7, "csi1")), /* D23 */
@@ -876,7 +1004,10 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd1"), /* CLK */
- SUNXI_FUNCTION(0x3, "pata"), /* ATACS1 */
+ SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATACS1 */
+ PINCTRL_SUN4I_A10),
+ SUNXI_FUNCTION_VARIANT(0x3, "emac", /* ETXCK */
+ PINCTRL_SUN7I_A20),
SUNXI_FUNCTION(0x4, "keypad"), /* OUT4 */
SUNXI_FUNCTION(0x5, "mmc1"), /* D0 */
SUNXI_FUNCTION(0x7, "csi1")), /* PCLK */
@@ -884,7 +1015,10 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd1"), /* DE */
- SUNXI_FUNCTION(0x3, "pata"), /* ATAIORDY */
+ SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATAIORDY */
+ PINCTRL_SUN4I_A10),
+ SUNXI_FUNCTION_VARIANT(0x3, "emac", /* ECRS */
+ PINCTRL_SUN7I_A20),
SUNXI_FUNCTION(0x4, "keypad"), /* OUT5 */
SUNXI_FUNCTION(0x5, "mmc1"), /* D1 */
SUNXI_FUNCTION(0x7, "csi1")), /* FIELD */
@@ -892,7 +1026,10 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd1"), /* HSYNC */
- SUNXI_FUNCTION(0x3, "pata"), /* ATAIOR */
+ SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATAIOR */
+ PINCTRL_SUN4I_A10),
+ SUNXI_FUNCTION_VARIANT(0x3, "emac", /* ECOL */
+ PINCTRL_SUN7I_A20),
SUNXI_FUNCTION(0x4, "keypad"), /* OUT6 */
SUNXI_FUNCTION(0x5, "mmc1"), /* D2 */
SUNXI_FUNCTION(0x7, "csi1")), /* HSYNC */
@@ -900,24 +1037,35 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd1"), /* VSYNC */
- SUNXI_FUNCTION(0x3, "pata"), /* ATAIOW */
+ SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATAIOW */
+ PINCTRL_SUN4I_A10),
+ SUNXI_FUNCTION_VARIANT(0x3, "emac", /* ETXERR */
+ PINCTRL_SUN7I_A20),
SUNXI_FUNCTION(0x4, "keypad"), /* OUT7 */
SUNXI_FUNCTION(0x5, "mmc1"), /* D3 */
SUNXI_FUNCTION(0x7, "csi1")), /* VSYNC */
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION_VARIANT(0x3, "i2c3", /* SCK */
+ PINCTRL_SUN7I_A20)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION_VARIANT(0x3, "i2c3", /* SDA */
+ PINCTRL_SUN7I_A20)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION_VARIANT(0x3, "i2c4", /* SCK */
+ PINCTRL_SUN7I_A20)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
- SUNXI_FUNCTION(0x2, "pwm")), /* PWM1 */
+ SUNXI_FUNCTION(0x2, "pwm"), /* PWM1 */
+ SUNXI_FUNCTION_VARIANT(0x3, "i2c3", /* SDA */
+ PINCTRL_SUN7I_A20)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
@@ -959,12 +1107,16 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi0"), /* MOSI */
SUNXI_FUNCTION(0x3, "uart6"), /* TX */
+ SUNXI_FUNCTION_VARIANT(0x4, "clk_out_a",
+ PINCTRL_SUN7I_A20),
SUNXI_FUNCTION_IRQ(0x6, 24)), /* EINT24 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 13),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi0"), /* MISO */
SUNXI_FUNCTION(0x3, "uart6"), /* RX */
+ SUNXI_FUNCTION_VARIANT(0x4, "clk_out_b",
+ PINCTRL_SUN7I_A20),
SUNXI_FUNCTION_IRQ(0x6, 25)), /* EINT25 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 14),
SUNXI_FUNCTION(0x0, "gpio_in"),
@@ -1027,12 +1179,21 @@ static const struct sunxi_pinctrl_desc sun4i_a10_pinctrl_data = {
static int sun4i_a10_pinctrl_probe(struct platform_device *pdev)
{
- return sunxi_pinctrl_init(pdev,
- &sun4i_a10_pinctrl_data);
+ unsigned long variant = (unsigned long)of_device_get_match_data(&pdev->dev);
+
+ return sunxi_pinctrl_init_with_variant(pdev, &sun4i_a10_pinctrl_data,
+ variant);
}
static const struct of_device_id sun4i_a10_pinctrl_match[] = {
- { .compatible = "allwinner,sun4i-a10-pinctrl", },
+ {
+ .compatible = "allwinner,sun4i-a10-pinctrl",
+ .data = (void *)PINCTRL_SUN4I_A10
+ },
+ {
+ .compatible = "allwinner,sun7i-a20-pinctrl",
+ .data = (void *)PINCTRL_SUN7I_A20
+ },
{}
};
--
2.12.2
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| From | Icenowy Zheng <icenowy@aosc.io> |
|---|---|
| Date | 2017-05-04 16:20 +0200 |
| Subject | [PATCH v2 05/10] dt-bindings: add compatible string for Allwinner R40 pinctrl |
| Message-ID | <tDpLQ-4yP-33@gated-at.bofh.it> |
| In reply to | #1635750 |
Allwinner R40 has a pin controller like the ones in older Allwinner SoCs (especially A20), and can use modified version of the A10/A20 pinctrl driver. Add a compatible string for it. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> --- Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt index b53224473672..3ab9f7849a19 100644 --- a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt @@ -22,6 +22,7 @@ Required properties: "allwinner,sun8i-a83t-pinctrl" "allwinner,sun8i-h3-pinctrl" "allwinner,sun8i-h3-r-pinctrl" + "allwinner,sun8i-r40-pinctrl" "allwinner,sun50i-a64-pinctrl" "allwinner,sun50i-a64-r-pinctrl" "allwinner,sun50i-h5-pinctrl" -- 2.12.2
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| From | Rob Herring <robh@kernel.org> |
|---|---|
| Date | 2017-05-08 18:50 +0200 |
| Subject | Re: [PATCH v2 05/10] dt-bindings: add compatible string for Allwinner R40 pinctrl |
| Message-ID | <tEU1c-6nV-23@gated-at.bofh.it> |
| In reply to | #1635777 |
On Thu, May 04, 2017 at 09:50:01PM +0800, Icenowy Zheng wrote: > Allwinner R40 has a pin controller like the ones in older Allwinner SoCs > (especially A20), and can use modified version of the A10/A20 pinctrl > driver. > > Add a compatible string for it. > > Signed-off-by: Icenowy Zheng <icenowy@aosc.io> > --- > Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt | 1 + > 1 file changed, 1 insertion(+) Acked-by: Rob Herring <robh@kernel.org>
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| From | Maxime Ripard <maxime.ripard@free-electrons.com> |
|---|---|
| Date | 2017-05-04 16:30 +0200 |
| Subject | Re: [PATCH v2 08/10] clk: sunxi-ng: support R40 SoC |
| Message-ID | <tDpVw-4CY-23@gated-at.bofh.it> |
| In reply to | #1635750 |
[Multipart message — attachments visible in raw view] — view raw
On Thu, May 04, 2017 at 09:50:04PM +0800, Icenowy Zheng wrote:
> From: Icenowy Zheng <icenowy@aosc.xyz>
>
> Allwinner R40 SoC have a clock controller module in the style of the
> SoCs beyond sun6i, however, it's more rich and complex.
>
> Add support for it.
>
> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
> ---
> Changes in v2:
> - Fixes according to the SoC's user manual.
>
> drivers/clk/sunxi-ng/Kconfig | 10 +
> drivers/clk/sunxi-ng/Makefile | 1 +
> drivers/clk/sunxi-ng/ccu-sun8i-r40.c | 1153 +++++++++++++++++++++++++++++
> drivers/clk/sunxi-ng/ccu-sun8i-r40.h | 68 ++
> include/dt-bindings/clock/sun8i-r40-ccu.h | 191 +++++
> include/dt-bindings/reset/sun8i-r40-ccu.h | 129 ++++
> 6 files changed, 1552 insertions(+)
> create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-r40.c
> create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-r40.h
> create mode 100644 include/dt-bindings/clock/sun8i-r40-ccu.h
> create mode 100644 include/dt-bindings/reset/sun8i-r40-ccu.h
>
> diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig
> index 64088e599404..e6884eafde44 100644
> --- a/drivers/clk/sunxi-ng/Kconfig
> +++ b/drivers/clk/sunxi-ng/Kconfig
> @@ -140,6 +140,16 @@ config SUN8I_V3S_CCU
> default MACH_SUN8I
> depends on MACH_SUN8I || COMPILE_TEST
>
> +config SUN8I_R40_CCU
> + bool "Support for the Allwinner R40 CCU"
> + select SUNXI_CCU_DIV
> + select SUNXI_CCU_NK
> + select SUNXI_CCU_NKM
> + select SUNXI_CCU_NKMP
> + select SUNXI_CCU_NM
> + select SUNXI_CCU_MP
> + default MACH_SUN8I
> +
> config SUN9I_A80_CCU
> bool "Support for the Allwinner A80 CCU"
> select SUNXI_CCU_DIV
> diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-ng/Makefile
> index 0ec02fe14c50..aa00b641484e 100644
> --- a/drivers/clk/sunxi-ng/Makefile
> +++ b/drivers/clk/sunxi-ng/Makefile
> @@ -26,6 +26,7 @@ obj-$(CONFIG_SUN8I_A33_CCU) += ccu-sun8i-a33.o
> obj-$(CONFIG_SUN8I_H3_CCU) += ccu-sun8i-h3.o
> obj-$(CONFIG_SUN8I_V3S_CCU) += ccu-sun8i-v3s.o
> obj-$(CONFIG_SUN8I_R_CCU) += ccu-sun8i-r.o
> +obj-$(CONFIG_SUN8I_R40_CCU) += ccu-sun8i-r40.o
> obj-$(CONFIG_SUN9I_A80_CCU) += ccu-sun9i-a80.o
> obj-$(CONFIG_SUN9I_A80_CCU) += ccu-sun9i-a80-de.o
> obj-$(CONFIG_SUN9I_A80_CCU) += ccu-sun9i-a80-usb.o
> diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-r40.c b/drivers/clk/sunxi-ng/ccu-sun8i-r40.c
> new file mode 100644
> index 000000000000..0cc1b1ab7c3f
> --- /dev/null
> +++ b/drivers/clk/sunxi-ng/ccu-sun8i-r40.c
> @@ -0,0 +1,1153 @@
> +/*
> + * Copyright (c) 2016 Icenowy Zheng <icenowy@aosc.xyz>
> + *
> + * This software is licensed under the terms of the GNU General Public
> + * License version 2, as published by the Free Software Foundation, and
> + * may be copied, distributed, and modified under those terms.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +#include <linux/clk-provider.h>
> +#include <linux/of_address.h>
> +
> +#include "ccu_common.h"
> +#include "ccu_reset.h"
> +
> +#include "ccu_div.h"
> +#include "ccu_gate.h"
> +#include "ccu_mp.h"
> +#include "ccu_mult.h"
> +#include "ccu_nk.h"
> +#include "ccu_nkm.h"
> +#include "ccu_nkmp.h"
> +#include "ccu_nm.h"
> +#include "ccu_phase.h"
> +
> +#include "ccu-sun8i-r40.h"
> +
> +static SUNXI_CCU_NKMP_WITH_GATE_LOCK(pll_cpu_clk, "pll-cpu",
> + "osc24M", 0x000,
> + 8, 5, /* N */
> + 4, 2, /* K */
> + 0, 2, /* M */
> + 16, 2, /* P */
> + BIT(31), /* gate */
> + BIT(28), /* lock */
> + 0);
> +
> +/*
> + * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
> + * the base (2x, 4x and 8x), and one variable divider (the one true
> + * pll audio).
> + *
> + * We don't have any need for the variable divider for now, so we just
> + * hardcode it to match with the clock names
> + */
> +#define SUN8I_R40_PLL_AUDIO_REG 0x008
> +
> +static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
> + "osc24M", 0x008,
> + 8, 7, /* N */
> + 0, 5, /* M */
> + BIT(31), /* gate */
> + BIT(28), /* lock */
> + 0);
> +
> +static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video0_clk, "pll-video0",
> + "osc24M", 0x0010,
> + 8, 7, /* N */
> + 0, 4, /* M */
> + BIT(24), /* frac enable */
> + BIT(25), /* frac select */
> + 270000000, /* frac rate 0 */
> + 297000000, /* frac rate 1 */
> + BIT(31), /* gate */
> + BIT(28), /* lock */
> + 0);
> +
> +static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
> + "osc24M", 0x0018,
> + 8, 7, /* N */
> + 0, 4, /* M */
> + BIT(24), /* frac enable */
> + BIT(25), /* frac select */
> + 270000000, /* frac rate 0 */
> + 297000000, /* frac rate 1 */
> + BIT(31), /* gate */
> + BIT(28), /* lock */
> + 0);
> +
> +static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr0_clk, "pll-ddr0",
> + "osc24M", 0x020,
> + 8, 5, /* N */
> + 4, 2, /* K */
> + 0, 2, /* M */
> + BIT(31), /* gate */
> + BIT(28), /* lock */
> + 0);
> +
> +/* According to the BSP driver, pll-periph{0,1} have M at 0:1 */
> +static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_periph0_clk, "pll-periph0",
> + "osc24M", 0x028,
> + 8, 5, /* N */
> + 4, 2, /* K */
> + 0, 2, /* M */
> + BIT(31), /* gate */
> + BIT(28), /* lock */
> + 0);
> +
> +static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_periph1_clk, "pll-periph1",
> + "osc24M", 0x02c,
> + 8, 5, /* N */
> + 4, 2, /* K */
> + 0, 2, /* M */
> + BIT(31), /* gate */
> + BIT(28), /* lock */
> + 0);
> +
> +static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video1_clk, "pll-video1",
> + "osc24M", 0x030,
> + 8, 7, /* N */
> + 0, 4, /* M */
> + BIT(24), /* frac enable */
> + BIT(25), /* frac select */
> + 270000000, /* frac rate 0 */
> + 297000000, /* frac rate 1 */
> + BIT(31), /* gate */
> + BIT(28), /* lock */
> + CLK_SET_RATE_UNGATE);
> +
> +/*
> + * For the special bit in gate part, please see the BSP source code at
> + * https://github.com/BPI-SINOVOIP/BPI-M2U-bsp/blob/master/linux-sunxi/drivers/clk/sunxi/clk-sun8iw11.c#L665
> + */
Please don't put URLs in there. They are meant to be broken.
> +static CLK_FIXED_FACTOR(osc24m_2x_clk, "osc24M-2x",
> + "osc24M", 1, 2, 0);
There's a single user for this. You should just be using a factor to
the parent clock, there's no need to introduce a new clock.
> +static CLK_FIXED_FACTOR(osc24m_32k_clk, "osc24M-32k",
> + "osc24M", 750, 1, 0);
This is fed from a 16MHz clock, likely the internal oscillator, that
is muxed from the RTC...
> +static struct clk_hw_onecell_data sun8i_r40_hw_clks = {
> + .hws = {
> + [CLK_OSC24M_2X] = &osc24m_2x_clk.hw,
> + [CLK_OSC24M_32K] = &osc24m_32k_clk.hw,
Which means that you should be a consumer of the RTC clock, not feed
it.
> + [CLK_PLL_CPU] = &pll_cpu_clk.common.hw,
> + [CLK_PLL_AUDIO_BASE] = &pll_audio_base_clk.common.hw,
> + [CLK_PLL_AUDIO] = &pll_audio_clk.hw,
> + [CLK_PLL_AUDIO_2X] = &pll_audio_2x_clk.hw,
> + [CLK_PLL_AUDIO_4X] = &pll_audio_4x_clk.hw,
> + [CLK_PLL_AUDIO_8X] = &pll_audio_8x_clk.hw,
> + [CLK_PLL_VIDEO0] = &pll_video0_clk.common.hw,
> + [CLK_PLL_VIDEO0_2X] = &pll_video0_2x_clk.hw,
> + [CLK_PLL_VE] = &pll_ve_clk.common.hw,
> + [CLK_PLL_DDR0] = &pll_ddr0_clk.common.hw,
> + [CLK_PLL_PERIPH0] = &pll_periph0_clk.common.hw,
> + [CLK_PLL_PERIPH0_2X] = &pll_periph0_2x_clk.hw,
> + [CLK_PLL_PERIPH1] = &pll_periph1_clk.common.hw,
> + [CLK_PLL_PERIPH1_2X] = &pll_periph1_2x_clk.hw,
> + [CLK_PLL_VIDEO1] = &pll_video1_clk.common.hw,
> + [CLK_PLL_VIDEO1_2X] = &pll_video1_2x_clk.hw,
> + [CLK_PLL_SATA] = &pll_sata_clk.common.hw,
> + [CLK_PLL_GPU] = &pll_gpu_clk.common.hw,
> + [CLK_PLL_MIPI] = &pll_mipi_clk.common.hw,
> + [CLK_PLL_DE] = &pll_de_clk.common.hw,
> + [CLK_PLL_DDR1] = &pll_ddr1_clk.common.hw,
> + [CLK_CPU] = &cpu_clk.common.hw,
> + [CLK_AXI] = &axi_clk.common.hw,
> + [CLK_AHB1] = &ahb1_clk.common.hw,
> + [CLK_APB1] = &apb1_clk.common.hw,
> + [CLK_APB2] = &apb2_clk.common.hw,
> + [CLK_BUS_MIPI_DSI] = &bus_mipi_dsi_clk.common.hw,
> + [CLK_BUS_CE] = &bus_ce_clk.common.hw,
> + [CLK_BUS_DMA] = &bus_dma_clk.common.hw,
> + [CLK_BUS_MMC0] = &bus_mmc0_clk.common.hw,
> + [CLK_BUS_MMC1] = &bus_mmc1_clk.common.hw,
> + [CLK_BUS_MMC2] = &bus_mmc2_clk.common.hw,
> + [CLK_BUS_MMC3] = &bus_mmc3_clk.common.hw,
> + [CLK_BUS_NAND] = &bus_nand_clk.common.hw,
> + [CLK_BUS_DRAM] = &bus_dram_clk.common.hw,
> + [CLK_BUS_EMAC] = &bus_emac_clk.common.hw,
> + [CLK_BUS_TS] = &bus_ts_clk.common.hw,
> + [CLK_BUS_HSTIMER] = &bus_hstimer_clk.common.hw,
> + [CLK_BUS_SPI0] = &bus_spi0_clk.common.hw,
> + [CLK_BUS_SPI1] = &bus_spi1_clk.common.hw,
> + [CLK_BUS_SPI2] = &bus_spi2_clk.common.hw,
> + [CLK_BUS_SPI3] = &bus_spi3_clk.common.hw,
> + [CLK_BUS_SATA] = &bus_sata_clk.common.hw,
> + [CLK_BUS_OTG] = &bus_otg_clk.common.hw,
> + [CLK_BUS_EHCI0] = &bus_ehci0_clk.common.hw,
> + [CLK_BUS_EHCI1] = &bus_ehci1_clk.common.hw,
> + [CLK_BUS_EHCI2] = &bus_ehci2_clk.common.hw,
> + [CLK_BUS_OHCI0] = &bus_ohci0_clk.common.hw,
> + [CLK_BUS_OHCI1] = &bus_ohci1_clk.common.hw,
> + [CLK_BUS_OHCI2] = &bus_ohci2_clk.common.hw,
> + [CLK_BUS_VE] = &bus_ve_clk.common.hw,
> + [CLK_BUS_DE_MP] = &bus_de_mp_clk.common.hw,
> + [CLK_BUS_DEINTERLACE] = &bus_deinterlace_clk.common.hw,
> + [CLK_BUS_CSI0] = &bus_csi0_clk.common.hw,
> + [CLK_BUS_CSI1] = &bus_csi1_clk.common.hw,
> + [CLK_BUS_HDMI_SLOW] = &bus_hdmi_slow_clk.common.hw,
> + [CLK_BUS_HDMI] = &bus_hdmi_clk.common.hw,
> + [CLK_BUS_DE] = &bus_de_clk.common.hw,
> + [CLK_BUS_TVE0] = &bus_tve0_clk.common.hw,
> + [CLK_BUS_TVE1] = &bus_tve1_clk.common.hw,
> + [CLK_BUS_TVE_TOP] = &bus_tve_top_clk.common.hw,
> + [CLK_BUS_GMAC] = &bus_gmac_clk.common.hw,
> + [CLK_BUS_GPU] = &bus_gpu_clk.common.hw,
> + [CLK_BUS_TVD0] = &bus_tvd0_clk.common.hw,
> + [CLK_BUS_TVD1] = &bus_tvd1_clk.common.hw,
> + [CLK_BUS_TVD2] = &bus_tvd2_clk.common.hw,
> + [CLK_BUS_TVD3] = &bus_tvd3_clk.common.hw,
> + [CLK_BUS_TVD_TOP] = &bus_tvd_top_clk.common.hw,
> + [CLK_BUS_TCON0] = &bus_tcon0_clk.common.hw,
> + [CLK_BUS_TCON1] = &bus_tcon1_clk.common.hw,
> + [CLK_BUS_TVE0_TCON] = &bus_tve0_tcon_clk.common.hw,
> + [CLK_BUS_TVE1_TCON] = &bus_tve1_tcon_clk.common.hw,
> + [CLK_BUS_TCON_TOP] = &bus_tcon_top_clk.common.hw,
> + [CLK_BUS_CODEC] = &bus_codec_clk.common.hw,
> + [CLK_BUS_SPDIF] = &bus_spdif_clk.common.hw,
> + [CLK_BUS_AC97] = &bus_ac97_clk.common.hw,
> + [CLK_BUS_PIO] = &bus_pio_clk.common.hw,
> + [CLK_BUS_IR0] = &bus_ir0_clk.common.hw,
> + [CLK_BUS_IR1] = &bus_ir1_clk.common.hw,
> + [CLK_BUS_THS] = &bus_ths_clk.common.hw,
> + [CLK_BUS_KEYPAD] = &bus_keypad_clk.common.hw,
> + [CLK_BUS_I2S0] = &bus_i2s0_clk.common.hw,
> + [CLK_BUS_I2S1] = &bus_i2s1_clk.common.hw,
> + [CLK_BUS_I2S2] = &bus_i2s2_clk.common.hw,
> + [CLK_BUS_I2C0] = &bus_i2c0_clk.common.hw,
> + [CLK_BUS_I2C1] = &bus_i2c1_clk.common.hw,
> + [CLK_BUS_I2C2] = &bus_i2c2_clk.common.hw,
> + [CLK_BUS_I2C3] = &bus_i2c3_clk.common.hw,
> + [CLK_BUS_CAN] = &bus_can_clk.common.hw,
> + [CLK_BUS_SCR] = &bus_scr_clk.common.hw,
> + [CLK_BUS_PS20] = &bus_ps20_clk.common.hw,
> + [CLK_BUS_PS21] = &bus_ps21_clk.common.hw,
> + [CLK_BUS_I2C4] = &bus_i2c4_clk.common.hw,
> + [CLK_BUS_UART0] = &bus_uart0_clk.common.hw,
> + [CLK_BUS_UART1] = &bus_uart1_clk.common.hw,
> + [CLK_BUS_UART2] = &bus_uart2_clk.common.hw,
> + [CLK_BUS_UART3] = &bus_uart3_clk.common.hw,
> + [CLK_BUS_UART4] = &bus_uart4_clk.common.hw,
> + [CLK_BUS_UART5] = &bus_uart5_clk.common.hw,
> + [CLK_BUS_UART6] = &bus_uart6_clk.common.hw,
> + [CLK_BUS_UART7] = &bus_uart7_clk.common.hw,
> + [CLK_BUS_DBG] = &bus_dbg_clk.common.hw,
> + [CLK_THS] = &ths_clk.common.hw,
> + [CLK_NAND] = &nand_clk.common.hw,
> + [CLK_MMC0] = &mmc0_clk.common.hw,
> + [CLK_MMC1] = &mmc1_clk.common.hw,
> + [CLK_MMC2] = &mmc2_clk.common.hw,
> + [CLK_MMC3] = &mmc3_clk.common.hw,
> + [CLK_TS] = &ts_clk.common.hw,
> + [CLK_CE] = &ce_clk.common.hw,
> + [CLK_SPI0] = &spi0_clk.common.hw,
> + [CLK_SPI1] = &spi1_clk.common.hw,
> + [CLK_SPI2] = &spi2_clk.common.hw,
> + [CLK_SPI3] = &spi3_clk.common.hw,
> + [CLK_I2S0] = &i2s0_clk.common.hw,
> + [CLK_I2S1] = &i2s1_clk.common.hw,
> + [CLK_I2S2] = &i2s2_clk.common.hw,
> + [CLK_AC97] = &ac97_clk.common.hw,
> + [CLK_SPDIF] = &spdif_clk.common.hw,
> + [CLK_KEYPAD] = &keypad_clk.common.hw,
> + [CLK_SATA] = &sata_clk.common.hw,
> + [CLK_USB_PHY0] = &usb_phy0_clk.common.hw,
> + [CLK_USB_PHY1] = &usb_phy1_clk.common.hw,
> + [CLK_USB_PHY2] = &usb_phy2_clk.common.hw,
> + [CLK_USB_OHCI0] = &usb_ohci0_clk.common.hw,
> + [CLK_USB_OHCI1] = &usb_ohci1_clk.common.hw,
> + [CLK_USB_OHCI2] = &usb_ohci2_clk.common.hw,
> + [CLK_USB_OHCI0_12M] = &usb_ohci0_12m_clk.common.hw,
> + [CLK_USB_OHCI1_12M] = &usb_ohci1_12m_clk.common.hw,
> + [CLK_USB_OHCI2_12M] = &usb_ohci2_12m_clk.common.hw,
> + [CLK_IR0] = &ir0_clk.common.hw,
> + [CLK_IR1] = &ir1_clk.common.hw,
> + [CLK_DRAM] = &dram_clk.common.hw,
> + [CLK_DRAM_VE] = &dram_ve_clk.common.hw,
> + [CLK_DRAM_CSI0] = &dram_csi0_clk.common.hw,
> + [CLK_DRAM_CSI1] = &dram_csi1_clk.common.hw,
> + [CLK_DRAM_TS] = &dram_ts_clk.common.hw,
> + [CLK_DRAM_TVD] = &dram_tvd_clk.common.hw,
> + [CLK_DRAM_DE_MP] = &dram_de_mp_clk.common.hw,
> + [CLK_DRAM_DEINTERLACE] = &dram_deinterlace_clk.common.hw,
> + [CLK_DE] = &de_clk.common.hw,
> + [CLK_DE_MP] = &de_mp_clk.common.hw,
> + [CLK_TCON0] = &tcon0_clk.common.hw,
> + [CLK_TCON1] = &tcon1_clk.common.hw,
> + [CLK_TCON_TVE0] = &tcon_tve0_clk.common.hw,
> + [CLK_TCON_TVE1] = &tcon_tve1_clk.common.hw,
> + [CLK_DEINTERLACE] = &deinterlace_clk.common.hw,
> + [CLK_CSI1_MCLK] = &csi1_mclk_clk.common.hw,
> + [CLK_CSI_SCLK] = &csi_sclk_clk.common.hw,
> + [CLK_CSI0_MCLK] = &csi0_mclk_clk.common.hw,
> + [CLK_VE] = &ve_clk.common.hw,
> + [CLK_ADDA] = &adda_clk.common.hw,
> + [CLK_ADDA_4X] = &adda_4x_clk.common.hw,
> + [CLK_AVS] = &avs_clk.common.hw,
> + [CLK_HDMI] = &hdmi_clk.common.hw,
> + [CLK_HDMI_SLOW] = &hdmi_slow_clk.common.hw,
> + [CLK_MBUS] = &mbus_clk.common.hw,
> + [CLK_MIPI_DSI] = &mipi_dsi_clk.common.hw,
> + [CLK_TVE0] = &tve0_clk.common.hw,
> + [CLK_TVE1] = &tve1_clk.common.hw,
> + [CLK_TVD0] = &tvd0_clk.common.hw,
> + [CLK_TVD1] = &tvd1_clk.common.hw,
> + [CLK_TVD2] = &tvd2_clk.common.hw,
> + [CLK_TVD3] = &tvd3_clk.common.hw,
> + [CLK_GPU] = &gpu_clk.common.hw,
> + [CLK_OUTA] = &outa_clk.common.hw,
> + [CLK_OUTB] = &outb_clk.common.hw,
> + },
> + .num = CLK_NUMBER,
> +};
> +
> +static struct ccu_reset_map sun8i_r40_ccu_resets[] = {
> + [RST_USB_PHY0] = { 0x0cc, BIT(0) },
> + [RST_USB_PHY1] = { 0x0cc, BIT(1) },
> + [RST_USB_PHY2] = { 0x0cc, BIT(2) },
> +
> + [RST_MBUS] = { 0x0fc, BIT(31) },
> +
> + [RST_BUS_MIPI_DSI] = { 0x2c0, BIT(1) },
> + [RST_BUS_CE] = { 0x2c0, BIT(5) },
> + [RST_BUS_DMA] = { 0x2c0, BIT(6) },
> + [RST_BUS_MMC0] = { 0x2c0, BIT(8) },
> + [RST_BUS_MMC1] = { 0x2c0, BIT(9) },
> + [RST_BUS_MMC2] = { 0x2c0, BIT(10) },
> + [RST_BUS_MMC3] = { 0x2c0, BIT(11) },
> + [RST_BUS_NAND] = { 0x2c0, BIT(13) },
> + [RST_BUS_DRAM] = { 0x2c0, BIT(14) },
> + [RST_BUS_EMAC] = { 0x2c0, BIT(17) },
> + [RST_BUS_TS] = { 0x2c0, BIT(18) },
> + [RST_BUS_HSTIMER] = { 0x2c0, BIT(19) },
> + [RST_BUS_SPI0] = { 0x2c0, BIT(20) },
> + [RST_BUS_SPI1] = { 0x2c0, BIT(21) },
> + [RST_BUS_SPI2] = { 0x2c0, BIT(22) },
> + [RST_BUS_SPI3] = { 0x2c0, BIT(23) },
> + [RST_BUS_SATA] = { 0x2c0, BIT(24) },
> + [RST_BUS_OTG] = { 0x2c0, BIT(25) },
> + [RST_BUS_EHCI0] = { 0x2c0, BIT(26) },
> + [RST_BUS_EHCI1] = { 0x2c0, BIT(27) },
> + [RST_BUS_EHCI2] = { 0x2c0, BIT(28) },
> + [RST_BUS_OHCI0] = { 0x2c0, BIT(29) },
> + [RST_BUS_OHCI1] = { 0x2c0, BIT(30) },
> + [RST_BUS_OHCI2] = { 0x2c0, BIT(31) },
> +
> + [RST_BUS_VE] = { 0x2c4, BIT(0) },
> + [RST_BUS_DE_MP] = { 0x2c4, BIT(2) },
> + [RST_BUS_DEINTERLACE] = { 0x2c4, BIT(5) },
> + [RST_BUS_CSI0] = { 0x2c4, BIT(8) },
> + [RST_BUS_CSI1] = { 0x2c4, BIT(9) },
> + [RST_BUS_HDMI_SLOW] = { 0x2c4, BIT(10) },
> + [RST_BUS_HDMI] = { 0x2c4, BIT(11) },
> + [RST_BUS_DE] = { 0x2c4, BIT(12) },
> + [RST_BUS_TVE0] = { 0x2c4, BIT(13) },
> + [RST_BUS_TVE1] = { 0x2c4, BIT(14) },
> + [RST_BUS_TVE_TOP] = { 0x2c4, BIT(15) },
> + [RST_BUS_GMAC] = { 0x2c4, BIT(17) },
> + [RST_BUS_GPU] = { 0x2c4, BIT(20) },
> + [RST_BUS_TVD0] = { 0x2c4, BIT(21) },
> + [RST_BUS_TVD1] = { 0x2c4, BIT(22) },
> + [RST_BUS_TVD2] = { 0x2c4, BIT(23) },
> + [RST_BUS_TVD3] = { 0x2c4, BIT(24) },
> + [RST_BUS_TVD_TOP] = { 0x2c4, BIT(25) },
> + [RST_BUS_TCON0] = { 0x2c4, BIT(26) },
> + [RST_BUS_TCON1] = { 0x2c4, BIT(27) },
> + [RST_BUS_TCON_TVE0] = { 0x2c4, BIT(28) },
> + [RST_BUS_TCON_TVE1] = { 0x2c4, BIT(29) },
> + [RST_BUS_TCON_TOP] = { 0x2c4, BIT(30) },
> + [RST_BUS_DBG] = { 0x2c4, BIT(31) },
> +
> + [RST_BUS_LVDS] = { 0x2c8, BIT(0) },
> +
> + [RST_BUS_CODEC] = { 0x2d0, BIT(0) },
> + [RST_BUS_SPDIF] = { 0x2d0, BIT(1) },
> + [RST_BUS_AC97] = { 0x2d0, BIT(2) },
> + [RST_BUS_IR0] = { 0x2d0, BIT(6) },
> + [RST_BUS_IR1] = { 0x2d0, BIT(7) },
> + [RST_BUS_THS] = { 0x2d0, BIT(8) },
> + [RST_BUS_KEYPAD] = { 0x2d0, BIT(10) },
> + [RST_BUS_I2S0] = { 0x2d0, BIT(12) },
> + [RST_BUS_I2S1] = { 0x2d0, BIT(13) },
> + [RST_BUS_I2S2] = { 0x2d0, BIT(14) },
> +
> + [RST_BUS_I2C0] = { 0x2d8, BIT(0) },
> + [RST_BUS_I2C1] = { 0x2d8, BIT(1) },
> + [RST_BUS_I2C2] = { 0x2d8, BIT(2) },
> + [RST_BUS_I2C3] = { 0x2d8, BIT(3) },
> + [RST_BUS_CAN] = { 0x2d8, BIT(4) },
> + [RST_BUS_SCR] = { 0x2d8, BIT(5) },
> + [RST_BUS_PS20] = { 0x2d8, BIT(6) },
> + [RST_BUS_PS21] = { 0x2d8, BIT(7) },
> + [RST_BUS_I2C4] = { 0x2d8, BIT(15) },
> + [RST_BUS_UART0] = { 0x2d8, BIT(16) },
> + [RST_BUS_UART1] = { 0x2d8, BIT(17) },
> + [RST_BUS_UART2] = { 0x2d8, BIT(18) },
> + [RST_BUS_UART3] = { 0x2d8, BIT(19) },
> + [RST_BUS_UART4] = { 0x2d8, BIT(20) },
> + [RST_BUS_UART5] = { 0x2d8, BIT(21) },
> + [RST_BUS_UART6] = { 0x2d8, BIT(22) },
> + [RST_BUS_UART7] = { 0x2d8, BIT(23) },
> +};
> +
> +static const struct sunxi_ccu_desc sun8i_r40_ccu_desc = {
> + .ccu_clks = sun8i_r40_ccu_clks,
> + .num_ccu_clks = ARRAY_SIZE(sun8i_r40_ccu_clks),
> +
> + .hw_clks = &sun8i_r40_hw_clks,
> +
> + .resets = sun8i_r40_ccu_resets,
> + .num_resets = ARRAY_SIZE(sun8i_r40_ccu_resets),
> +};
> +
> +static struct ccu_mux_nb sun8i_r40_cpu_nb = {
> + .common = &cpu_clk.common,
> + .cm = &cpu_clk.mux,
> + .delay_us = 1, /* > 8 clock cycles at 24 MHz */
> + .bypass_index = 1, /* index of 24 MHz oscillator */
> +};
> +
> +static void __init sun8i_r40_ccu_setup(struct device_node *node)
> +{
> + void __iomem *reg;
> + u32 val;
> +
> + reg = of_io_request_and_map(node, 0, of_node_full_name(node));
> + if (IS_ERR(reg)) {
> + pr_err("%s: Could not map the clock registers\n",
> + of_node_full_name(node));
> + return;
> + }
> +
> + /* Force the PLL-Audio-1x divider to 4 */
> + val = readl(reg + SUN8I_R40_PLL_AUDIO_REG);
> + val &= ~GENMASK(19, 16);
> + writel(val | (3 << 16), reg + SUN8I_R40_PLL_AUDIO_REG);
> +
> + sunxi_ccu_probe(node, reg, &sun8i_r40_ccu_desc);
> +
> + ccu_mux_notifier_register(pll_cpu_clk.common.hw.clk,
> + &sun8i_r40_cpu_nb);
Did you test cpufreq on it? IT's likely to miss the gating notifier...
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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| From | Maxime Ripard <maxime.ripard@free-electrons.com> |
|---|---|
| Date | 2017-05-04 16:40 +0200 |
| Subject | Re: [PATCH v2 09/10] ARM: dts: sun8i: Add basic dtsi file for Allwinner R40 |
| Message-ID | <tDq5b-4H2-5@gated-at.bofh.it> |
| In reply to | #1635750 |
[Multipart message — attachments visible in raw view] — view raw
On Thu, May 04, 2017 at 09:50:05PM +0800, Icenowy Zheng wrote:
> From: Chen-Yu Tsai <wens@csie.org>
>
> The Allwinner R40 SoC is marketed as the successor to the A20 SoC.
> The R40 is a smaller chip than the A20, but features the same set
> of programmable pins, with a couple extra pins and some new pin
> functions. The chip features 4 Cortex-A7 cores and a Mali-400 MP2
> GPU. It retains most if not all features from the A20, while adding
> some new features, such as MIPI DSI output, or updating various
> hardware blocks, such as DE 2.0.
>
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
> Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
> ---
> arch/arm/boot/dts/sun8i-r40.dtsi | 404 +++++++++++++++++++++++++++++++++++++++
> 1 file changed, 404 insertions(+)
> create mode 100644 arch/arm/boot/dts/sun8i-r40.dtsi
>
> diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi
> new file mode 100644
> index 000000000000..20d4705a8206
> --- /dev/null
> +++ b/arch/arm/boot/dts/sun8i-r40.dtsi
> @@ -0,0 +1,404 @@
> +/*
> + * Copyright 2017 Chen-Yu Tsai <wens@csie.org>
> + * Copyright 2017 Icenowy Zheng <icenowy@aosc.xyz>
> + *
> + * This file is dual-licensed: you can use it either under the terms
> + * of the GPL or the X11 license, at your option. Note that this dual
> + * licensing only applies to this file, and not this project as a
> + * whole.
> + *
> + * a) This file is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of the
> + * License, or (at your option) any later version.
> + *
> + * This file is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * Or, alternatively,
> + *
> + * b) Permission is hereby granted, free of charge, to any person
> + * obtaining a copy of this software and associated documentation
> + * files (the "Software"), to deal in the Software without
> + * restriction, including without limitation the rights to use,
> + * copy, modify, merge, publish, distribute, sublicense, and/or
> + * sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following
> + * conditions:
> + *
> + * The above copyright notice and this permission notice shall be
> + * included in all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + */
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/clock/sun8i-r40-ccu.h>
> +#include <dt-bindings/reset/sun8i-r40-ccu.h>
> +
> +/ {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + interrupt-parent = <&gic>;
> +
> + aliases {
> + };
> +
> + chosen {
> + };
These two are probably useless...
> + clocks {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> + osc24M: osc24M {
> + #clock-cells = <0>;
> + compatible = "fixed-clock";
> + clock-frequency = <24000000>;
> + };
> +
> + osc32k: osc32k {
> + #clock-cells = <0>;
> + compatible = "fixed-clock";
> + clock-frequency = <32768>;
> + clock-output-names = "osc32k";
> + };
> + };
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu@0 {
> + compatible = "arm,cortex-a7";
> + device_type = "cpu";
> + reg = <0>;
> + };
> +
> + cpu@1 {
> + compatible = "arm,cortex-a7";
> + device_type = "cpu";
> + reg = <1>;
> + };
> +
> + cpu@2 {
> + compatible = "arm,cortex-a7";
> + device_type = "cpu";
> + reg = <2>;
> + };
> +
> + cpu@3 {
> + compatible = "arm,cortex-a7";
> + device_type = "cpu";
> + reg = <3>;
> + };
> + };
> +
> + memory {
> + device_type = "memory";
> + reg = <0x40000000 0x80000000>;
> + };
This one too.
> + soc@1c00000 {
> + compatible = "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> + nmi_intc: interrupt-controller@1c00030 {
> + compatible = "allwinner,sun7i-a20-sc-nmi";
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + reg = <0x01c00030 0x0c>;
> + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + mmc0: mmc@1c0f000 {
> + compatible = "allwinner,sun50i-a64-mmc";
> + reg = <0x01c0f000 0x1000>;
> + clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
> + clock-names = "ahb", "mmc";
> + resets = <&ccu RST_BUS_MMC0>;
> + reset-names = "ahb";
> + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
> + max-frequency = <150000000>;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + mmc1: mmc@1c10000 {
> + compatible = "allwinner,sun50i-a64-mmc";
> + reg = <0x01c10000 0x1000>;
> + clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
> + clock-names = "ahb", "mmc";
> + resets = <&ccu RST_BUS_MMC1>;
> + reset-names = "ahb";
> + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
> + max-frequency = <150000000>;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + mmc2: mmc@1c11000 {
> + compatible = "allwinner,sun50i-a64-emmc";
> + reg = <0x01c11000 0x1000>;
> + clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
> + clock-names = "ahb", "mmc";
> + resets = <&ccu RST_BUS_MMC2>;
> + reset-names = "ahb";
> + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
> + max-frequency = <200000000>;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + mmc3: mmc@1c12000 {
> + compatible = "allwinner,sun50i-a64-mmc";
This needs a specific compatible.
> + reg = <0x01c12000 0x1000>;
> + clocks = <&ccu CLK_BUS_MMC3>, <&ccu CLK_MMC3>;
> + clock-names = "ahb", "mmc";
> + resets = <&ccu RST_BUS_MMC3>;
> + reset-names = "ahb";
> + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
> + max-frequency = <150000000>;
Did you actually test those frequencies?
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + ccu: clock@1c20000 {
> + compatible = "allwinner,sun8i-r40-ccu";
> + reg = <0x01c20000 0x400>;
> + clocks = <&osc24M>, <&osc32k>;
> + clock-names = "hosc", "losc";
This is very likely to be fed from the RTC.
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + };
> +
> + pio: pinctrl@1c20800 {
> + compatible = "allwinner,sun8i-r40-pinctrl";
> + reg = <0x01c20800 0x400>;
> + interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>;
> + clock-names = "apb", "hosc", "losc";
Here too.
> + gpio-controller;
> + interrupt-controller;
> + #interrupt-cells = <3>;
> + #gpio-cells = <3>;
> +
> + i2c0_pins: twi0@0 {
> + pins = "PB0", "PB1";
> + function = "i2c0";
> + };
> +
> + mmc0_pins: mmc0@0 {
> + pins = "PF0", "PF1", "PF2",
> + "PF3", "PF4", "PF5";
> + function = "mmc0";
> + drive-strength = <30>;
> + bias-pull-up;
> + };
> +
> + mmc1_pins: mmc1@0 {
> + pins = "PG0", "PG1", "PG2",
> + "PG3", "PG4", "PG5";
> + function = "mmc1";
> + drive-strength = <30>;
> + bias-pull-up;
> + };
> +
> + mmc2_pins: mmc2@0 {
> + pins = "PC5", "PC6", "PC7", "PC8", "PC9",
> + "PC10", "PC11", "PC12", "PC13", "PC14",
> + "PC15", "PC24";
> + function = "mmc2";
> + drive-strength = <30>;
> + bias-pull-up;
> + };
This implies an 8 bit bus width, which is not that common, and not
your default in the MMC driver either.
> + uart0_pins_0: uart0@0 {
> + pins = "PB22", "PB23";
> + function = "uart0";
> + };
> + };
> +
> + uart0: serial@1c28000 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x01c28000 0x400>;
> + interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + clocks = <&ccu CLK_BUS_UART0>;
> + resets = <&ccu RST_BUS_UART0>;
> + status = "disabled";
> + };
> +
> + uart1: serial@1c28400 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x01c28400 0x400>;
> + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + clocks = <&ccu CLK_BUS_UART1>;
> + resets = <&ccu RST_BUS_UART1>;
> + status = "disabled";
> + };
> +
> + uart2: serial@1c28800 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x01c28800 0x400>;
> + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + clocks = <&ccu CLK_BUS_UART2>;
> + resets = <&ccu RST_BUS_UART2>;
> + status = "disabled";
> + };
> +
> + uart3: serial@1c28c00 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x01c28c00 0x400>;
> + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + clocks = <&ccu CLK_BUS_UART3>;
> + resets = <&ccu RST_BUS_UART3>;
> + status = "disabled";
> + };
> +
> + uart4: serial@1c29000 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x01c29000 0x400>;
> + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + clocks = <&ccu CLK_BUS_UART4>;
> + resets = <&ccu RST_BUS_UART4>;
> + status = "disabled";
> + };
> +
> + uart5: serial@1c29400 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x01c29400 0x400>;
> + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + clocks = <&ccu CLK_BUS_UART5>;
> + resets = <&ccu RST_BUS_UART5>;
> + status = "disabled";
> + };
> +
> + uart6: serial@1c29800 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x01c29800 0x400>;
> + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + clocks = <&ccu CLK_BUS_UART6>;
> + resets = <&ccu RST_BUS_UART6>;
> + status = "disabled";
> + };
> +
> + uart7: serial@1c29c00 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x01c29c00 0x400>;
> + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + clocks = <&ccu CLK_BUS_UART7>;
> + resets = <&ccu RST_BUS_UART7>;
> + status = "disabled";
> + };
> +
> + i2c0: i2c@1c2ac00 {
> + compatible = "allwinner,sun6i-a31-i2c";
> + reg = <0x01c2ac00 0x400>;
> + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_I2C0>;
> + resets = <&ccu RST_BUS_I2C0>;
> + pinctrl-0 = <&i2c0_pins>;
> + pinctrl-names = "default";
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + i2c1: i2c@1c2b000 {
> + compatible = "allwinner,sun6i-a31-i2c";
> + reg = <0x01c2b000 0x400>;
> + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_I2C1>;
> + resets = <&ccu RST_BUS_I2C1>;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + i2c2: i2c@1c2b400 {
> + compatible = "allwinner,sun6i-a31-i2c";
> + reg = <0x01c2b400 0x400>;
> + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_I2C2>;
> + resets = <&ccu RST_BUS_I2C2>;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + i2c3: i2c@1c2b800 {
> + compatible = "allwinner,sun6i-a31-i2c";
> + reg = <0x01c2b800 0x400>;
> + interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_I2C3>;
> + resets = <&ccu RST_BUS_I2C3>;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + i2c4: i2c@1c2c000 {
> + compatible = "allwinner,sun6i-a31-i2c";
> + reg = <0x01c2c000 0x400>;
> + interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_I2C4>;
> + resets = <&ccu RST_BUS_I2C4>;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + gic: interrupt-controller@1c81000 {
> + compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
> + reg = <0x01c81000 0x1000>,
> + <0x01c82000 0x1000>,
> + <0x01c84000 0x2000>,
> + <0x01c86000 0x2000>;
> + interrupt-controller;
> + #interrupt-cells = <3>;
> + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
> + };
> + };
> +
> + timer {
> + compatible = "arm,armv7-timer";
> + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
> + clock-frequency = <24000000>;
> + arm,cpu-registers-not-fw-configured;
Is it true? U-boot doesn't setup those already?
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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| From | Icenowy Zheng <icenowy@aosc.io> |
|---|---|
| Date | 2017-05-04 17:30 +0200 |
| Subject | [PATCH v2 09/10] ARM: dts: sun8i: Add basic dtsi file for Allwinner R40 |
| Message-ID | <tDq5b-4H2-7@gated-at.bofh.it> |
| In reply to | #1635750 |
From: Chen-Yu Tsai <wens@csie.org>
The Allwinner R40 SoC is marketed as the successor to the A20 SoC.
The R40 is a smaller chip than the A20, but features the same set
of programmable pins, with a couple extra pins and some new pin
functions. The chip features 4 Cortex-A7 cores and a Mali-400 MP2
GPU. It retains most if not all features from the A20, while adding
some new features, such as MIPI DSI output, or updating various
hardware blocks, such as DE 2.0.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
---
arch/arm/boot/dts/sun8i-r40.dtsi | 404 +++++++++++++++++++++++++++++++++++++++
1 file changed, 404 insertions(+)
create mode 100644 arch/arm/boot/dts/sun8i-r40.dtsi
diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi
new file mode 100644
index 000000000000..20d4705a8206
--- /dev/null
+++ b/arch/arm/boot/dts/sun8i-r40.dtsi
@@ -0,0 +1,404 @@
+/*
+ * Copyright 2017 Chen-Yu Tsai <wens@csie.org>
+ * Copyright 2017 Icenowy Zheng <icenowy@aosc.xyz>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/sun8i-r40-ccu.h>
+#include <dt-bindings/reset/sun8i-r40-ccu.h>
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <&gic>;
+
+ aliases {
+ };
+
+ chosen {
+ };
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ osc24M: osc24M {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ };
+
+ osc32k: osc32k {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ clock-output-names = "osc32k";
+ };
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ compatible = "arm,cortex-a7";
+ device_type = "cpu";
+ reg = <0>;
+ };
+
+ cpu@1 {
+ compatible = "arm,cortex-a7";
+ device_type = "cpu";
+ reg = <1>;
+ };
+
+ cpu@2 {
+ compatible = "arm,cortex-a7";
+ device_type = "cpu";
+ reg = <2>;
+ };
+
+ cpu@3 {
+ compatible = "arm,cortex-a7";
+ device_type = "cpu";
+ reg = <3>;
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x40000000 0x80000000>;
+ };
+
+ soc@1c00000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ nmi_intc: interrupt-controller@1c00030 {
+ compatible = "allwinner,sun7i-a20-sc-nmi";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x01c00030 0x0c>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ mmc0: mmc@1c0f000 {
+ compatible = "allwinner,sun50i-a64-mmc";
+ reg = <0x01c0f000 0x1000>;
+ clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
+ clock-names = "ahb", "mmc";
+ resets = <&ccu RST_BUS_MMC0>;
+ reset-names = "ahb";
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ max-frequency = <150000000>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mmc1: mmc@1c10000 {
+ compatible = "allwinner,sun50i-a64-mmc";
+ reg = <0x01c10000 0x1000>;
+ clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
+ clock-names = "ahb", "mmc";
+ resets = <&ccu RST_BUS_MMC1>;
+ reset-names = "ahb";
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ max-frequency = <150000000>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mmc2: mmc@1c11000 {
+ compatible = "allwinner,sun50i-a64-emmc";
+ reg = <0x01c11000 0x1000>;
+ clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
+ clock-names = "ahb", "mmc";
+ resets = <&ccu RST_BUS_MMC2>;
+ reset-names = "ahb";
+ interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+ max-frequency = <200000000>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mmc3: mmc@1c12000 {
+ compatible = "allwinner,sun50i-a64-mmc";
+ reg = <0x01c12000 0x1000>;
+ clocks = <&ccu CLK_BUS_MMC3>, <&ccu CLK_MMC3>;
+ clock-names = "ahb", "mmc";
+ resets = <&ccu RST_BUS_MMC3>;
+ reset-names = "ahb";
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+ max-frequency = <150000000>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ ccu: clock@1c20000 {
+ compatible = "allwinner,sun8i-r40-ccu";
+ reg = <0x01c20000 0x400>;
+ clocks = <&osc24M>, <&osc32k>;
+ clock-names = "hosc", "losc";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ pio: pinctrl@1c20800 {
+ compatible = "allwinner,sun8i-r40-pinctrl";
+ reg = <0x01c20800 0x400>;
+ interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>;
+ clock-names = "apb", "hosc", "losc";
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ #gpio-cells = <3>;
+
+ i2c0_pins: twi0@0 {
+ pins = "PB0", "PB1";
+ function = "i2c0";
+ };
+
+ mmc0_pins: mmc0@0 {
+ pins = "PF0", "PF1", "PF2",
+ "PF3", "PF4", "PF5";
+ function = "mmc0";
+ drive-strength = <30>;
+ bias-pull-up;
+ };
+
+ mmc1_pins: mmc1@0 {
+ pins = "PG0", "PG1", "PG2",
+ "PG3", "PG4", "PG5";
+ function = "mmc1";
+ drive-strength = <30>;
+ bias-pull-up;
+ };
+
+ mmc2_pins: mmc2@0 {
+ pins = "PC5", "PC6", "PC7", "PC8", "PC9",
+ "PC10", "PC11", "PC12", "PC13", "PC14",
+ "PC15", "PC24";
+ function = "mmc2";
+ drive-strength = <30>;
+ bias-pull-up;
+ };
+
+ uart0_pins_0: uart0@0 {
+ pins = "PB22", "PB23";
+ function = "uart0";
+ };
+ };
+
+ uart0: serial@1c28000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c28000 0x400>;
+ interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&ccu CLK_BUS_UART0>;
+ resets = <&ccu RST_BUS_UART0>;
+ status = "disabled";
+ };
+
+ uart1: serial@1c28400 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c28400 0x400>;
+ interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&ccu CLK_BUS_UART1>;
+ resets = <&ccu RST_BUS_UART1>;
+ status = "disabled";
+ };
+
+ uart2: serial@1c28800 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c28800 0x400>;
+ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&ccu CLK_BUS_UART2>;
+ resets = <&ccu RST_BUS_UART2>;
+ status = "disabled";
+ };
+
+ uart3: serial@1c28c00 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c28c00 0x400>;
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&ccu CLK_BUS_UART3>;
+ resets = <&ccu RST_BUS_UART3>;
+ status = "disabled";
+ };
+
+ uart4: serial@1c29000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c29000 0x400>;
+ interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&ccu CLK_BUS_UART4>;
+ resets = <&ccu RST_BUS_UART4>;
+ status = "disabled";
+ };
+
+ uart5: serial@1c29400 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c29400 0x400>;
+ interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&ccu CLK_BUS_UART5>;
+ resets = <&ccu RST_BUS_UART5>;
+ status = "disabled";
+ };
+
+ uart6: serial@1c29800 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c29800 0x400>;
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&ccu CLK_BUS_UART6>;
+ resets = <&ccu RST_BUS_UART6>;
+ status = "disabled";
+ };
+
+ uart7: serial@1c29c00 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c29c00 0x400>;
+ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&ccu CLK_BUS_UART7>;
+ resets = <&ccu RST_BUS_UART7>;
+ status = "disabled";
+ };
+
+ i2c0: i2c@1c2ac00 {
+ compatible = "allwinner,sun6i-a31-i2c";
+ reg = <0x01c2ac00 0x400>;
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_I2C0>;
+ resets = <&ccu RST_BUS_I2C0>;
+ pinctrl-0 = <&i2c0_pins>;
+ pinctrl-names = "default";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c1: i2c@1c2b000 {
+ compatible = "allwinner,sun6i-a31-i2c";
+ reg = <0x01c2b000 0x400>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_I2C1>;
+ resets = <&ccu RST_BUS_I2C1>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c2: i2c@1c2b400 {
+ compatible = "allwinner,sun6i-a31-i2c";
+ reg = <0x01c2b400 0x400>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_I2C2>;
+ resets = <&ccu RST_BUS_I2C2>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c3: i2c@1c2b800 {
+ compatible = "allwinner,sun6i-a31-i2c";
+ reg = <0x01c2b800 0x400>;
+ interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_I2C3>;
+ resets = <&ccu RST_BUS_I2C3>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c4: i2c@1c2c000 {
+ compatible = "allwinner,sun6i-a31-i2c";
+ reg = <0x01c2c000 0x400>;
+ interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_I2C4>;
+ resets = <&ccu RST_BUS_I2C4>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ gic: interrupt-controller@1c81000 {
+ compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
+ reg = <0x01c81000 0x1000>,
+ <0x01c82000 0x1000>,
+ <0x01c84000 0x2000>,
+ <0x01c86000 0x2000>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ clock-frequency = <24000000>;
+ arm,cpu-registers-not-fw-configured;
+ };
+};
--
2.12.2
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| From | Linus Walleij <linus.walleij@linaro.org> |
|---|---|
| Date | 2017-05-11 16:50 +0200 |
| Subject | Re: [PATCH v2 04/10] pinctrl: sunxi: switch A20's pinctrl driver to use the A10 version |
| Message-ID | <tFXzJ-7Av-33@gated-at.bofh.it> |
| In reply to | #1635750 |
On Thu, May 4, 2017 at 3:50 PM, Icenowy Zheng <icenowy@aosc.io> wrote: > As we added A20 support to A10 pinctrl driver, now we can delete the > dedicated A20 pinctrl driver, and enable A10 driver for A20. > > Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Looks all right to me but I'm waiting for Maxime's review on these patches. Yours, Linus Walleij
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