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Groups > linux.kernel > #1575389 > unrolled thread
| Started by | Lukasz Majewski <lukma@denx.de> |
|---|---|
| First post | 2017-02-07 06:30 +0100 |
| Last post | 2017-02-07 20:10 +0100 |
| Articles | 7 — 3 participants |
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[PATCH v3 2/3] net: phy: dp83867: Add lane swapping support in the DP83867 TI's PHY driver Lukasz Majewski <lukma@denx.de> - 2017-02-07 06:30 +0100
[PATCH v3 3/3] net: phy: dp83867: Recover from "port mirroring" N/A MODE4 Lukasz Majewski <lukma@denx.de> - 2017-02-07 06:30 +0100
Re: [PATCH v3 3/3] net: phy: dp83867: Recover from "port mirroring" N/A MODE4 Andrew Lunn <andrew@lunn.ch> - 2017-02-07 14:10 +0100
Re: [PATCH v3 3/3] net: phy: dp83867: Recover from "port mirroring" N/A MODE4 David Miller <davem@davemloft.net> - 2017-02-07 20:10 +0100
Re: [PATCH v3 2/3] net: phy: dp83867: Add lane swapping support in the DP83867 TI's PHY driver Andrew Lunn <andrew@lunn.ch> - 2017-02-07 14:10 +0100
Re: [PATCH v3 2/3] net: phy: dp83867: Add lane swapping support in the DP83867 TI's PHY driver Andrew Lunn <andrew@lunn.ch> - 2017-02-07 14:20 +0100
Re: [PATCH v3 2/3] net: phy: dp83867: Add lane swapping support in the DP83867 TI's PHY driver David Miller <davem@davemloft.net> - 2017-02-07 20:10 +0100
| From | Lukasz Majewski <lukma@denx.de> |
|---|---|
| Date | 2017-02-07 06:30 +0100 |
| Subject | [PATCH v3 2/3] net: phy: dp83867: Add lane swapping support in the DP83867 TI's PHY driver |
| Message-ID | <t86vM-6Us-7@gated-at.bofh.it> |
This patch adds support for enabling or disabling the lane swapping (called
"port mirroring" in PHY's CFG4 register) feature of the DP83867 TI's PHY
device.
One use case is when bootstrap configuration enables this feature (because
of e.g. LED_0 wrong wiring) so then one needs to disable it in software
(at u-boot/Linux).
Signed-off-by: Lukasz Majewski <lukma@denx.de>
---
Changes for v3:
- Add "line swapping" to the patch description
- Add DP83867_PORT_MIRROING_KEEP enum for better code readability
Changes for v2:
- use "net-phy-lane-swap" and "net-phy-lane-no-swap" generic PHY properties.
instead of TI specific one
---
drivers/net/phy/dp83867.c | 38 ++++++++++++++++++++++++++++++++++++++
1 file changed, 38 insertions(+)
diff --git a/drivers/net/phy/dp83867.c b/drivers/net/phy/dp83867.c
index ca1b462..be6fa24 100644
--- a/drivers/net/phy/dp83867.c
+++ b/drivers/net/phy/dp83867.c
@@ -32,6 +32,7 @@
#define DP83867_CFG3 0x1e
/* Extended Registers */
+#define DP83867_CFG4 0x0031
#define DP83867_RGMIICTL 0x0032
#define DP83867_RGMIIDCTL 0x0086
#define DP83867_IO_MUX_CFG 0x0170
@@ -70,11 +71,21 @@
#define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX 0x0
#define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN 0x1f
+/* CFG4 bits */
+#define DP83867_CFG4_PORT_MIRROR_EN BIT(0)
+
+enum {
+ DP83867_PORT_MIRROING_KEEP,
+ DP83867_PORT_MIRROING_EN,
+ DP83867_PORT_MIRROING_DIS,
+};
+
struct dp83867_private {
int rx_id_delay;
int tx_id_delay;
int fifo_depth;
int io_impedance;
+ int port_mirroring;
};
static int dp83867_ack_interrupt(struct phy_device *phydev)
@@ -111,6 +122,24 @@ static int dp83867_config_intr(struct phy_device *phydev)
return phy_write(phydev, MII_DP83867_MICR, micr_status);
}
+static int dp83867_config_port_mirroring(struct phy_device *phydev)
+{
+ struct dp83867_private *dp83867 =
+ (struct dp83867_private *)phydev->priv;
+ u16 val;
+
+ val = phy_read_mmd_indirect(phydev, DP83867_CFG4, DP83867_DEVADDR);
+
+ if (dp83867->port_mirroring == DP83867_PORT_MIRROING_EN)
+ val |= DP83867_CFG4_PORT_MIRROR_EN;
+ else
+ val &= ~DP83867_CFG4_PORT_MIRROR_EN;
+
+ phy_write_mmd_indirect(phydev, DP83867_CFG4, DP83867_DEVADDR, val);
+
+ return 0;
+}
+
#ifdef CONFIG_OF_MDIO
static int dp83867_of_init(struct phy_device *phydev)
{
@@ -144,6 +173,12 @@ static int dp83867_of_init(struct phy_device *phydev)
phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID))
return ret;
+ if (of_property_read_bool(of_node, "enet-phy-lane-swap"))
+ dp83867->port_mirroring = DP83867_PORT_MIRROING_EN;
+
+ if (of_property_read_bool(of_node, "enet-phy-lane-no-swap"))
+ dp83867->port_mirroring = DP83867_PORT_MIRROING_DIS;
+
return of_property_read_u32(of_node, "ti,fifo-depth",
&dp83867->fifo_depth);
}
@@ -228,6 +263,9 @@ static int dp83867_config_init(struct phy_device *phydev)
phy_write(phydev, DP83867_CFG3, val);
}
+ if (dp83867->port_mirroring != DP83867_PORT_MIRROING_KEEP)
+ dp83867_config_port_mirroring(phydev);
+
return 0;
}
--
2.1.4
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| From | Lukasz Majewski <lukma@denx.de> |
|---|---|
| Date | 2017-02-07 06:30 +0100 |
| Subject | [PATCH v3 3/3] net: phy: dp83867: Recover from "port mirroring" N/A MODE4 |
| Message-ID | <t86vM-6Us-15@gated-at.bofh.it> |
| In reply to | #1575389 |
The DP83867 when not properly bootstrapped - especially with LED_0 pin -
can enter N/A MODE4 for "port mirroring" feature.
To provide normal operation of the PHY, one needs not only to explicitly
disable the port mirroring feature, but as well stop some IC internal
testing (which disables RGMII communication).
To do that the STRAP_STS1 (0x006E) register must be read and RESERVED bit
11 examined. When it is set, the another RESERVED bit (11) at PHYCR
(0x0010) register must be clear to disable testing mode and enable RGMII
communication.
Thorough explanation of the problem can be found at following e2e thread:
"DP83867IR: Problem with RESERVED bits in PHY Control Register (PHYCR) -
Linux driver"
https://e2e.ti.com/support/interface/ethernet/f/903/p/571313/2096954#2096954
Signed-off-by: Lukasz Majewski <lukma@denx.de>
---
Changes for v3:
- None
---
drivers/net/phy/dp83867.c | 23 ++++++++++++++++++++++-
1 file changed, 22 insertions(+), 1 deletion(-)
diff --git a/drivers/net/phy/dp83867.c b/drivers/net/phy/dp83867.c
index be6fa24..1986553 100644
--- a/drivers/net/phy/dp83867.c
+++ b/drivers/net/phy/dp83867.c
@@ -34,6 +34,7 @@
/* Extended Registers */
#define DP83867_CFG4 0x0031
#define DP83867_RGMIICTL 0x0032
+#define DP83867_STRAP_STS1 0x006E
#define DP83867_RGMIIDCTL 0x0086
#define DP83867_IO_MUX_CFG 0x0170
@@ -58,9 +59,13 @@
#define DP83867_RGMII_TX_CLK_DELAY_EN BIT(1)
#define DP83867_RGMII_RX_CLK_DELAY_EN BIT(0)
+/* STRAP_STS1 bits */
+#define DP83867_STRAP_STS1_RESERVED BIT(11)
+
/* PHY CTRL bits */
#define DP83867_PHYCR_FIFO_DEPTH_SHIFT 14
#define DP83867_PHYCR_FIFO_DEPTH_MASK (3 << 14)
+#define DP83867_PHYCR_RESERVED_MASK BIT(11)
/* RGMIIDCTL bits */
#define DP83867_RGMII_TX_CLK_DELAY_SHIFT 4
@@ -192,7 +197,7 @@ static int dp83867_of_init(struct phy_device *phydev)
static int dp83867_config_init(struct phy_device *phydev)
{
struct dp83867_private *dp83867;
- int ret, val;
+ int ret, val, bs;
u16 delay;
if (!phydev->priv) {
@@ -215,6 +220,22 @@ static int dp83867_config_init(struct phy_device *phydev)
return val;
val &= ~DP83867_PHYCR_FIFO_DEPTH_MASK;
val |= (dp83867->fifo_depth << DP83867_PHYCR_FIFO_DEPTH_SHIFT);
+
+ /* The code below checks if "port mirroring" N/A MODE4 has been
+ * enabled during power on bootstrap.
+ *
+ * Such N/A mode enabled by mistake can put PHY IC in some
+ * internal testing mode and disable RGMII transmission.
+ *
+ * In this particular case one needs to check STRAP_STS1
+ * register's bit 11 (marked as RESERVED).
+ */
+
+ bs = phy_read_mmd_indirect(phydev, DP83867_STRAP_STS1,
+ DP83867_DEVADDR);
+ if (bs & DP83867_STRAP_STS1_RESERVED)
+ val &= ~DP83867_PHYCR_RESERVED_MASK;
+
ret = phy_write(phydev, MII_DP83867_PHYCTRL, val);
if (ret)
return ret;
--
2.1.4
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| From | Andrew Lunn <andrew@lunn.ch> |
|---|---|
| Date | 2017-02-07 14:10 +0100 |
| Subject | Re: [PATCH v3 3/3] net: phy: dp83867: Recover from "port mirroring" N/A MODE4 |
| Message-ID | <t8dGZ-3hn-115@gated-at.bofh.it> |
| In reply to | #1575390 |
On Tue, Feb 07, 2017 at 06:20:24AM +0100, Lukasz Majewski wrote:
> The DP83867 when not properly bootstrapped - especially with LED_0 pin -
> can enter N/A MODE4 for "port mirroring" feature.
>
> To provide normal operation of the PHY, one needs not only to explicitly
> disable the port mirroring feature, but as well stop some IC internal
> testing (which disables RGMII communication).
>
> To do that the STRAP_STS1 (0x006E) register must be read and RESERVED bit
> 11 examined. When it is set, the another RESERVED bit (11) at PHYCR
> (0x0010) register must be clear to disable testing mode and enable RGMII
> communication.
>
> Thorough explanation of the problem can be found at following e2e thread:
> "DP83867IR: Problem with RESERVED bits in PHY Control Register (PHYCR) -
> Linux driver"
>
> https://e2e.ti.com/support/interface/ethernet/f/903/p/571313/2096954#2096954
>
> Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Andrew
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| From | David Miller <davem@davemloft.net> |
|---|---|
| Date | 2017-02-07 20:10 +0100 |
| Subject | Re: [PATCH v3 3/3] net: phy: dp83867: Recover from "port mirroring" N/A MODE4 |
| Message-ID | <t8jjj-6Qz-3@gated-at.bofh.it> |
| In reply to | #1575390 |
From: Lukasz Majewski <lukma@denx.de> Date: Tue, 7 Feb 2017 06:20:24 +0100 > The DP83867 when not properly bootstrapped - especially with LED_0 pin - > can enter N/A MODE4 for "port mirroring" feature. > > To provide normal operation of the PHY, one needs not only to explicitly > disable the port mirroring feature, but as well stop some IC internal > testing (which disables RGMII communication). > > To do that the STRAP_STS1 (0x006E) register must be read and RESERVED bit > 11 examined. When it is set, the another RESERVED bit (11) at PHYCR > (0x0010) register must be clear to disable testing mode and enable RGMII > communication. > > Thorough explanation of the problem can be found at following e2e thread: > "DP83867IR: Problem with RESERVED bits in PHY Control Register (PHYCR) - > Linux driver" > > https://e2e.ti.com/support/interface/ethernet/f/903/p/571313/2096954#2096954 > > Signed-off-by: Lukasz Majewski <lukma@denx.de> > --- > Changes for v3: > - None Applied.
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| From | Andrew Lunn <andrew@lunn.ch> |
|---|---|
| Date | 2017-02-07 14:10 +0100 |
| Subject | Re: [PATCH v3 2/3] net: phy: dp83867: Add lane swapping support in the DP83867 TI's PHY driver |
| Message-ID | <t8dGV-3hn-7@gated-at.bofh.it> |
| In reply to | #1575389 |
On Tue, Feb 07, 2017 at 06:20:23AM +0100, Lukasz Majewski wrote:
> This patch adds support for enabling or disabling the lane swapping (called
> "port mirroring" in PHY's CFG4 register) feature of the DP83867 TI's PHY
> device.
>
> One use case is when bootstrap configuration enables this feature (because
> of e.g. LED_0 wrong wiring) so then one needs to disable it in software
> (at u-boot/Linux).
>
> Signed-off-by: Lukasz Majewski <lukma@denx.de>
So it is documented, in a separate patch, which is out of order.
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Andrew
> ---
> Changes for v3:
> - Add "line swapping" to the patch description
> - Add DP83867_PORT_MIRROING_KEEP enum for better code readability
>
> Changes for v2:
> - use "net-phy-lane-swap" and "net-phy-lane-no-swap" generic PHY properties.
> instead of TI specific one
> ---
> drivers/net/phy/dp83867.c | 38 ++++++++++++++++++++++++++++++++++++++
> 1 file changed, 38 insertions(+)
>
> diff --git a/drivers/net/phy/dp83867.c b/drivers/net/phy/dp83867.c
> index ca1b462..be6fa24 100644
> --- a/drivers/net/phy/dp83867.c
> +++ b/drivers/net/phy/dp83867.c
> @@ -32,6 +32,7 @@
> #define DP83867_CFG3 0x1e
>
> /* Extended Registers */
> +#define DP83867_CFG4 0x0031
> #define DP83867_RGMIICTL 0x0032
> #define DP83867_RGMIIDCTL 0x0086
> #define DP83867_IO_MUX_CFG 0x0170
> @@ -70,11 +71,21 @@
> #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX 0x0
> #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN 0x1f
>
> +/* CFG4 bits */
> +#define DP83867_CFG4_PORT_MIRROR_EN BIT(0)
> +
> +enum {
> + DP83867_PORT_MIRROING_KEEP,
> + DP83867_PORT_MIRROING_EN,
> + DP83867_PORT_MIRROING_DIS,
> +};
> +
> struct dp83867_private {
> int rx_id_delay;
> int tx_id_delay;
> int fifo_depth;
> int io_impedance;
> + int port_mirroring;
> };
>
> static int dp83867_ack_interrupt(struct phy_device *phydev)
> @@ -111,6 +122,24 @@ static int dp83867_config_intr(struct phy_device *phydev)
> return phy_write(phydev, MII_DP83867_MICR, micr_status);
> }
>
> +static int dp83867_config_port_mirroring(struct phy_device *phydev)
> +{
> + struct dp83867_private *dp83867 =
> + (struct dp83867_private *)phydev->priv;
> + u16 val;
> +
> + val = phy_read_mmd_indirect(phydev, DP83867_CFG4, DP83867_DEVADDR);
> +
> + if (dp83867->port_mirroring == DP83867_PORT_MIRROING_EN)
> + val |= DP83867_CFG4_PORT_MIRROR_EN;
> + else
> + val &= ~DP83867_CFG4_PORT_MIRROR_EN;
> +
> + phy_write_mmd_indirect(phydev, DP83867_CFG4, DP83867_DEVADDR, val);
> +
> + return 0;
> +}
> +
> #ifdef CONFIG_OF_MDIO
> static int dp83867_of_init(struct phy_device *phydev)
> {
> @@ -144,6 +173,12 @@ static int dp83867_of_init(struct phy_device *phydev)
> phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID))
> return ret;
>
> + if (of_property_read_bool(of_node, "enet-phy-lane-swap"))
> + dp83867->port_mirroring = DP83867_PORT_MIRROING_EN;
> +
> + if (of_property_read_bool(of_node, "enet-phy-lane-no-swap"))
> + dp83867->port_mirroring = DP83867_PORT_MIRROING_DIS;
> +
> return of_property_read_u32(of_node, "ti,fifo-depth",
> &dp83867->fifo_depth);
> }
> @@ -228,6 +263,9 @@ static int dp83867_config_init(struct phy_device *phydev)
> phy_write(phydev, DP83867_CFG3, val);
> }
>
> + if (dp83867->port_mirroring != DP83867_PORT_MIRROING_KEEP)
> + dp83867_config_port_mirroring(phydev);
> +
> return 0;
> }
>
> --
> 2.1.4
>
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| From | Andrew Lunn <andrew@lunn.ch> |
|---|---|
| Date | 2017-02-07 14:20 +0100 |
| Subject | Re: [PATCH v3 2/3] net: phy: dp83867: Add lane swapping support in the DP83867 TI's PHY driver |
| Message-ID | <t8dQD-3lb-31@gated-at.bofh.it> |
| In reply to | #1575389 |
On Tue, Feb 07, 2017 at 06:20:23AM +0100, Lukasz Majewski wrote: > This patch adds support for enabling or disabling the lane swapping (called > "port mirroring" in PHY's CFG4 register) feature of the DP83867 TI's PHY > device. > > One use case is when bootstrap configuration enables this feature (because > of e.g. LED_0 wrong wiring) so then one needs to disable it in software > (at u-boot/Linux). > > Signed-off-by: Lukasz Majewski <lukma@denx.de> > --- > Changes for v3: > - Add "line swapping" to the patch description > - Add DP83867_PORT_MIRROING_KEEP enum for better code readability > > Changes for v2: > - use "net-phy-lane-swap" and "net-phy-lane-no-swap" generic PHY properties. > instead of TI specific one > --- > drivers/net/phy/dp83867.c | 38 ++++++++++++++++++++++++++++++++++++++ > 1 file changed, 38 insertions(+) Hi Lukasz You are missing the documentation update. Documentation/devicetree/binding/net/phy.h Apart from that, this looks good. Thanks Andrew
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| From | David Miller <davem@davemloft.net> |
|---|---|
| Date | 2017-02-07 20:10 +0100 |
| Subject | Re: [PATCH v3 2/3] net: phy: dp83867: Add lane swapping support in the DP83867 TI's PHY driver |
| Message-ID | <t8jjk-6Qz-7@gated-at.bofh.it> |
| In reply to | #1575389 |
From: Lukasz Majewski <lukma@denx.de> Date: Tue, 7 Feb 2017 06:20:23 +0100 > This patch adds support for enabling or disabling the lane swapping (called > "port mirroring" in PHY's CFG4 register) feature of the DP83867 TI's PHY > device. > > One use case is when bootstrap configuration enables this feature (because > of e.g. LED_0 wrong wiring) so then one needs to disable it in software > (at u-boot/Linux). > > Signed-off-by: Lukasz Majewski <lukma@denx.de> > --- > Changes for v3: > - Add "line swapping" to the patch description > - Add DP83867_PORT_MIRROING_KEEP enum for better code readability > > Changes for v2: > - use "net-phy-lane-swap" and "net-phy-lane-no-swap" generic PHY properties. > instead of TI specific one Applied.
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