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[PATCH v2] EDAC: mpc85xx: Add T2080 l2-cache support

Started byChris Packham <chris.packham@alliedtelesis.co.nz>
First post2017-02-02 00:20 +0100
Last post2017-02-03 10:50 +0100
Articles 8 — 4 participants

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  [PATCH v2] EDAC: mpc85xx: Add T2080 l2-cache support Chris Packham <chris.packham@alliedtelesis.co.nz> - 2017-02-02 00:20 +0100
    Re: [PATCH v2] EDAC: mpc85xx: Add T2080 l2-cache support Borislav Petkov <bp@alien8.de> - 2017-02-02 00:30 +0100
      Re: [PATCH v2] EDAC: mpc85xx: Add T2080 l2-cache support Chris Packham <Chris.Packham@alliedtelesis.co.nz> - 2017-02-02 00:50 +0100
        Re: [PATCH v2] EDAC: mpc85xx: Add T2080 l2-cache support Borislav Petkov <bp@alien8.de> - 2017-02-02 18:50 +0100
          Re: [PATCH v2] EDAC: mpc85xx: Add T2080 l2-cache support Michael Ellerman <mpe@ellerman.id.au> - 2017-02-03 01:00 +0100
            Re: [PATCH v2] EDAC: mpc85xx: Add T2080 l2-cache support Chris Packham <Chris.Packham@alliedtelesis.co.nz> - 2017-02-03 01:20 +0100
              Re: [PATCH v2] EDAC: mpc85xx: Add T2080 l2-cache support Michael Ellerman <mpe@ellerman.id.au> - 2017-02-03 06:20 +0100
            Re: [PATCH v2] EDAC: mpc85xx: Add T2080 l2-cache support Borislav Petkov <bp@alien8.de> - 2017-02-03 10:50 +0100

#1572044 — [PATCH v2] EDAC: mpc85xx: Add T2080 l2-cache support

FromChris Packham <chris.packham@alliedtelesis.co.nz>
Date2017-02-02 00:20 +0100
Subject[PATCH v2] EDAC: mpc85xx: Add T2080 l2-cache support
Message-ID<t6clY-4e8-9@gated-at.bofh.it>
The l2-cache controller on the T2080 SoC has similar capabilities to the
others already supported by the mpc85xx_edac driver. Add it to the list
of compatible devices.

Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Acked-by: Johannes Thumshirn <jth@kernel.org>
---
This is a resend of a patch that got an ack[1] but didn't seem to get
picked up.

[1] http://marc.info/?l=linux-edac&m=148042072225488&w=2

Changes since v1:
- Collect ack from Johannes.

 arch/powerpc/boot/dts/fsl/t2081si-post.dtsi | 1 +
 drivers/edac/mpc85xx_edac.c                 | 1 +
 2 files changed, 2 insertions(+)

diff --git a/arch/powerpc/boot/dts/fsl/t2081si-post.dtsi b/arch/powerpc/boot/dts/fsl/t2081si-post.dtsi
index c744569a20e1..a97296c64eb2 100644
--- a/arch/powerpc/boot/dts/fsl/t2081si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/t2081si-post.dtsi
@@ -678,5 +678,6 @@
 		compatible = "fsl,t2080-l2-cache-controller";
 		reg = <0xc20000 0x40000>;
 		next-level-cache = <&cpc>;
+		interrupts = <16 2 1 9>;
 	};
 };
diff --git a/drivers/edac/mpc85xx_edac.c b/drivers/edac/mpc85xx_edac.c
index 8f66cbed70b7..67f7bc3fe5b3 100644
--- a/drivers/edac/mpc85xx_edac.c
+++ b/drivers/edac/mpc85xx_edac.c
@@ -629,6 +629,7 @@ static const struct of_device_id mpc85xx_l2_err_of_match[] = {
 	{ .compatible = "fsl,p1020-l2-cache-controller", },
 	{ .compatible = "fsl,p1021-l2-cache-controller", },
 	{ .compatible = "fsl,p2020-l2-cache-controller", },
+	{ .compatible = "fsl,t2080-l2-cache-controller", },
 	{},
 };
 MODULE_DEVICE_TABLE(of, mpc85xx_l2_err_of_match);
-- 
2.11.0.24.ge6920cf

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#1572046

FromBorislav Petkov <bp@alien8.de>
Date2017-02-02 00:30 +0100
Message-ID<t6cvD-4hs-3@gated-at.bofh.it>
In reply to#1572044
On Thu, Feb 02, 2017 at 12:16:24PM +1300, Chris Packham wrote:
> The l2-cache controller on the T2080 SoC has similar capabilities to the
> others already supported by the mpc85xx_edac driver. Add it to the list
> of compatible devices.
> 
> Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
> Acked-by: Johannes Thumshirn <jth@kernel.org>
> ---
> This is a resend of a patch that got an ack[1] but didn't seem to get
> picked up.
> 
> [1] http://marc.info/?l=linux-edac&m=148042072225488&w=2
> 
> Changes since v1:
> - Collect ack from Johannes.

Whoops, my bad. Sorry about that.

>  arch/powerpc/boot/dts/fsl/t2081si-post.dtsi | 1 +
>  drivers/edac/mpc85xx_edac.c                 | 1 +
>  2 files changed, 2 insertions(+)
> 
> diff --git a/arch/powerpc/boot/dts/fsl/t2081si-post.dtsi b/arch/powerpc/boot/dts/fsl/t2081si-post.dtsi
> index c744569a20e1..a97296c64eb2 100644
> --- a/arch/powerpc/boot/dts/fsl/t2081si-post.dtsi
> +++ b/arch/powerpc/boot/dts/fsl/t2081si-post.dtsi
> @@ -678,5 +678,6 @@
>  		compatible = "fsl,t2080-l2-cache-controller";
>  		reg = <0xc20000 0x40000>;
>  		next-level-cache = <&cpc>;
> +		interrupts = <16 2 1 9>;
>  	};
>  };
> diff --git a/drivers/edac/mpc85xx_edac.c b/drivers/edac/mpc85xx_edac.c
> index 8f66cbed70b7..67f7bc3fe5b3 100644
> --- a/drivers/edac/mpc85xx_edac.c
> +++ b/drivers/edac/mpc85xx_edac.c
> @@ -629,6 +629,7 @@ static const struct of_device_id mpc85xx_l2_err_of_match[] = {
>  	{ .compatible = "fsl,p1020-l2-cache-controller", },
>  	{ .compatible = "fsl,p1021-l2-cache-controller", },
>  	{ .compatible = "fsl,p2020-l2-cache-controller", },
> +	{ .compatible = "fsl,t2080-l2-cache-controller", },

WARNING: DT compatible string "fsl,t2080-l2-cache-controller" appears un-documented -- check ./Documentation/devicetree/bindings/
#58: FILE: drivers/edac/mpc85xx_edac.c:632:
+       { .compatible = "fsl,t2080-l2-cache-controller", },

What is checkpatch.pl trying to tell me here?

-- 
Regards/Gruss,
    Boris.

Good mailing practices for 400: avoid top-posting and trim the reply.

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#1572072

FromChris Packham <Chris.Packham@alliedtelesis.co.nz>
Date2017-02-02 00:50 +0100
Message-ID<t6cOZ-4om-5@gated-at.bofh.it>
In reply to#1572046
On 02/02/17 12:28, Borislav Petkov wrote:
> On Thu, Feb 02, 2017 at 12:16:24PM +1300, Chris Packham wrote:
>> The l2-cache controller on the T2080 SoC has similar capabilities to the
>> others already supported by the mpc85xx_edac driver. Add it to the list
>> of compatible devices.
>>
>> Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
>> Acked-by: Johannes Thumshirn <jth@kernel.org>
>> ---
>> This is a resend of a patch that got an ack[1] but didn't seem to get
>> picked up.
>>
>> [1] http://marc.info/?l=linux-edac&m=148042072225488&w=2
>>
>> Changes since v1:
>> - Collect ack from Johannes.
>
> Whoops, my bad. Sorry about that.
>
>>  arch/powerpc/boot/dts/fsl/t2081si-post.dtsi | 1 +
>>  drivers/edac/mpc85xx_edac.c                 | 1 +
>>  2 files changed, 2 insertions(+)
>>
>> diff --git a/arch/powerpc/boot/dts/fsl/t2081si-post.dtsi b/arch/powerpc/boot/dts/fsl/t2081si-post.dtsi
>> index c744569a20e1..a97296c64eb2 100644
>> --- a/arch/powerpc/boot/dts/fsl/t2081si-post.dtsi
>> +++ b/arch/powerpc/boot/dts/fsl/t2081si-post.dtsi
>> @@ -678,5 +678,6 @@
>>  		compatible = "fsl,t2080-l2-cache-controller";
>>  		reg = <0xc20000 0x40000>;
>>  		next-level-cache = <&cpc>;
>> +		interrupts = <16 2 1 9>;
>>  	};
>>  };
>> diff --git a/drivers/edac/mpc85xx_edac.c b/drivers/edac/mpc85xx_edac.c
>> index 8f66cbed70b7..67f7bc3fe5b3 100644
>> --- a/drivers/edac/mpc85xx_edac.c
>> +++ b/drivers/edac/mpc85xx_edac.c
>> @@ -629,6 +629,7 @@ static const struct of_device_id mpc85xx_l2_err_of_match[] = {
>>  	{ .compatible = "fsl,p1020-l2-cache-controller", },
>>  	{ .compatible = "fsl,p1021-l2-cache-controller", },
>>  	{ .compatible = "fsl,p2020-l2-cache-controller", },
>> +	{ .compatible = "fsl,t2080-l2-cache-controller", },
>
> WARNING: DT compatible string "fsl,t2080-l2-cache-controller" appears un-documented -- check ./Documentation/devicetree/bindings/
> #58: FILE: drivers/edac/mpc85xx_edac.c:632:
> +       { .compatible = "fsl,t2080-l2-cache-controller", },
>
> What is checkpatch.pl trying to tell me here?
>

checpkatch.pl is confused by 
Documentation/devicetree/bindings/powerpc/fsl/l2cache.txt which says

- compatible    : Should include "fsl,chip-l2-cache-controller" and "cache"
                   where chip is the processor (bsc9132, npc8572 etc.)

So none of the fsl cache controllers pass the checkpatch.pl test.

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#1572545

FromBorislav Petkov <bp@alien8.de>
Date2017-02-02 18:50 +0100
Message-ID<t6tG9-73H-11@gated-at.bofh.it>
In reply to#1572072
On Wed, Feb 01, 2017 at 11:46:23PM +0000, Chris Packham wrote:
> >> diff --git a/drivers/edac/mpc85xx_edac.c b/drivers/edac/mpc85xx_edac.c
> >> index 8f66cbed70b7..67f7bc3fe5b3 100644
> >> --- a/drivers/edac/mpc85xx_edac.c
> >> +++ b/drivers/edac/mpc85xx_edac.c
> >> @@ -629,6 +629,7 @@ static const struct of_device_id mpc85xx_l2_err_of_match[] = {
> >>  	{ .compatible = "fsl,p1020-l2-cache-controller", },
> >>  	{ .compatible = "fsl,p1021-l2-cache-controller", },
> >>  	{ .compatible = "fsl,p2020-l2-cache-controller", },
> >> +	{ .compatible = "fsl,t2080-l2-cache-controller", },
> >
> > WARNING: DT compatible string "fsl,t2080-l2-cache-controller" appears un-documented -- check ./Documentation/devicetree/bindings/
> > #58: FILE: drivers/edac/mpc85xx_edac.c:632:
> > +       { .compatible = "fsl,t2080-l2-cache-controller", },
> >
> > What is checkpatch.pl trying to tell me here?
> >
> 
> checpkatch.pl is confused by 
> Documentation/devicetree/bindings/powerpc/fsl/l2cache.txt which says
> 
> - compatible    : Should include "fsl,chip-l2-cache-controller" and "cache"
>                    where chip is the processor (bsc9132, npc8572 etc.)
> 
> So none of the fsl cache controllers pass the checkpatch.pl test.

Hmm, so others do list those names explicitly. For example:

Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt

And the patch that added that check to cp:

bff5da433525 ("checkpatch: add DT compatible string documentation checks")

is basically to enforce explicit compatible names.

So I'd like to have an ACK from a PPC maintainer here first before I
apply this.

-- 
Regards/Gruss,
    Boris.

Good mailing practices for 400: avoid top-posting and trim the reply.

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#1572816

FromMichael Ellerman <mpe@ellerman.id.au>
Date2017-02-03 01:00 +0100
Message-ID<t6zsd-2i0-7@gated-at.bofh.it>
In reply to#1572545
Borislav Petkov <bp@alien8.de> writes:

> On Wed, Feb 01, 2017 at 11:46:23PM +0000, Chris Packham wrote:
>> >> diff --git a/drivers/edac/mpc85xx_edac.c b/drivers/edac/mpc85xx_edac.c
>> >> index 8f66cbed70b7..67f7bc3fe5b3 100644
>> >> --- a/drivers/edac/mpc85xx_edac.c
>> >> +++ b/drivers/edac/mpc85xx_edac.c
>> >> @@ -629,6 +629,7 @@ static const struct of_device_id mpc85xx_l2_err_of_match[] = {
>> >>  	{ .compatible = "fsl,p1020-l2-cache-controller", },
>> >>  	{ .compatible = "fsl,p1021-l2-cache-controller", },
>> >>  	{ .compatible = "fsl,p2020-l2-cache-controller", },
>> >> +	{ .compatible = "fsl,t2080-l2-cache-controller", },
>> >
>> > WARNING: DT compatible string "fsl,t2080-l2-cache-controller" appears un-documented -- check ./Documentation/devicetree/bindings/
>> > #58: FILE: drivers/edac/mpc85xx_edac.c:632:
>> > +       { .compatible = "fsl,t2080-l2-cache-controller", },
>> >
>> > What is checkpatch.pl trying to tell me here?
>> >
>> 
>> checpkatch.pl is confused by 
>> Documentation/devicetree/bindings/powerpc/fsl/l2cache.txt which says
>> 
>> - compatible    : Should include "fsl,chip-l2-cache-controller" and "cache"
>>                    where chip is the processor (bsc9132, npc8572 etc.)
>> 
>> So none of the fsl cache controllers pass the checkpatch.pl test.
>
> Hmm, so others do list those names explicitly. For example:
>
> Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
>
> And the patch that added that check to cp:
>
> bff5da433525 ("checkpatch: add DT compatible string documentation checks")
>
> is basically to enforce explicit compatible names.
>
> So I'd like to have an ACK from a PPC maintainer here first before I
> apply this.

It's fine with me:

Acked-by: Michael Ellerman <mpe@ellerman.id.au>


Chris if you want to send a patch to add the compatible string to the
l2cache.txt I would merge that, but honestly it doesn't achieve much
other than possibly catching a typo in the compatible name.

cheers

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#1572825

FromChris Packham <Chris.Packham@alliedtelesis.co.nz>
Date2017-02-03 01:20 +0100
Message-ID<t6zLA-2DZ-13@gated-at.bofh.it>
In reply to#1572816
On 03/02/17 12:55, Michael Ellerman wrote:
> Chris if you want to send a patch to add the compatible string to the
> l2cache.txt I would merge that, but honestly it doesn't achieve much
> other than possibly catching a typo in the compatible name.

I think catching a typo might be worthwhile. It's 5 minutes work for me 
to grep/sed through the code to find existing compatible strings and 
update the document. Which might save someone else a lot of time 
debugging only to find out they've transposed some digits in the dts.

I'll whip something up and send it out shortly.

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#1572890

FromMichael Ellerman <mpe@ellerman.id.au>
Date2017-02-03 06:20 +0100
Message-ID<t6ErT-5C9-9@gated-at.bofh.it>
In reply to#1572825
Chris Packham <Chris.Packham@alliedtelesis.co.nz> writes:

> On 03/02/17 12:55, Michael Ellerman wrote:
>> Chris if you want to send a patch to add the compatible string to the
>> l2cache.txt I would merge that, but honestly it doesn't achieve much
>> other than possibly catching a typo in the compatible name.
>
> I think catching a typo might be worthwhile. It's 5 minutes work for me 
> to grep/sed through the code to find existing compatible strings and 
> update the document. Which might save someone else a lot of time 
> debugging only to find out they've transposed some digits in the dts.
>
> I'll whip something up and send it out shortly.

Thanks.

cheers

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#1572970

FromBorislav Petkov <bp@alien8.de>
Date2017-02-03 10:50 +0100
Message-ID<t6IFc-8jr-5@gated-at.bofh.it>
In reply to#1572816
On Fri, Feb 03, 2017 at 10:55:33AM +1100, Michael Ellerman wrote:
> > So I'd like to have an ACK from a PPC maintainer here first before I
> > apply this.
> 
> It's fine with me:
> 
> Acked-by: Michael Ellerman <mpe@ellerman.id.au>

Applied,
thanks guys.

-- 
Regards/Gruss,
    Boris.

Good mailing practices for 400: avoid top-posting and trim the reply.

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