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Re: Cherryview wake up events

Started byJohannes Stezenbach <js@sig21.net>
First post2017-01-24 11:30 +0100
Last post2017-02-09 10:50 +0100
Articles 20 on this page of 30 — 3 participants

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  Re: Cherryview wake up events Johannes Stezenbach <js@sig21.net> - 2017-01-24 11:30 +0100
    Re: Cherryview wake up events Andy Shevchenko <andy.shevchenko@gmail.com> - 2017-01-24 12:20 +0100
      Re: Cherryview wake up events Johannes Stezenbach <js@sig21.net> - 2017-01-24 15:00 +0100
        Re: Cherryview wake up events Andy Shevchenko <andy.shevchenko@gmail.com> - 2017-01-24 15:30 +0100
          Re: Cherryview wake up events Johannes Stezenbach <js@sig21.net> - 2017-01-24 20:30 +0100
            Re: Cherryview wake up events Mika Westerberg <mika.westerberg@linux.intel.com> - 2017-01-25 10:40 +0100
            Re: Cherryview wake up events Andy Shevchenko <andy.shevchenko@gmail.com> - 2017-01-27 00:00 +0100
              Re: Cherryview wake up events Johannes Stezenbach <js@sig21.net> - 2017-01-27 12:40 +0100
                Re: Cherryview wake up events Andy Shevchenko <andy.shevchenko@gmail.com> - 2017-01-27 14:30 +0100
                  Re: Cherryview wake up events Johannes Stezenbach <js@sig21.net> - 2017-01-27 14:40 +0100
                    Re: Cherryview wake up events Johannes Stezenbach <js@sig21.net> - 2017-01-30 22:00 +0100
                      Re: Cherryview wake up events Andy Shevchenko <andy.shevchenko@gmail.com> - 2017-01-30 23:10 +0100
                        Re: Cherryview wake up events Mika Westerberg <mika.westerberg@linux.intel.com> - 2017-01-31 15:50 +0100
                        Re: Cherryview wake up events Johannes Stezenbach <js@sig21.net> - 2017-01-31 15:50 +0100
                          Re: Cherryview wake up events Johannes Stezenbach <js@sig21.net> - 2017-02-02 11:00 +0100
                            Re: Cherryview wake up events Mika Westerberg <mika.westerberg@linux.intel.com> - 2017-02-02 11:40 +0100
                              Re: Cherryview wake up events Johannes Stezenbach <js@sig21.net> - 2017-02-02 12:20 +0100
                                Re: Cherryview wake up events Mika Westerberg <mika.westerberg@linux.intel.com> - 2017-02-02 12:40 +0100
                                  Re: Cherryview wake up events Mika Westerberg <mika.westerberg@linux.intel.com> - 2017-02-02 13:20 +0100
                                    Re: Cherryview wake up events Johannes Stezenbach <js@sig21.net> - 2017-02-02 15:00 +0100
                                      Re: Cherryview wake up events Mika Westerberg <mika.westerberg@linux.intel.com> - 2017-02-02 15:30 +0100
                                        Re: Cherryview wake up events Johannes Stezenbach <js@sig21.net> - 2017-02-02 15:40 +0100
                                          Re: Cherryview wake up events Mika Westerberg <mika.westerberg@linux.intel.com> - 2017-02-02 16:10 +0100
                                            Re: Cherryview wake up events Johannes Stezenbach <js@sig21.net> - 2017-02-02 16:50 +0100
                                              Re: Cherryview wake up events Mika Westerberg <mika.westerberg@linux.intel.com> - 2017-02-02 17:00 +0100
                                                Re: Cherryview wake up events Johannes Stezenbach <js@sig21.net> - 2017-02-02 18:40 +0100
                                                  Re: Cherryview wake up events Mika Westerberg <mika.westerberg@linux.intel.com> - 2017-02-03 11:10 +0100
                                                    Re: Cherryview wake up events Johannes Stezenbach <js@sig21.net> - 2017-02-03 14:20 +0100
                                                Re: Cherryview wake up events Johannes Stezenbach <js@sig21.net> - 2017-02-09 10:30 +0100
                                                  Re: Cherryview wake up events Mika Westerberg <mika.westerberg@linux.intel.com> - 2017-02-09 10:50 +0100

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#1565767 — Re: Cherryview wake up events

FromJohannes Stezenbach <js@sig21.net>
Date2017-01-24 11:30 +0100
SubjectRe: Cherryview wake up events
Message-ID<t36wr-34u-33@gated-at.bofh.it>
Hi,

On Mon, Dec 05, 2016 at 01:06:08PM +0200, Mika Westerberg wrote:
> On Sun, Dec 04, 2016 at 07:52:19PM +0100, Johannes Stezenbach wrote:
> > On Wed, Oct 05, 2016 at 04:05:11PM +0300, Mika Westerberg wrote:
> > > On Wed, Oct 05, 2016 at 02:46:48PM +0200, Johannes Stezenbach wrote:
> > > > On Fri, Sep 23, 2016 at 11:19:04AM +0300, Mika Westerberg wrote:
> > > > > David (CC'd) is working on getting the Dollar Cove PMIC driver
> > > > > upstreamed to the mainline kernel.
> > > > 
> > > > May I ask when to expect a patch?  I'm ready if you
> > > > have something to test, even if it's not in
> > > > shape for mainline yet.
> > > 
> > > It typically takes quite some time to get all the legal stuff done
> > > before the code can be published. And if people are busy with other
> > > things it takes even more time.
> > > 
> > > So please be patient, it will happen sooner or later ;-)
> > 
> > I don't want to nag, but just so it doesn't drop off
> > the TODO list due to "lack of interest":  What's the
> > status?  Will Santa bring the the TI Dollar Cove PMIC driver?
> 
> David, do you have any estimate?


Meanwhile I found out the TI PMIC and power button drivers
has been published as part of the Asus ZenFone Zoom (ZX551ML)
Android kernel code drop (based on linux-3.10.x):

https://www.asus.com/support/Download/39/1/0/26/BXbNqJplzZiLmk6G/32/

Please let me know if there is anything I could do
to help get it mainlined soon.


Thanks,
Johannes

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#1565787

FromAndy Shevchenko <andy.shevchenko@gmail.com>
Date2017-01-24 12:20 +0100
Message-ID<t37iO-3Bi-15@gated-at.bofh.it>
In reply to#1565767
On Tue, Jan 24, 2017 at 11:41 AM, Johannes Stezenbach <js@sig21.net> wrote:
> Hi,
>
> On Mon, Dec 05, 2016 at 01:06:08PM +0200, Mika Westerberg wrote:
>> On Sun, Dec 04, 2016 at 07:52:19PM +0100, Johannes Stezenbach wrote:
>> > On Wed, Oct 05, 2016 at 04:05:11PM +0300, Mika Westerberg wrote:
>> > > On Wed, Oct 05, 2016 at 02:46:48PM +0200, Johannes Stezenbach wrote:
>> > > > On Fri, Sep 23, 2016 at 11:19:04AM +0300, Mika Westerberg wrote:
>> > > > > David (CC'd) is working on getting the Dollar Cove PMIC driver
>> > > > > upstreamed to the mainline kernel.
>> > > >
>> > > > May I ask when to expect a patch?  I'm ready if you
>> > > > have something to test, even if it's not in
>> > > > shape for mainline yet.
>> > >
>> > > It typically takes quite some time to get all the legal stuff done
>> > > before the code can be published. And if people are busy with other
>> > > things it takes even more time.
>> > >
>> > > So please be patient, it will happen sooner or later ;-)
>> >
>> > I don't want to nag, but just so it doesn't drop off
>> > the TODO list due to "lack of interest":  What's the
>> > status?  Will Santa bring the the TI Dollar Cove PMIC driver?
>>
>> David, do you have any estimate?
>
>
> Meanwhile I found out the TI PMIC and power button drivers
> has been published as part of the Asus ZenFone Zoom (ZX551ML)
> Android kernel code drop (based on linux-3.10.x):
>
> https://www.asus.com/support/Download/39/1/0/26/BXbNqJplzZiLmk6G/32/
>
> Please let me know if there is anything I could do
> to help get it mainlined soon.

AFAIK ASuS Zenfone 2 (Intel based) series uses Intel Moorefield. It
has ShadyCove PMIC.

-- 
With Best Regards,
Andy Shevchenko

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#1565876

FromJohannes Stezenbach <js@sig21.net>
Date2017-01-24 15:00 +0100
Message-ID<t39NE-4ZI-33@gated-at.bofh.it>
In reply to#1565787
On Tue, Jan 24, 2017 at 01:14:16PM +0200, Andy Shevchenko wrote:
> On Tue, Jan 24, 2017 at 11:41 AM, Johannes Stezenbach <js@sig21.net> wrote:
> > Meanwhile I found out the TI PMIC and power button drivers
> > has been published as part of the Asus ZenFone Zoom (ZX551ML)
> > Android kernel code drop (based on linux-3.10.x):
> >
> > https://www.asus.com/support/Download/39/1/0/26/BXbNqJplzZiLmk6G/32/
> >
> > Please let me know if there is anything I could do
> > to help get it mainlined soon.
> 
> AFAIK ASuS Zenfone 2 (Intel based) series uses Intel Moorefield. It
> has ShadyCove PMIC.

So Asus released more than they needed.  I confirmed their
source drop contains the TI Dollar Cove driver (dollar_cove_ti.c).
iPreviously I searched for Android devices using CherryView but the
only one I could find is Xioami MiPad 2 and it's released
kernel source doesn't contain the driver.

Anyway, let me know if I can help to get it into mainline soon.


Johannes

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#1565895

FromAndy Shevchenko <andy.shevchenko@gmail.com>
Date2017-01-24 15:30 +0100
Message-ID<t3agF-5pf-3@gated-at.bofh.it>
In reply to#1565876
On Tue, Jan 24, 2017 at 3:52 PM, Johannes Stezenbach <js@sig21.net> wrote:
> On Tue, Jan 24, 2017 at 01:14:16PM +0200, Andy Shevchenko wrote:
>> On Tue, Jan 24, 2017 at 11:41 AM, Johannes Stezenbach <js@sig21.net> wrote:
>> > Meanwhile I found out the TI PMIC and power button drivers
>> > has been published as part of the Asus ZenFone Zoom (ZX551ML)
>> > Android kernel code drop (based on linux-3.10.x):
>> >
>> > https://www.asus.com/support/Download/39/1/0/26/BXbNqJplzZiLmk6G/32/
>> >
>> > Please let me know if there is anything I could do
>> > to help get it mainlined soon.
>>
>> AFAIK ASuS Zenfone 2 (Intel based) series uses Intel Moorefield. It
>> has ShadyCove PMIC.
>
> So Asus released more than they needed.  I confirmed their
> source drop contains the TI Dollar Cove driver (dollar_cove_ti.c).

They probably release just almost all One Big Ugly patch from official
BSP, which by some reason, includes all Intel MID SoCs, Baytrail.
I think I know how Dollar Cove related code ended up there. But that
all stuff is a total mess.

> Anyway, let me know if I can help to get it into mainline soon.

-- 
With Best Regards,
Andy Shevchenko

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#1566079

FromJohannes Stezenbach <js@sig21.net>
Date2017-01-24 20:30 +0100
Message-ID<t3eWZ-8j5-5@gated-at.bofh.it>
In reply to#1565895
On Tue, Jan 24, 2017 at 04:28:29PM +0200, Andy Shevchenko wrote:
> They probably release just almost all One Big Ugly patch from official
> BSP, which by some reason, includes all Intel MID SoCs, Baytrail.
> I think I know how Dollar Cove related code ended up there. But that
> all stuff is a total mess.

I agree.  Probably it was a mistake to bring up this code here.
Let me try to go back two steps:  Could you please let me
know if there is any progress in mainlining the TI Dollar Cove PMIC
and related drivers?  Is there a schedule?
After waiting for four months I'm actually getting impatient
because by now the Cherryview based hardware seems to go out
of production and I fear the mainlining might never happen.

Thanks,
Johannes

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#1566418

FromMika Westerberg <mika.westerberg@linux.intel.com>
Date2017-01-25 10:40 +0100
Message-ID<t3sdA-8r2-47@gated-at.bofh.it>
In reply to#1566079
On Tue, Jan 24, 2017 at 08:23:14PM +0100, Johannes Stezenbach wrote:
> On Tue, Jan 24, 2017 at 04:28:29PM +0200, Andy Shevchenko wrote:
> > They probably release just almost all One Big Ugly patch from official
> > BSP, which by some reason, includes all Intel MID SoCs, Baytrail.
> > I think I know how Dollar Cove related code ended up there. But that
> > all stuff is a total mess.
> 
> I agree.  Probably it was a mistake to bring up this code here.
> Let me try to go back two steps:  Could you please let me
> know if there is any progress in mainlining the TI Dollar Cove PMIC
> and related drivers?  Is there a schedule?

David, can you please answer this!

> After waiting for four months I'm actually getting impatient
> because by now the Cherryview based hardware seems to go out
> of production and I fear the mainlining might never happen.

If we hear nothing from David soon, I think I'll just take it to my
growing todo list. Unless someone else wants to take it.

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#1567786

FromAndy Shevchenko <andy.shevchenko@gmail.com>
Date2017-01-27 00:00 +0100
Message-ID<t41bj-4KV-5@gated-at.bofh.it>
In reply to#1566079
On Tue, Jan 24, 2017 at 9:23 PM, Johannes Stezenbach <js@sig21.net> wrote:
> On Tue, Jan 24, 2017 at 04:28:29PM +0200, Andy Shevchenko wrote:
>> They probably release just almost all One Big Ugly patch from official
>> BSP, which by some reason, includes all Intel MID SoCs, Baytrail.
>> I think I know how Dollar Cove related code ended up there. But that
>> all stuff is a total mess.

I'm reading your long thread about the issue.

> but excluded CONFIG_MFD_AXP20X based on \_SB.PIC0.I2C7.PMI1._STA returning 0 in acpidbg,
> but \_SB.PIC0.I2C7.PMI1._STA returns 0xf

Did you mean PMI2 in the second sentence?
Had you tried to add ID to axp20x-i2c.c ?

> Repeating essential info to avoid any confusion, the PMIC is

In code you found there are two DCove drivers :-) One with "ti" suffix.


-- 
With Best Regards,
Andy Shevchenko

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#1568193

FromJohannes Stezenbach <js@sig21.net>
Date2017-01-27 12:40 +0100
Message-ID<t4d2N-3w5-3@gated-at.bofh.it>
In reply to#1567786
On Fri, Jan 27, 2017 at 12:56:53AM +0200, Andy Shevchenko wrote:
> 
> I'm reading your long thread about the issue.

Thanks for taking the time!

> > but excluded CONFIG_MFD_AXP20X based on \_SB.PIC0.I2C7.PMI1._STA returning 0 in acpidbg,
> > but \_SB.PIC0.I2C7.PMI1._STA returns 0xf
> 
> Did you mean PMI2 in the second sentence?

Yes, sorry for copy & paste mistake.  I just repated to confirm:
In acpidbg:

- execute \_SB.PCI0.I2C7.PMI1._STA
Evaluating \_SB.PCI0.I2C7.PMI1._STA
Evaluation of \_SB.PCI0.I2C7.PMI1._STA returned object ffffa14a67420000, external buffer length 18
 [Integer] = 0000000000000000

- execute \_SB.PCI0.I2C7.PMI2._STA
Evaluating \_SB.PCI0.I2C7.PMI2._STA
Evaluation of \_SB.PCI0.I2C7.PMI2._STA returned object ffffa14a67420000, external buffer length 18
 [Integer] = 000000000000000F

And the same info is also in sysfs:

# cat /sys/devices/LNXSYSTM\:00/LNXSYBUS\:00/PNP0A08\:00/808622C1\:06/INT33F4\:00/status

0
# cat /sys/devices/LNXSYSTM\:00/LNXSYBUS\:00/PNP0A08\:00/808622C1\:06/INT33F5\:00/status
15

The DSDT is still at https://linuxtv.org/~js/e200ha/

> Had you tried to add ID to axp20x-i2c.c ?

Nope, since I have no idea if the axp and TI hardware is similar.

There might be more issues, currently the machine hangs often
during bootup at random points.  I built i915 as a module and
blacklisted it for autoloading so I can read the last message
on the console.  All I can say is that it is more likely to
hang when the loglevel is high, i.e. it almost never succeeds
with "debug" on kernel command line.  Sometimes there are
timeout errors from I2C:
[    4.307189] i2c_designware 808622C1:06: controller timed out
[    5.331709] i2c_designware 808622C1:06: controller timed out

Once it has booted it is running stable.


Thanks,
Johannes

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#1568353

FromAndy Shevchenko <andy.shevchenko@gmail.com>
Date2017-01-27 14:30 +0100
Message-ID<t4eLf-4FD-9@gated-at.bofh.it>
In reply to#1568193
On Fri, Jan 27, 2017 at 1:38 PM, Johannes Stezenbach <js@sig21.net> wrote:
> On Fri, Jan 27, 2017 at 12:56:53AM +0200, Andy Shevchenko wrote:

> And the same info is also in sysfs:
>
> # cat /sys/devices/LNXSYSTM\:00/LNXSYBUS\:00/PNP0A08\:00/808622C1\:06/INT33F4\:00/status
> 0
> # cat /sys/devices/LNXSYSTM\:00/LNXSYBUS\:00/PNP0A08\:00/808622C1\:06/INT33F5\:00/status
> 15
>
> The DSDT is still at https://linuxtv.org/~js/e200ha/
>
>> Had you tried to add ID to axp20x-i2c.c ?
>
> Nope, since I have no idea if the axp and TI hardware is similar.

I think you would give a try.

> There might be more issues, currently the machine hangs often
> during bootup at random points.  I built i915 as a module and
> blacklisted it for autoloading so I can read the last message
> on the console.  All I can say is that it is more likely to
> hang when the loglevel is high, i.e. it almost never succeeds
> with "debug" on kernel command line.  Sometimes there are
> timeout errors from I2C:
> [    4.307189] i2c_designware 808622C1:06: controller timed out
> [    5.331709] i2c_designware 808622C1:06: controller timed out
>
> Once it has booted it is running stable.

This is known: http://www.spinics.net/lists/intel-gfx/msg117738.html

-- 
With Best Regards,
Andy Shevchenko

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#1568368

FromJohannes Stezenbach <js@sig21.net>
Date2017-01-27 14:40 +0100
Message-ID<t4eUX-4Ja-41@gated-at.bofh.it>
In reply to#1568353
On Fri, Jan 27, 2017 at 03:21:22PM +0200, Andy Shevchenko wrote:
> On Fri, Jan 27, 2017 at 1:38 PM, Johannes Stezenbach <js@sig21.net> wrote:
> > On Fri, Jan 27, 2017 at 12:56:53AM +0200, Andy Shevchenko wrote:
> 
> > And the same info is also in sysfs:
> >
> > # cat /sys/devices/LNXSYSTM\:00/LNXSYBUS\:00/PNP0A08\:00/808622C1\:06/INT33F4\:00/status
> > 0
> > # cat /sys/devices/LNXSYSTM\:00/LNXSYBUS\:00/PNP0A08\:00/808622C1\:06/INT33F5\:00/status
> > 15
> >
> > The DSDT is still at https://linuxtv.org/~js/e200ha/
> >
> >> Had you tried to add ID to axp20x-i2c.c ?
> >
> > Nope, since I have no idea if the axp and TI hardware is similar.
> 
> I think you would give a try.

I'll check it.

> > There might be more issues, currently the machine hangs often
> > during bootup at random points.  I built i915 as a module and
> > blacklisted it for autoloading so I can read the last message
> > on the console.  All I can say is that it is more likely to
> > hang when the loglevel is high, i.e. it almost never succeeds
> > with "debug" on kernel command line.  Sometimes there are
> > timeout errors from I2C:
> > [    4.307189] i2c_designware 808622C1:06: controller timed out
> > [    5.331709] i2c_designware 808622C1:06: controller timed out
> >
> > Once it has booted it is running stable.
> 
> This is known: http://www.spinics.net/lists/intel-gfx/msg117738.html

Not sure because it happens with i915 module not loaded
(currently I load it manually after boot completed).
But thanks for the link.

Johannes

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#1570118

FromJohannes Stezenbach <js@sig21.net>
Date2017-01-30 22:00 +0100
Message-ID<t5rdo-bx-7@gated-at.bofh.it>
In reply to#1568368
On Fri, Jan 27, 2017 at 02:30:58PM +0100, Johannes Stezenbach wrote:
> On Fri, Jan 27, 2017 at 03:21:22PM +0200, Andy Shevchenko wrote:
> > On Fri, Jan 27, 2017 at 1:38 PM, Johannes Stezenbach <js@sig21.net> wrote:
> > > On Fri, Jan 27, 2017 at 12:56:53AM +0200, Andy Shevchenko wrote:
> > 
> > >> Had you tried to add ID to axp20x-i2c.c ?
> > >
> > > Nope, since I have no idea if the axp and TI hardware is similar.
> > 
> > I think you would give a try.
> 
> I'll check it.

I checked the reference source code, my impression is the
TI Dollar Cove and and AXP288 are completely different hardware.

> > > [    5.331709] i2c_designware 808622C1:06: controller timed out
> > >
> > This is known: http://www.spinics.net/lists/intel-gfx/msg117738.html

Interestingly via this link I found Intel also published
the TI DCove source in a patch series against an unspecified kernel:
https://github.com/01org/ProductionKernelQuilts
specifically
https://github.com/01org/ProductionKernelQuilts/blob/master/uefi/cht-m1stable/patches/mfd-intel_soc_pmic-add-TI-variant-of-dollar-cove.patch
https://github.com/01org/ProductionKernelQuilts/blob/master/uefi/cht-m1stable/patches/PWRBTN-add-driver-for-TI-PMIC.patch
and some more (the series is quite messy).

For the Asus E200HA I'm not sure if the charger and coulomb
counter drivers are needed since charging just works and
the battery status is reported via ACPI.  It seems these
drivers are only for tablets without ACPI support, right?


Thanks,
Johannes

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#1570145

FromAndy Shevchenko <andy.shevchenko@gmail.com>
Date2017-01-30 23:10 +0100
Message-ID<t5sj8-12l-21@gated-at.bofh.it>
In reply to#1570118
On Mon, Jan 30, 2017 at 10:57 PM, Johannes Stezenbach <js@sig21.net> wrote:
> On Fri, Jan 27, 2017 at 02:30:58PM +0100, Johannes Stezenbach wrote:
>> On Fri, Jan 27, 2017 at 03:21:22PM +0200, Andy Shevchenko wrote:
>> > On Fri, Jan 27, 2017 at 1:38 PM, Johannes Stezenbach <js@sig21.net> wrote:
>> > > On Fri, Jan 27, 2017 at 12:56:53AM +0200, Andy Shevchenko wrote:
>> >
>> > >> Had you tried to add ID to axp20x-i2c.c ?
>> > >
>> > > Nope, since I have no idea if the axp and TI hardware is similar.
>> >
>> > I think you would give a try.
>>
>> I'll check it.
>
> I checked the reference source code, my impression is the
> TI Dollar Cove and and AXP288 are completely different hardware.

Thanks for checking.

Yes, due to not obvious communication to PMIC. I suppose that the IP
core is quite similar in all of them, the difference is just how OS
and other MCUs in SoC communicate with it.

So, basically what it means that I2C direct communication is prohibited here.

>
>> > > [    5.331709] i2c_designware 808622C1:06: controller timed out
>> > >
>> > This is known: http://www.spinics.net/lists/intel-gfx/msg117738.html
>
> Interestingly via this link I found Intel also published
> the TI DCove source in a patch series against an unspecified kernel:
> https://github.com/01org/ProductionKernelQuilts
> specifically
> https://github.com/01org/ProductionKernelQuilts/blob/master/uefi/cht-m1stable/patches/mfd-intel_soc_pmic-add-TI-variant-of-dollar-cove.patch
> https://github.com/01org/ProductionKernelQuilts/blob/master/uefi/cht-m1stable/patches/PWRBTN-add-driver-for-TI-PMIC.patch
> and some more (the series is quite messy).
>
> For the Asus E200HA I'm not sure if the charger and coulomb
> counter drivers are needed since charging just works and
> the battery status is reported via ACPI.  It seems these
> drivers are only for tablets without ACPI support, right?

Have no idea.

What that code reminds me is MID family of devices. So, power button
is (reasonable) easy to get support of in that case.
Look into drivers/platform/x86/intel_mid_powerbtn.c. I recently
updated it to support Basin Cove on Intel Edison.

-- 
With Best Regards,
Andy Shevchenko

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#1570793

FromMika Westerberg <mika.westerberg@linux.intel.com>
Date2017-01-31 15:50 +0100
Message-ID<t5HUR-1S1-3@gated-at.bofh.it>
In reply to#1570145
On Tue, Jan 31, 2017 at 03:37:40PM +0100, Johannes Stezenbach wrote:
> You seem to suggest I should try and tackle it myself,
> which I would do, but for one I don't want to step on
> Mika's toes

Trust me, you don't step on my toes if you want to handle this yourself :)

But if noone else is going to anything about this, I'll then put it to
my todo list and work on it when I have some spare time. Currently busy
with some other things, though.

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#1570798

FromJohannes Stezenbach <js@sig21.net>
Date2017-01-31 15:50 +0100
Message-ID<t5HUR-1S1-5@gated-at.bofh.it>
In reply to#1570145
Hi Andy and Mika,

On Tue, Jan 31, 2017 at 12:05:07AM +0200, Andy Shevchenko wrote:
> On Mon, Jan 30, 2017 at 10:57 PM, Johannes Stezenbach <js@sig21.net> wrote:
> >
> > I checked the reference source code, my impression is the
> > TI Dollar Cove and and AXP288 are completely different hardware.
> 
> Thanks for checking.
> 
> Yes, due to not obvious communication to PMIC. I suppose that the IP
> core is quite similar in all of them, the difference is just how OS
> and other MCUs in SoC communicate with it.
> 
> So, basically what it means that I2C direct communication is prohibited here.

Not sure about that, but I guess this is needed:
https://lists.freedesktop.org/archives/intel-gfx/2017-January/117696.html

> >> > This is known: http://www.spinics.net/lists/intel-gfx/msg117738.html
> >
> > Interestingly via this link I found Intel also published
> > the TI DCove source in a patch series against an unspecified kernel:
> > https://github.com/01org/ProductionKernelQuilts
> > specifically
> > https://github.com/01org/ProductionKernelQuilts/blob/master/uefi/cht-m1stable/patches/mfd-intel_soc_pmic-add-TI-variant-of-dollar-cove.patch
> > https://github.com/01org/ProductionKernelQuilts/blob/master/uefi/cht-m1stable/patches/PWRBTN-add-driver-for-TI-PMIC.patch
> > and some more (the series is quite messy).

FWIW, now I came across yet another source for this driver:
https://android.googlesource.com/kernel/x86/+/android-x86-grant-3.10-marshmallow-mr1-wear-release/drivers/external_drivers/drivers/mfd/intel_pmic/
(but seems to be older)

> > For the Asus E200HA I'm not sure if the charger and coulomb
> > counter drivers are needed since charging just works and
> > the battery status is reported via ACPI.  It seems these
> > drivers are only for tablets without ACPI support, right?
> 
> Have no idea.
> 
> What that code reminds me is MID family of devices. So, power button
> is (reasonable) easy to get support of in that case.
> Look into drivers/platform/x86/intel_mid_powerbtn.c. I recently
> updated it to support Basin Cove on Intel Edison.

You seem to suggest I should try and tackle it myself,
which I would do, but for one I don't want to step on
Mika's toes, secondly ISTR you indicated you have newer,
better source than what is available publicly?
If you want me to take it, please let me know which tree
to work against and any other suggestions you have.

Some more questions:
- Powerbutton driver seems simple enough, the only specialty
  of the TI dcove PB driver is the workarond for lost button
  press event after resume.  However, I still don't see how
  the PB would cause thermal event irqs on E200HA and how the
  PMIC driver would change it?
- Wakeup from freeze state (E200HA doesn't support suspend / ACPI S3)
  is only step 1, to make it usable we need S0ix support.
  Any hints about that?

I think the mfd driver would be similar to intel_soc_pmic_crc.c,
the dollar_cove_ti_powerbtn.c I would keep instead of merging
it into intel_mid_powerbtn.c.  I guess what we need is in
drivers/acpi/pmic/ something similar to intel_pmic_crc.c,
the ProductionKernelQuilts has 0001-ACPI-Adding-support-for-TI-pmic-opregion.patch.


Thanks,
Johannes

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#1572236

FromJohannes Stezenbach <js@sig21.net>
Date2017-02-02 11:00 +0100
Message-ID<t6mlk-2a2-11@gated-at.bofh.it>
In reply to#1570798
Hi Mika,

On Tue, Jan 31, 2017 at 03:37:40PM +0100, Johannes Stezenbach wrote:
> - Powerbutton driver seems simple enough, the only specialty
>   of the TI dcove PB driver is the workarond for lost button
>   press event after resume.  However, I still don't see how
>   the PB would cause thermal event irqs on E200HA and how the
>   PMIC driver would change it?

In ProductionKernelQuilts I found
DC-TI-PMIC-disable-power-button-support.patch so I guess it
might not be needed because it's probably handled by ACPI.

> I think the mfd driver would be similar to intel_soc_pmic_crc.c,
> the dollar_cove_ti_powerbtn.c I would keep instead of merging
> it into intel_mid_powerbtn.c.  I guess what we need is in
> drivers/acpi/pmic/ something similar to intel_pmic_crc.c,
> the ProductionKernelQuilts has 0001-ACPI-Adding-support-for-TI-pmic-opregion.patch.

I have preliminary versions of the mfd and opregion driver,
while testing I found the GPIO opregion is not registered:

Excerpt from DSDT:
https://linuxtv.org/~js/e200ha/dsdt.dsl

            Device (PMI2)
            {
                Name (_ADR, Zero)  // _ADR: Address
                Name (_HID, "INT33F5" /* TI PMIC Controller */)  // _HID: Hardware ID
                Name (_CID, "INT33F5" /* TI PMIC Controller */)  // _CID: Compatible ID
                Name (_DDN, "TI PMIC Controller")  // _DDN: DOS Device Name
                Name (_HRV, 0x03)  // _HRV: Hardware Revision
                Name (_UID, One)  // _UID: Unique ID
                Name (_DEP, Package (0x02)  // _DEP: Dependencies
                {
                    I2C7, 
                    GPO1
                })
                Method (_CRS, 0, NotSerialized)  // _CRS: Current Resource Settings
                {
                    Name (SBUF, ResourceTemplate ()
                    {
                        I2cSerialBusV2 (0x005E, ControllerInitiated, 0x000F4240,
                            AddressingMode7Bit, "\\_SB.PCI0.I2C7",
                            0x00, ResourceConsumer, , Exclusive,
                            )
                        GpioInt (Level, ActiveHigh, Shared, PullDefault, 0x0000,
                            "\\_SB.GPO1", 0x00, ResourceConsumer, ,
                            )
                            {   // Pin list
                                0x000F
                            }
                    })
                    Return (SBUF) /* \_SB_.PCI0.I2C7.PMI2._CRS.SBUF */
                }
...
                Name (AVBL, Zero)
                Name (AVBD, Zero)
                Name (AVBG, Zero)
                Method (_REG, 2, NotSerialized)  // _REG: Region Availability
                {
                    If (Arg0 == 0x08)
                    {
                        AVBG = Arg1
                    }

                    If (Arg0 == 0x8D)
                    {
                        AVBL = Arg1
                    }

                    If (Arg0 == 0x8C)
                    {
                        AVBD = Arg1
                    }
                }


acpidbg:
        \_SB.PCI0.I2C7.PMI2.AVBL Integer      ffff8be7b74d97a8 01 = 0000000000000001
        \_SB.PCI0.I2C7.PMI2.AVBD Integer      ffff8be7b74d94d8 01 = 0000000000000001
        \_SB.PCI0.I2C7.PMI2.AVBG Integer      ffff8be7b74d9be0 01 = 0000000000000000

Any idea about it?
devm_gpiochip_add_data() in chv_gpio_probe() indirectly calls acpi_gpiochip_add()
which should use _DEP to figure out to call _REG, right?

Also PMI2 has

                OperationRegion (GPOP, GeneralPurposeIo, Zero, 0x0100)
                Field (GPOP, ByteAcc, NoLock, Preserve)
                {
                    Connection (
                        GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, IoRestrictionOutputOnly,
                            "\\_SB.PCI0.I2C7.PMI2", 0x00, ResourceConsumer, ,
                            )
                            {   // Pin list
                                0x0020
                            }
                    ), 
                    GMP0,   1, 
                    ...
                    (repeat for many more pins)

I guess it means it uses chv_gpio pins and can't work
if the GPIO opregion is not registered?


FWIW, with the mfd driver, /proc/interrupts has

 180:          0          0          0          0  chv-gpio    9  TI Dollar Cove

I guess the 9 refers to the 10th pin in north_pins[] which is pin 0x000F, right?
I boot with "dyndbg=file gpiolib* +p" and get

[  +0.012798] acpi INT33F5:00: GPIO: looking up 0 in _CRS
[  +0.000214] intel_soc_pmic_i2c i2c-INT33F5:00: GPIO lookup for consumer intel_soc_pmic
[  +0.000003] intel_soc_pmic_i2c i2c-INT33F5:00: using ACPI for GPIO lookup
[  +0.000005] acpi INT33F5:00: GPIO: looking up intel_soc_pmic-gpios
[  +0.000005] acpi INT33F5:00: GPIO: looking up intel_soc_pmic-gpio
[  +0.000005] acpi INT33F5:00: GPIO: looking up 0 in _CRS
[  +0.000091] cherryview-pinctrl INT33FF:01: request pin 15 (GPIO_SUS0) for INT33FF:01:406

but so far the irq never triggers.


Thanks
Johannes

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#1572258

FromMika Westerberg <mika.westerberg@linux.intel.com>
Date2017-02-02 11:40 +0100
Message-ID<t6mY1-2GK-1@gated-at.bofh.it>
In reply to#1572236
On Thu, Feb 02, 2017 at 10:52:00AM +0100, Johannes Stezenbach wrote:
> Hi Mika,
> 
> On Tue, Jan 31, 2017 at 03:37:40PM +0100, Johannes Stezenbach wrote:
> > - Powerbutton driver seems simple enough, the only specialty
> >   of the TI dcove PB driver is the workarond for lost button
> >   press event after resume.  However, I still don't see how
> >   the PB would cause thermal event irqs on E200HA and how the
> >   PMIC driver would change it?
> 
> In ProductionKernelQuilts I found
> DC-TI-PMIC-disable-power-button-support.patch so I guess it
> might not be needed because it's probably handled by ACPI.
> 
> > I think the mfd driver would be similar to intel_soc_pmic_crc.c,
> > the dollar_cove_ti_powerbtn.c I would keep instead of merging
> > it into intel_mid_powerbtn.c.  I guess what we need is in
> > drivers/acpi/pmic/ something similar to intel_pmic_crc.c,
> > the ProductionKernelQuilts has 0001-ACPI-Adding-support-for-TI-pmic-opregion.patch.
> 
> I have preliminary versions of the mfd and opregion driver,
> while testing I found the GPIO opregion is not registered:

Cool, I take it that you started working on that ;-)

> Excerpt from DSDT:
> https://linuxtv.org/~js/e200ha/dsdt.dsl
> 
>             Device (PMI2)
>             {
>                 Name (_ADR, Zero)  // _ADR: Address
>                 Name (_HID, "INT33F5" /* TI PMIC Controller */)  // _HID: Hardware ID
>                 Name (_CID, "INT33F5" /* TI PMIC Controller */)  // _CID: Compatible ID
>                 Name (_DDN, "TI PMIC Controller")  // _DDN: DOS Device Name
>                 Name (_HRV, 0x03)  // _HRV: Hardware Revision
>                 Name (_UID, One)  // _UID: Unique ID
>                 Name (_DEP, Package (0x02)  // _DEP: Dependencies
>                 {
>                     I2C7, 
>                     GPO1
>                 })
>                 Method (_CRS, 0, NotSerialized)  // _CRS: Current Resource Settings
>                 {
>                     Name (SBUF, ResourceTemplate ()
>                     {
>                         I2cSerialBusV2 (0x005E, ControllerInitiated, 0x000F4240,
>                             AddressingMode7Bit, "\\_SB.PCI0.I2C7",
>                             0x00, ResourceConsumer, , Exclusive,
>                             )
>                         GpioInt (Level, ActiveHigh, Shared, PullDefault, 0x0000,
>                             "\\_SB.GPO1", 0x00, ResourceConsumer, ,
>                             )
>                             {   // Pin list
>                                 0x000F
>                             }
>                     })
>                     Return (SBUF) /* \_SB_.PCI0.I2C7.PMI2._CRS.SBUF */
>                 }
> ...
>                 Name (AVBL, Zero)
>                 Name (AVBD, Zero)
>                 Name (AVBG, Zero)
>                 Method (_REG, 2, NotSerialized)  // _REG: Region Availability
>                 {
>                     If (Arg0 == 0x08)
>                     {
>                         AVBG = Arg1
>                     }
> 
>                     If (Arg0 == 0x8D)
>                     {
>                         AVBL = Arg1
>                     }
> 
>                     If (Arg0 == 0x8C)
>                     {
>                         AVBD = Arg1
>                     }
>                 }
> 
> 
> acpidbg:
>         \_SB.PCI0.I2C7.PMI2.AVBL Integer      ffff8be7b74d97a8 01 = 0000000000000001
>         \_SB.PCI0.I2C7.PMI2.AVBD Integer      ffff8be7b74d94d8 01 = 0000000000000001
>         \_SB.PCI0.I2C7.PMI2.AVBG Integer      ffff8be7b74d9be0 01 = 0000000000000000
> 
> Any idea about it?
> devm_gpiochip_add_data() in chv_gpio_probe() indirectly calls acpi_gpiochip_add()
> which should use _DEP to figure out to call _REG, right?

Actually no, we don't support all _DEP in Linux yet. But that's not the
problem though. See below.

> Also PMI2 has
> 
>                 OperationRegion (GPOP, GeneralPurposeIo, Zero, 0x0100)
>                 Field (GPOP, ByteAcc, NoLock, Preserve)
>                 {
>                     Connection (
>                         GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, IoRestrictionOutputOnly,
>                             "\\_SB.PCI0.I2C7.PMI2", 0x00, ResourceConsumer, ,
>                             )
>                             {   // Pin list
>                                 0x0020
>                             }
>                     ), 
>                     GMP0,   1, 
>                     ...
>                     (repeat for many more pins)
> 
> I guess it means it uses chv_gpio pins and can't work
> if the GPIO opregion is not registered?

That is using GPIO pins of the PMI2 device - the PMIC GPIO driver, I
suppose.

So in addition to the PMIC MFD driver, you need to have a GPIO driver
for Dollar Cove (I guess the quilt patch series included that as well?).

If you look under the /sys/bus/acpi/devices/DEVICE, it should include
bunch of physical_nodeX links. Those are the subdevices of the MFD so
when the GPIO driver registers the GPIO core then automatically installs
GPIO OpRegion handler.

> FWIW, with the mfd driver, /proc/interrupts has
> 
>  180:          0          0          0          0  chv-gpio    9  TI Dollar Cove
> 
> I guess the 9 refers to the 10th pin in north_pins[] which is pin 0x000F, right?
> I boot with "dyndbg=file gpiolib* +p" and get
> 
> [  +0.012798] acpi INT33F5:00: GPIO: looking up 0 in _CRS
> [  +0.000214] intel_soc_pmic_i2c i2c-INT33F5:00: GPIO lookup for consumer intel_soc_pmic
> [  +0.000003] intel_soc_pmic_i2c i2c-INT33F5:00: using ACPI for GPIO lookup
> [  +0.000005] acpi INT33F5:00: GPIO: looking up intel_soc_pmic-gpios
> [  +0.000005] acpi INT33F5:00: GPIO: looking up intel_soc_pmic-gpio
> [  +0.000005] acpi INT33F5:00: GPIO: looking up 0 in _CRS
> [  +0.000091] cherryview-pinctrl INT33FF:01: request pin 15 (GPIO_SUS0) for INT33FF:01:406
> 
> but so far the irq never triggers.

Probably because the PMIC does not have anything to report yet. When you
add the DCOVE GPIO driver, and start receiving input events from the
button array, then you should see that interrupt count increasing. If
everything works correctly.

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#1572281

FromJohannes Stezenbach <js@sig21.net>
Date2017-02-02 12:20 +0100
Message-ID<t6nAJ-3eT-7@gated-at.bofh.it>
In reply to#1572258
On Thu, Feb 02, 2017 at 12:31:22PM +0200, Mika Westerberg wrote:
> On Thu, Feb 02, 2017 at 10:52:00AM +0100, Johannes Stezenbach wrote:
> >                 OperationRegion (GPOP, GeneralPurposeIo, Zero, 0x0100)
> >                 Field (GPOP, ByteAcc, NoLock, Preserve)
> >                 {
> >                     Connection (
> >                         GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, IoRestrictionOutputOnly,
> >                             "\\_SB.PCI0.I2C7.PMI2", 0x00, ResourceConsumer, ,
> >                             )
> >                             {   // Pin list
> >                                 0x0020
> >                             }
> >                     ), 
> >                     GMP0,   1, 
> >                     ...
> >                     (repeat for many more pins)
> > 
> > I guess it means it uses chv_gpio pins and can't work
> > if the GPIO opregion is not registered?
> 
> That is using GPIO pins of the PMI2 device - the PMIC GPIO driver, I
> suppose.
> 
> So in addition to the PMIC MFD driver, you need to have a GPIO driver
> for Dollar Cove (I guess the quilt patch series included that as well?).

Nope, I see it for AX288 but didn't find it for TI DCove.  And in
current Linus' tree axp288_cells[] doesn't include gpio so
I concluded it's not needed... what am I missing?


Thanks,
Johannes

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#1572295

FromMika Westerberg <mika.westerberg@linux.intel.com>
Date2017-02-02 12:40 +0100
Message-ID<t6nU6-3lz-29@gated-at.bofh.it>
In reply to#1572281
On Thu, Feb 02, 2017 at 12:12:22PM +0100, Johannes Stezenbach wrote:
> On Thu, Feb 02, 2017 at 12:31:22PM +0200, Mika Westerberg wrote:
> > On Thu, Feb 02, 2017 at 10:52:00AM +0100, Johannes Stezenbach wrote:
> > >                 OperationRegion (GPOP, GeneralPurposeIo, Zero, 0x0100)
> > >                 Field (GPOP, ByteAcc, NoLock, Preserve)
> > >                 {
> > >                     Connection (
> > >                         GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, IoRestrictionOutputOnly,
> > >                             "\\_SB.PCI0.I2C7.PMI2", 0x00, ResourceConsumer, ,
> > >                             )
> > >                             {   // Pin list
> > >                                 0x0020
> > >                             }
> > >                     ), 
> > >                     GMP0,   1, 
> > >                     ...
> > >                     (repeat for many more pins)
> > > 
> > > I guess it means it uses chv_gpio pins and can't work
> > > if the GPIO opregion is not registered?
> > 
> > That is using GPIO pins of the PMI2 device - the PMIC GPIO driver, I
> > suppose.
> > 
> > So in addition to the PMIC MFD driver, you need to have a GPIO driver
> > for Dollar Cove (I guess the quilt patch series included that as well?).
> 
> Nope, I see it for AX288 but didn't find it for TI DCove.  And in
> current Linus' tree axp288_cells[] doesn't include gpio so
> I concluded it's not needed... what am I missing?

So reading your DSDT there is that GPIO button array device \_SB.TBAD
which has one GpioInt() referencing \_SB.PCI0.I2C7.PMI2. I suppose that
is the power button GPIO.

In order to use that there needs to be a GPIO driver exposing those
GPIOs to other drivers. So it is definitely needed.

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#1572319

FromMika Westerberg <mika.westerberg@linux.intel.com>
Date2017-02-02 13:20 +0100
Message-ID<t6owO-3OM-17@gated-at.bofh.it>
In reply to#1572295
On Thu, Feb 02, 2017 at 01:35:08PM +0200, Mika Westerberg wrote:
> On Thu, Feb 02, 2017 at 12:12:22PM +0100, Johannes Stezenbach wrote:
> > On Thu, Feb 02, 2017 at 12:31:22PM +0200, Mika Westerberg wrote:
> > > On Thu, Feb 02, 2017 at 10:52:00AM +0100, Johannes Stezenbach wrote:
> > > >                 OperationRegion (GPOP, GeneralPurposeIo, Zero, 0x0100)
> > > >                 Field (GPOP, ByteAcc, NoLock, Preserve)
> > > >                 {
> > > >                     Connection (
> > > >                         GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, IoRestrictionOutputOnly,
> > > >                             "\\_SB.PCI0.I2C7.PMI2", 0x00, ResourceConsumer, ,
> > > >                             )
> > > >                             {   // Pin list
> > > >                                 0x0020
> > > >                             }
> > > >                     ), 
> > > >                     GMP0,   1, 
> > > >                     ...
> > > >                     (repeat for many more pins)
> > > > 
> > > > I guess it means it uses chv_gpio pins and can't work
> > > > if the GPIO opregion is not registered?
> > > 
> > > That is using GPIO pins of the PMI2 device - the PMIC GPIO driver, I
> > > suppose.
> > > 
> > > So in addition to the PMIC MFD driver, you need to have a GPIO driver
> > > for Dollar Cove (I guess the quilt patch series included that as well?).
> > 
> > Nope, I see it for AX288 but didn't find it for TI DCove.  And in
> > current Linus' tree axp288_cells[] doesn't include gpio so
> > I concluded it's not needed... what am I missing?
> 
> So reading your DSDT there is that GPIO button array device \_SB.TBAD
> which has one GpioInt() referencing \_SB.PCI0.I2C7.PMI2. I suppose that
> is the power button GPIO.
> 
> In order to use that there needs to be a GPIO driver exposing those
> GPIOs to other drivers. So it is definitely needed.

Actually, looking again the patches you found:

https://github.com/01org/ProductionKernelQuilts/blob/master/uefi/cht-m1stable/patches/mfd-intel_soc_pmic-add-TI-variant-of-dollar-cove.patch
https://github.com/01org/ProductionKernelQuilts/blob/master/uefi/cht-m1stable/patches/PWRBTN-add-driver-for-TI-PMIC.patch

Did you try to them both? The latter seems to handle the power button
by talking directly with the PMIC (instead of using a GPIO).

Let's include the original author (Ramakrishna) as well if we could get
some information from him.

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#1572376

FromJohannes Stezenbach <js@sig21.net>
Date2017-02-02 15:00 +0100
Message-ID<t6q5z-4M6-17@gated-at.bofh.it>
In reply to#1572319
On Thu, Feb 02, 2017 at 02:16:39PM +0200, Mika Westerberg wrote:
> On Thu, Feb 02, 2017 at 01:35:08PM +0200, Mika Westerberg wrote:
> > On Thu, Feb 02, 2017 at 12:12:22PM +0100, Johannes Stezenbach wrote:
> > > On Thu, Feb 02, 2017 at 12:31:22PM +0200, Mika Westerberg wrote:
> > > > On Thu, Feb 02, 2017 at 10:52:00AM +0100, Johannes Stezenbach wrote:
> > > > >                 OperationRegion (GPOP, GeneralPurposeIo, Zero, 0x0100)
> > > > >                 Field (GPOP, ByteAcc, NoLock, Preserve)
> > > > >                 {
> > > > >                     Connection (
> > > > >                         GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, IoRestrictionOutputOnly,
> > > > >                             "\\_SB.PCI0.I2C7.PMI2", 0x00, ResourceConsumer, ,
> > > > >                             )
> > > > >                             {   // Pin list
> > > > >                                 0x0020
> > > > >                             }
> > > > >                     ), 
> > > > >                     GMP0,   1, 
> > > > >                     ...
> > > > >                     (repeat for many more pins)
> > > > > 
> > > > > I guess it means it uses chv_gpio pins and can't work
> > > > > if the GPIO opregion is not registered?
> > > > 
> > > > That is using GPIO pins of the PMI2 device - the PMIC GPIO driver, I
> > > > suppose.
> > > > 
> > > > So in addition to the PMIC MFD driver, you need to have a GPIO driver
> > > > for Dollar Cove (I guess the quilt patch series included that as well?).
> > > 
> > > Nope, I see it for AX288 but didn't find it for TI DCove.  And in
> > > current Linus' tree axp288_cells[] doesn't include gpio so
> > > I concluded it's not needed... what am I missing?
> > 
> > So reading your DSDT there is that GPIO button array device \_SB.TBAD
> > which has one GpioInt() referencing \_SB.PCI0.I2C7.PMI2. I suppose that
> > is the power button GPIO.
> > 
> > In order to use that there needs to be a GPIO driver exposing those
> > GPIOs to other drivers. So it is definitely needed.
> 
> Actually, looking again the patches you found:
> 
> https://github.com/01org/ProductionKernelQuilts/blob/master/uefi/cht-m1stable/patches/mfd-intel_soc_pmic-add-TI-variant-of-dollar-cove.patch
> https://github.com/01org/ProductionKernelQuilts/blob/master/uefi/cht-m1stable/patches/PWRBTN-add-driver-for-TI-PMIC.patch
> 
> Did you try to them both? The latter seems to handle the power button
> by talking directly with the PMIC (instead of using a GPIO).

Nope, as I've written earlier:
> In ProductionKernelQuilts I found
> DC-TI-PMIC-disable-power-button-support.patch so I guess it
> might not be needed because it's probably handled by ACPI.

[  +0.000338] input: Power Button as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0C0C:00/input/input0
[  +0.000127] ACPI: Power Button [PWRB]
...
[  +0.000248] input: Power Button as /devices/LNXSYSTM:00/LNXPWRBN:00/input/input3
[  +0.000116] ACPI: Power Button [PWRF]

And I also have:

[  +0.000004] soc_button_array INTCFD9:00: GPIO lookup for consumer soc_button_array
[  +0.000002] soc_button_array INTCFD9:00: using ACPI for GPIO lookup
[  +0.000003] acpi INTCFD9:00: GPIO: looking up soc_button_array-gpios
[  +0.000004] acpi INTCFD9:00: GPIO: looking up soc_button_array-gpio
[  +0.000003] acpi INTCFD9:00: GPIO: looking up 0 in _CRS
[  +0.000610] soc_button_array INTCFD9:00: lookup for GPIO soc_button_array failed
(repeats for 5 buttons, one of them should succeed)

> Let's include the original author (Ramakrishna) as well if we could get
> some information from him.

Looking at 0002-GPIO-Adding-AXP288-PMIC-GPIO-driver.patch from ProductionKernelQuilts,
it doesn't seem hard to do the same for the TI PMIC, but it needs information
from the PMIC datasheet for irq and gpio control registers.
Hopefully you have a patch or at least could provide the information.


Thanks,
Johannes

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