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Groups > linux.kernel > #1569191 > unrolled thread

[PATCH v3 00/24] drm/rockchip: MIPI fixes & improvements

Started byJohn Keeping <john@metanate.com>
First post2017-01-29 15:10 +0100
Last post2017-01-31 20:30 +0100
Articles 20 on this page of 42 — 2 participants

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Contents

  [PATCH v3 00/24] drm/rockchip: MIPI fixes & improvements John Keeping <john@metanate.com> - 2017-01-29 15:10 +0100
    [PATCH v3 08/24] drm/rockchip: dw-mipi-dsi: respect message flags John Keeping <john@metanate.com> - 2017-01-29 15:10 +0100
      Re: [PATCH v3 08/24] drm/rockchip: dw-mipi-dsi: respect message flags Sean Paul <seanpaul@chromium.org> - 2017-01-30 19:30 +0100
    [PATCH v3 01/24] drm/rockchip: dw-mipi-dsi: don't configure hardware in mode_set for MIPI John Keeping <john@metanate.com> - 2017-01-29 15:10 +0100
      Re: [PATCH v3 01/24] drm/rockchip: dw-mipi-dsi: don't configure  hardware in mode_set for MIPI Sean Paul <seanpaul@chromium.org> - 2017-01-30 16:40 +0100
    [PATCH v3 24/24] drm/rockchip: dw-mipi-dsi: support read commands John Keeping <john@metanate.com> - 2017-01-29 15:50 +0100
      Re: [PATCH v3 24/24] drm/rockchip: dw-mipi-dsi: support read commands Sean Paul <seanpaul@chromium.org> - 2017-01-30 16:40 +0100
        Re: [PATCH v3 24/24] drm/rockchip: dw-mipi-dsi: support read  commands John Keeping <john@metanate.com> - 2017-01-30 19:40 +0100
          Re: [PATCH v3 24/24] drm/rockchip: dw-mipi-dsi: support read commands Sean Paul <seanpaul@chromium.org> - 2017-01-30 21:20 +0100
            Re: [PATCH v3 24/24] drm/rockchip: dw-mipi-dsi: support read  commands John Keeping <john@metanate.com> - 2017-01-31 13:50 +0100
              Re: [PATCH v3 24/24] drm/rockchip: dw-mipi-dsi: support read commands Sean Paul <seanpaul@chromium.org> - 2017-01-31 15:50 +0100
    [PATCH v3 11/24] drm/rockchip: dw-mipi-dsi: prepare panel after phy init John Keeping <john@metanate.com> - 2017-01-29 15:50 +0100
      Re: [PATCH v3 11/24] drm/rockchip: dw-mipi-dsi: prepare panel after  phy init Sean Paul <seanpaul@chromium.org> - 2017-01-30 21:20 +0100
    [PATCH v3 05/24] drm/rockchip: dw-mipi-dsi: fix generic packet status check John Keeping <john@metanate.com> - 2017-01-29 15:50 +0100
      Re: [PATCH v3 05/24] drm/rockchip: dw-mipi-dsi: fix generic packet  status check Sean Paul <seanpaul@chromium.org> - 2017-01-30 19:30 +0100
    [PATCH v3 07/24] drm/rockchip: dw-mipi-dsi: include bad value in error message John Keeping <john@metanate.com> - 2017-01-29 15:50 +0100
      Re: [PATCH v3 07/24] drm/rockchip: dw-mipi-dsi: include bad value in  error message Sean Paul <seanpaul@chromium.org> - 2017-01-30 19:10 +0100
    [PATCH v3 20/24] drm/rockchip: vop: test for P{H,V}SYNC John Keeping <john@metanate.com> - 2017-01-29 15:50 +0100
      Re: [PATCH v3 20/24] drm/rockchip: vop: test for P{H,V}SYNC Sean Paul <seanpaul@chromium.org> - 2017-01-31 20:20 +0100
    [PATCH v3 12/24] drm/rockchip: dw-mipi-dsi: allow commands in panel_disable John Keeping <john@metanate.com> - 2017-01-29 15:50 +0100
      Re: [PATCH v3 12/24] drm/rockchip: dw-mipi-dsi: allow commands in  panel_disable Sean Paul <seanpaul@chromium.org> - 2017-01-30 21:30 +0100
        Re: [PATCH v3 12/24] drm/rockchip: dw-mipi-dsi: allow commands in  panel_disable John Keeping <john@metanate.com> - 2017-01-31 13:30 +0100
    [PATCH v3 13/24] drm/rockchip: dw-mipi-dsi: fix escape clock rate John Keeping <john@metanate.com> - 2017-01-29 15:50 +0100
      Re: [PATCH v3 13/24] drm/rockchip: dw-mipi-dsi: fix escape clock rate Sean Paul <seanpaul@chromium.org> - 2017-01-30 21:30 +0100
        Re: [PATCH v3 13/24] drm/rockchip: dw-mipi-dsi: fix escape clock  rate John Keeping <john@metanate.com> - 2017-02-01 18:30 +0100
    [PATCH v3 18/24] drm/rockchip: dw-mipi-dsi: use specific poll helper John Keeping <john@metanate.com> - 2017-01-29 15:50 +0100
      Re: [PATCH v3 18/24] drm/rockchip: dw-mipi-dsi: use specific poll  helper Sean Paul <seanpaul@chromium.org> - 2017-01-31 20:00 +0100
    [PATCH v3 04/24] drm/rockchip: dw-mipi-dsi: fix command header writes John Keeping <john@metanate.com> - 2017-01-29 15:50 +0100
      Re: [PATCH v3 04/24] drm/rockchip: dw-mipi-dsi: fix command header  writes Sean Paul <seanpaul@chromium.org> - 2017-01-30 17:00 +0100
    [PATCH v3 15/24] drm/rockchip: dw-mipi-dsi: configure PHY before enabling John Keeping <john@metanate.com> - 2017-01-29 15:50 +0100
      Re: [PATCH v3 15/24] drm/rockchip: dw-mipi-dsi: configure PHY before  enabling Sean Paul <seanpaul@chromium.org> - 2017-01-30 21:30 +0100
        Re: [PATCH v3 15/24] drm/rockchip: dw-mipi-dsi: configure PHY  before enabling John Keeping <john@metanate.com> - 2017-01-31 13:40 +0100
    [PATCH v3 19/24] drm/rockchip: dw-mipi-dsi: use positive check for N{H,V}SYNC John Keeping <john@metanate.com> - 2017-01-29 16:20 +0100
      Re: [PATCH v3 19/24] drm/rockchip: dw-mipi-dsi: use positive check  for N{H, V}SYNC Sean Paul <seanpaul@chromium.org> - 2017-01-31 20:20 +0100
    [PATCH v3 17/24] drm/rockchip: dw-mipi-dsi: improve PLL configuration John Keeping <john@metanate.com> - 2017-01-29 16:20 +0100
      Re: [PATCH v3 17/24] drm/rockchip: dw-mipi-dsi: improve PLL  configuration Sean Paul <seanpaul@chromium.org> - 2017-01-31 20:20 +0100
    [PATCH v3 23/24] drm/rockchip: dw-mipi-dsi: add reset control John Keeping <john@metanate.com> - 2017-01-29 16:30 +0100
      Re: [PATCH v3 23/24] drm/rockchip: dw-mipi-dsi: add reset control Sean Paul <seanpaul@chromium.org> - 2017-01-31 20:30 +0100
    [PATCH v3 03/24] drm/rockchip: dw-mipi-dsi: remove mode_set hook John Keeping <john@metanate.com> - 2017-01-29 16:30 +0100
      Re: [PATCH v3 03/24] drm/rockchip: dw-mipi-dsi: remove mode_set hook Sean Paul <seanpaul@chromium.org> - 2017-01-30 16:50 +0100
    [PATCH v3 22/24] drm/rockchip: dw-mipi-dsi: support non-burst modes John Keeping <john@metanate.com> - 2017-01-29 16:30 +0100
      Re: [PATCH v3 22/24] drm/rockchip: dw-mipi-dsi: support non-burst  modes Sean Paul <seanpaul@chromium.org> - 2017-01-31 20:30 +0100

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#1570101 — Re: [PATCH v3 12/24] drm/rockchip: dw-mipi-dsi: allow commands in panel_disable

FromSean Paul <seanpaul@chromium.org>
Date2017-01-30 21:30 +0100
SubjectRe: [PATCH v3 12/24] drm/rockchip: dw-mipi-dsi: allow commands in panel_disable
Message-ID<t5qKm-8tx-23@gated-at.bofh.it>
In reply to#1569200
On Sun, Jan 29, 2017 at 01:24:32PM +0000, John Keeping wrote:
> Panel drivers may want to sent commands during the disable function, for
> example MIPI_DCS_SET_DISPLAY_OFF before the video signal ends.  In order
> to send commands we need to write to registers, so pclk must be enabled.
> 
> While changing this, remove the unnecessary code after the panel
> unprepare call which seems to be a workaround for a specific panel and
> thus belongs in the panel driver.

Do you know which panel? If the panel driver is upstream, we should make sure we
migrate this hack before removing it here. If it's downstream somewhere,

Reviewed-by: Sean Paul <seanpaul@chromium.org>

> 
> Signed-off-by: John Keeping <john@metanate.com>
> Reviewed-by: Chris Zhong <zyw@rock-chips.com>
> ---
> v3:
> - Add Chris' Reviewed-by
> Unchanged in v2
> 
>  drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 12 ++----------
>  1 file changed, 2 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
> index 7ada6d8ed143..290282e86d16 100644
> --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
> +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
> @@ -846,24 +846,16 @@ static void dw_mipi_dsi_encoder_disable(struct drm_encoder *encoder)
>  {
>  	struct dw_mipi_dsi *dsi = encoder_to_dsi(encoder);
>  
> -	drm_panel_disable(dsi->panel);
> -
>  	if (clk_prepare_enable(dsi->pclk)) {
>  		dev_err(dsi->dev, "%s: Failed to enable pclk\n", __func__);
>  		return;
>  	}
>  
> +	drm_panel_disable(dsi->panel);
> +
>  	dw_mipi_dsi_set_mode(dsi, DW_MIPI_DSI_CMD_MODE);
>  	drm_panel_unprepare(dsi->panel);
> -	dw_mipi_dsi_set_mode(dsi, DW_MIPI_DSI_VID_MODE);
>  
> -	/*
> -	 * This is necessary to make sure the peripheral will be driven
> -	 * normally when the display is enabled again later.
> -	 */
> -	msleep(120);
> -
> -	dw_mipi_dsi_set_mode(dsi, DW_MIPI_DSI_CMD_MODE);
>  	dw_mipi_dsi_disable(dsi);
>  	clk_disable_unprepare(dsi->pclk);
>  }
> -- 
> 2.11.0.197.gb556de5.dirty
> 
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel

-- 
Sean Paul, Software Engineer, Google / Chromium OS

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#1570661 — Re: [PATCH v3 12/24] drm/rockchip: dw-mipi-dsi: allow commands in panel_disable

FromJohn Keeping <john@metanate.com>
Date2017-01-31 13:30 +0100
SubjectRe: [PATCH v3 12/24] drm/rockchip: dw-mipi-dsi: allow commands in panel_disable
Message-ID<t5FJn-DW-1@gated-at.bofh.it>
In reply to#1570101
On Mon, 30 Jan 2017 15:19:53 -0500, Sean Paul wrote:

> On Sun, Jan 29, 2017 at 01:24:32PM +0000, John Keeping wrote:
> > Panel drivers may want to sent commands during the disable function, for
> > example MIPI_DCS_SET_DISPLAY_OFF before the video signal ends.  In order
> > to send commands we need to write to registers, so pclk must be enabled.
> > 
> > While changing this, remove the unnecessary code after the panel
> > unprepare call which seems to be a workaround for a specific panel and
> > thus belongs in the panel driver.  
> 
> Do you know which panel? If the panel driver is upstream, we should make sure we
> migrate this hack before removing it here. If it's downstream somewhere,

I'm just going by the comment in the code that this patch deletes and
the fact that this delay was not needed on any of the three panels I
tested.

Given the way the modes change, I think this should be a 120ms disable
delay if the affected panel is supported by the simple-panel driver.

> Reviewed-by: Sean Paul <seanpaul@chromium.org>
> 
> > 
> > Signed-off-by: John Keeping <john@metanate.com>
> > Reviewed-by: Chris Zhong <zyw@rock-chips.com>
> > ---
> > v3:
> > - Add Chris' Reviewed-by
> > Unchanged in v2
> > 
> >  drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 12 ++----------
> >  1 file changed, 2 insertions(+), 10 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
> > index 7ada6d8ed143..290282e86d16 100644
> > --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
> > +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
> > @@ -846,24 +846,16 @@ static void dw_mipi_dsi_encoder_disable(struct drm_encoder *encoder)
> >  {
> >  	struct dw_mipi_dsi *dsi = encoder_to_dsi(encoder);
> >  
> > -	drm_panel_disable(dsi->panel);
> > -
> >  	if (clk_prepare_enable(dsi->pclk)) {
> >  		dev_err(dsi->dev, "%s: Failed to enable pclk\n", __func__);
> >  		return;
> >  	}
> >  
> > +	drm_panel_disable(dsi->panel);
> > +
> >  	dw_mipi_dsi_set_mode(dsi, DW_MIPI_DSI_CMD_MODE);
> >  	drm_panel_unprepare(dsi->panel);
> > -	dw_mipi_dsi_set_mode(dsi, DW_MIPI_DSI_VID_MODE);
> >  
> > -	/*
> > -	 * This is necessary to make sure the peripheral will be driven
> > -	 * normally when the display is enabled again later.
> > -	 */
> > -	msleep(120);
> > -
> > -	dw_mipi_dsi_set_mode(dsi, DW_MIPI_DSI_CMD_MODE);
> >  	dw_mipi_dsi_disable(dsi);
> >  	clk_disable_unprepare(dsi->pclk);
> >  }
> > -- 
> > 2.11.0.197.gb556de5.dirty
> > 
> > _______________________________________________
> > dri-devel mailing list
> > dri-devel@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/dri-devel  
>

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#1569201 — [PATCH v3 13/24] drm/rockchip: dw-mipi-dsi: fix escape clock rate

FromJohn Keeping <john@metanate.com>
Date2017-01-29 15:50 +0100
Subject[PATCH v3 13/24] drm/rockchip: dw-mipi-dsi: fix escape clock rate
Message-ID<t4YXM-8ez-27@gated-at.bofh.it>
In reply to#1569191
This clock rate is derived from the PHY PLL, so it should be calculated
dynamically.  Use the same calculation as the vendor kernel to derive
the escape clock speed.

Signed-off-by: John Keeping <john@metanate.com>
Reviewed-by: Chris Zhong <zyw@rock-chips.com>
---
v3:
- Improve the commit message a bit
- Add Chris' Reviewed-by
Unchanged in v2

 drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
index 290282e86d16..c2e0ba96e0a0 100644
--- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
@@ -710,11 +710,13 @@ static void dw_mipi_dsi_disable(struct dw_mipi_dsi *dsi)
 
 static void dw_mipi_dsi_init(struct dw_mipi_dsi *dsi)
 {
+	u32 esc_clk_division = (dsi->lane_mbps >> 3) / 20 + 1;
+
 	dsi_write(dsi, DSI_PWR_UP, RESET);
 	dsi_write(dsi, DSI_PHY_RSTZ, PHY_DISFORCEPLL | PHY_DISABLECLK
 		  | PHY_RSTZ | PHY_SHUTDOWNZ);
 	dsi_write(dsi, DSI_CLKMGR_CFG, TO_CLK_DIVIDSION(10) |
-		  TX_ESC_CLK_DIVIDSION(7));
+		  TX_ESC_CLK_DIVIDSION(esc_clk_division));
 }
 
 static void dw_mipi_dsi_dpi_config(struct dw_mipi_dsi *dsi,
-- 
2.11.0.197.gb556de5.dirty

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#1570098 — Re: [PATCH v3 13/24] drm/rockchip: dw-mipi-dsi: fix escape clock rate

FromSean Paul <seanpaul@chromium.org>
Date2017-01-30 21:30 +0100
SubjectRe: [PATCH v3 13/24] drm/rockchip: dw-mipi-dsi: fix escape clock rate
Message-ID<t5qKn-8tx-27@gated-at.bofh.it>
In reply to#1569201
On Sun, Jan 29, 2017 at 01:24:33PM +0000, John Keeping wrote:
> This clock rate is derived from the PHY PLL, so it should be calculated
> dynamically.  Use the same calculation as the vendor kernel to derive
> the escape clock speed.
> 

Nit below, but

Reviewed-by: Sean Paul <seanpaul@chromium.org>

> Signed-off-by: John Keeping <john@metanate.com>
> Reviewed-by: Chris Zhong <zyw@rock-chips.com>
> ---
> v3:
> - Improve the commit message a bit
> - Add Chris' Reviewed-by
> Unchanged in v2
> 
>  drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
> index 290282e86d16..c2e0ba96e0a0 100644
> --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
> +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
> @@ -710,11 +710,13 @@ static void dw_mipi_dsi_disable(struct dw_mipi_dsi *dsi)
>  
>  static void dw_mipi_dsi_init(struct dw_mipi_dsi *dsi)
>  {

Nit: It would be nice to add a comment to the effect of "You are not meant to
understand this, it comes from the vendor kernel"

> +	u32 esc_clk_division = (dsi->lane_mbps >> 3) / 20 + 1;
> +
>  	dsi_write(dsi, DSI_PWR_UP, RESET);
>  	dsi_write(dsi, DSI_PHY_RSTZ, PHY_DISFORCEPLL | PHY_DISABLECLK
>  		  | PHY_RSTZ | PHY_SHUTDOWNZ);
>  	dsi_write(dsi, DSI_CLKMGR_CFG, TO_CLK_DIVIDSION(10) |
> -		  TX_ESC_CLK_DIVIDSION(7));
> +		  TX_ESC_CLK_DIVIDSION(esc_clk_division));
>  }
>  
>  static void dw_mipi_dsi_dpi_config(struct dw_mipi_dsi *dsi,
> -- 
> 2.11.0.197.gb556de5.dirty
> 
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel

-- 
Sean Paul, Software Engineer, Google / Chromium OS

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#1571803 — Re: [PATCH v3 13/24] drm/rockchip: dw-mipi-dsi: fix escape clock rate

FromJohn Keeping <john@metanate.com>
Date2017-02-01 18:30 +0100
SubjectRe: [PATCH v3 13/24] drm/rockchip: dw-mipi-dsi: fix escape clock rate
Message-ID<t66Tg-m7-7@gated-at.bofh.it>
In reply to#1570098
On Mon, 30 Jan 2017 15:25:10 -0500, Sean Paul wrote:

> On Sun, Jan 29, 2017 at 01:24:33PM +0000, John Keeping wrote:
> > This clock rate is derived from the PHY PLL, so it should be calculated
> > dynamically.  Use the same calculation as the vendor kernel to derive
> > the escape clock speed.
> >   
> 
> Nit below, but
> 
> Reviewed-by: Sean Paul <seanpaul@chromium.org>
> 
> > Signed-off-by: John Keeping <john@metanate.com>
> > Reviewed-by: Chris Zhong <zyw@rock-chips.com>
> > ---
> > v3:
> > - Improve the commit message a bit
> > - Add Chris' Reviewed-by
> > Unchanged in v2
> > 
> >  drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 4 +++-
> >  1 file changed, 3 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
> > index 290282e86d16..c2e0ba96e0a0 100644
> > --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
> > +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
> > @@ -710,11 +710,13 @@ static void dw_mipi_dsi_disable(struct dw_mipi_dsi *dsi)
> >  
> >  static void dw_mipi_dsi_init(struct dw_mipi_dsi *dsi)
> >  {  
> 
> Nit: It would be nice to add a comment to the effect of "You are not meant to
> understand this, it comes from the vendor kernel"

Actually, I think my commit message was misleading.  I think I do
understand the calculation, although the TRM is not particularly clear
about it.  TX_ESC_CLK_DIVISION is described as:

    the division factor for the TX_Escape clock source (lanebyteclk).
    The value 0 and 1 stop the TX_ESC clock generation

Now lanebyteclk is (dsi->lane_mbps >> 3) since lane_mbps is the
lane bit clock.  The maximum escape mode clock from the MIPI
specification is 20MHz, so we end up needing

    lanebyteclk / esc_clk_division < 20

thus:

    esc_clk_division > lanebyteclk / 20

and we want esc_clk_division >= 2 to avoid disabling the clock
generation.

I'll add a comment to this effect.

> > +	u32 esc_clk_division = (dsi->lane_mbps >> 3) / 20 + 1;
> > +
> >  	dsi_write(dsi, DSI_PWR_UP, RESET);
> >  	dsi_write(dsi, DSI_PHY_RSTZ, PHY_DISFORCEPLL | PHY_DISABLECLK
> >  		  | PHY_RSTZ | PHY_SHUTDOWNZ);
> >  	dsi_write(dsi, DSI_CLKMGR_CFG, TO_CLK_DIVIDSION(10) |
> > -		  TX_ESC_CLK_DIVIDSION(7));
> > +		  TX_ESC_CLK_DIVIDSION(esc_clk_division));
> >  }
> >  
> >  static void dw_mipi_dsi_dpi_config(struct dw_mipi_dsi *dsi,
> > -- 
> > 2.11.0.197.gb556de5.dirty
> > 
> > _______________________________________________
> > dri-devel mailing list
> > dri-devel@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/dri-devel  
>

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#1569202 — [PATCH v3 18/24] drm/rockchip: dw-mipi-dsi: use specific poll helper

FromJohn Keeping <john@metanate.com>
Date2017-01-29 15:50 +0100
Subject[PATCH v3 18/24] drm/rockchip: dw-mipi-dsi: use specific poll helper
Message-ID<t4YXL-8ez-15@gated-at.bofh.it>
In reply to#1569191
As the documentation for readx_poll_timeout says, we want to use the
specialized macro for readl rather than using the generic version
directly.

Signed-off-by: John Keeping <john@metanate.com>
Reviewed-by: Chris Zhong <zyw@rock-chips.com>
---
v3:
- Add Chris' Reviewed-by
Unchanged in v2

 drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
index dcb66a21e1f1..be395c3c5c06 100644
--- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
@@ -474,14 +474,14 @@ static int dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi)
 				     PHY_UNRSTZ | PHY_UNSHUTDOWNZ);
 
 
-	ret = readx_poll_timeout(readl, dsi->base + DSI_PHY_STATUS,
+	ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS,
 				 val, val & LOCK, 1000, PHY_STATUS_TIMEOUT_US);
 	if (ret < 0) {
 		dev_err(dsi->dev, "failed to wait for phy lock state\n");
 		return ret;
 	}
 
-	ret = readx_poll_timeout(readl, dsi->base + DSI_PHY_STATUS,
+	ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS,
 				 val, val & STOP_STATE_CLK_LANE, 1000,
 				 PHY_STATUS_TIMEOUT_US);
 	if (ret < 0) {
@@ -597,7 +597,7 @@ static int dw_mipi_dsi_gen_pkt_hdr_write(struct dw_mipi_dsi *dsi, u32 hdr_val)
 	int ret;
 	u32 val, mask;
 
-	ret = readx_poll_timeout(readl, dsi->base + DSI_CMD_PKT_STATUS,
+	ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
 				 val, !(val & GEN_CMD_FULL), 1000,
 				 CMD_PKT_STATUS_TIMEOUT_US);
 	if (ret < 0) {
@@ -608,7 +608,7 @@ static int dw_mipi_dsi_gen_pkt_hdr_write(struct dw_mipi_dsi *dsi, u32 hdr_val)
 	dsi_write(dsi, DSI_GEN_HDR, hdr_val);
 
 	mask = GEN_CMD_EMPTY | GEN_PLD_W_EMPTY;
-	ret = readx_poll_timeout(readl, dsi->base + DSI_CMD_PKT_STATUS,
+	ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
 				 val, (val & mask) == mask,
 				 1000, CMD_PKT_STATUS_TIMEOUT_US);
 	if (ret < 0) {
@@ -667,7 +667,7 @@ static int dw_mipi_dsi_dcs_long_write(struct dw_mipi_dsi *dsi,
 			len -= pld_data_bytes;
 		}
 
-		ret = readx_poll_timeout(readl, dsi->base + DSI_CMD_PKT_STATUS,
+		ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
 					 val, !(val & GEN_PLD_W_FULL), 1000,
 					 CMD_PKT_STATUS_TIMEOUT_US);
 		if (ret < 0) {
-- 
2.11.0.197.gb556de5.dirty

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#1570992 — Re: [PATCH v3 18/24] drm/rockchip: dw-mipi-dsi: use specific poll helper

FromSean Paul <seanpaul@chromium.org>
Date2017-01-31 20:00 +0100
SubjectRe: [PATCH v3 18/24] drm/rockchip: dw-mipi-dsi: use specific poll helper
Message-ID<t5LON-4b0-1@gated-at.bofh.it>
In reply to#1569202
On Sun, Jan 29, 2017 at 01:24:38PM +0000, John Keeping wrote:
> As the documentation for readx_poll_timeout says, we want to use the
> specialized macro for readl rather than using the generic version
> directly.
> 

Reviewed-by: Sean Paul <seanpaul@chromium.org>

> Signed-off-by: John Keeping <john@metanate.com>
> Reviewed-by: Chris Zhong <zyw@rock-chips.com>
> ---
> v3:
> - Add Chris' Reviewed-by
> Unchanged in v2
> 
>  drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 10 +++++-----
>  1 file changed, 5 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
> index dcb66a21e1f1..be395c3c5c06 100644
> --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
> +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
> @@ -474,14 +474,14 @@ static int dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi)
>  				     PHY_UNRSTZ | PHY_UNSHUTDOWNZ);
>  
>  
> -	ret = readx_poll_timeout(readl, dsi->base + DSI_PHY_STATUS,
> +	ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS,
>  				 val, val & LOCK, 1000, PHY_STATUS_TIMEOUT_US);
>  	if (ret < 0) {
>  		dev_err(dsi->dev, "failed to wait for phy lock state\n");
>  		return ret;
>  	}
>  
> -	ret = readx_poll_timeout(readl, dsi->base + DSI_PHY_STATUS,
> +	ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS,
>  				 val, val & STOP_STATE_CLK_LANE, 1000,
>  				 PHY_STATUS_TIMEOUT_US);
>  	if (ret < 0) {
> @@ -597,7 +597,7 @@ static int dw_mipi_dsi_gen_pkt_hdr_write(struct dw_mipi_dsi *dsi, u32 hdr_val)
>  	int ret;
>  	u32 val, mask;
>  
> -	ret = readx_poll_timeout(readl, dsi->base + DSI_CMD_PKT_STATUS,
> +	ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
>  				 val, !(val & GEN_CMD_FULL), 1000,
>  				 CMD_PKT_STATUS_TIMEOUT_US);
>  	if (ret < 0) {
> @@ -608,7 +608,7 @@ static int dw_mipi_dsi_gen_pkt_hdr_write(struct dw_mipi_dsi *dsi, u32 hdr_val)
>  	dsi_write(dsi, DSI_GEN_HDR, hdr_val);
>  
>  	mask = GEN_CMD_EMPTY | GEN_PLD_W_EMPTY;
> -	ret = readx_poll_timeout(readl, dsi->base + DSI_CMD_PKT_STATUS,
> +	ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
>  				 val, (val & mask) == mask,
>  				 1000, CMD_PKT_STATUS_TIMEOUT_US);
>  	if (ret < 0) {
> @@ -667,7 +667,7 @@ static int dw_mipi_dsi_dcs_long_write(struct dw_mipi_dsi *dsi,
>  			len -= pld_data_bytes;
>  		}
>  
> -		ret = readx_poll_timeout(readl, dsi->base + DSI_CMD_PKT_STATUS,
> +		ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
>  					 val, !(val & GEN_PLD_W_FULL), 1000,
>  					 CMD_PKT_STATUS_TIMEOUT_US);
>  		if (ret < 0) {
> -- 
> 2.11.0.197.gb556de5.dirty
> 
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel

-- 
Sean Paul, Software Engineer, Google / Chromium OS

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#1569203 — [PATCH v3 04/24] drm/rockchip: dw-mipi-dsi: fix command header writes

FromJohn Keeping <john@metanate.com>
Date2017-01-29 15:50 +0100
Subject[PATCH v3 04/24] drm/rockchip: dw-mipi-dsi: fix command header writes
Message-ID<t4YXM-8ez-29@gated-at.bofh.it>
In reply to#1569191
In a couple of places here we use "val" for the value that is about to
be written to a register but then reuse the same variable for the value
of a status register before we get around to writing it.  Rename the
value to be written to so that we write the value we intend to and not
what we have just read from the status register.

Signed-off-by: John Keeping <john@metanate.com>
Tested-by: Chris Zhong <zyw@rock-chips.com>
Reviewed-by: Chris Zhong <zyw@rock-chips.com>
---
Unchanged in v3
Unchanged in v2

 drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 10 ++++++----
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
index bd92e58b64f3..4cbbbcb619b7 100644
--- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
@@ -542,9 +542,10 @@ static int dw_mipi_dsi_host_detach(struct mipi_dsi_host *host,
 	return 0;
 }
 
-static int dw_mipi_dsi_gen_pkt_hdr_write(struct dw_mipi_dsi *dsi, u32 val)
+static int dw_mipi_dsi_gen_pkt_hdr_write(struct dw_mipi_dsi *dsi, u32 hdr_val)
 {
 	int ret;
+	u32 val;
 
 	ret = readx_poll_timeout(readl, dsi->base + DSI_CMD_PKT_STATUS,
 				 val, !(val & GEN_CMD_FULL), 1000,
@@ -554,7 +555,7 @@ static int dw_mipi_dsi_gen_pkt_hdr_write(struct dw_mipi_dsi *dsi, u32 val)
 		return ret;
 	}
 
-	dsi_write(dsi, DSI_GEN_HDR, val);
+	dsi_write(dsi, DSI_GEN_HDR, hdr_val);
 
 	ret = readx_poll_timeout(readl, dsi->base + DSI_CMD_PKT_STATUS,
 				 val, val & (GEN_CMD_EMPTY | GEN_PLD_W_EMPTY),
@@ -587,8 +588,9 @@ static int dw_mipi_dsi_dcs_long_write(struct dw_mipi_dsi *dsi,
 {
 	const u32 *tx_buf = msg->tx_buf;
 	int len = msg->tx_len, pld_data_bytes = sizeof(*tx_buf), ret;
-	u32 val = GEN_HDATA(msg->tx_len) | GEN_HTYPE(msg->type);
+	u32 hdr_val = GEN_HDATA(msg->tx_len) | GEN_HTYPE(msg->type);
 	u32 remainder = 0;
+	u32 val;
 
 	if (msg->tx_len < 3) {
 		dev_err(dsi->dev, "wrong tx buf length %zu for long write\n",
@@ -617,7 +619,7 @@ static int dw_mipi_dsi_dcs_long_write(struct dw_mipi_dsi *dsi,
 		}
 	}
 
-	return dw_mipi_dsi_gen_pkt_hdr_write(dsi, val);
+	return dw_mipi_dsi_gen_pkt_hdr_write(dsi, hdr_val);
 }
 
 static ssize_t dw_mipi_dsi_host_transfer(struct mipi_dsi_host *host,
-- 
2.11.0.197.gb556de5.dirty

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#1569861 — Re: [PATCH v3 04/24] drm/rockchip: dw-mipi-dsi: fix command header writes

FromSean Paul <seanpaul@chromium.org>
Date2017-01-30 17:00 +0100
SubjectRe: [PATCH v3 04/24] drm/rockchip: dw-mipi-dsi: fix command header writes
Message-ID<t5mx4-5LI-21@gated-at.bofh.it>
In reply to#1569203
On Sun, Jan 29, 2017 at 01:24:24PM +0000, John Keeping wrote:
> In a couple of places here we use "val" for the value that is about to
> be written to a register but then reuse the same variable for the value
> of a status register before we get around to writing it.  Rename the
> value to be written to so that we write the value we intend to and not
> what we have just read from the status register.
> 

Oh my.

Reviewed-by: Sean Paul <seanpaul@chromium.org>

> Signed-off-by: John Keeping <john@metanate.com>
> Tested-by: Chris Zhong <zyw@rock-chips.com>
> Reviewed-by: Chris Zhong <zyw@rock-chips.com>
> ---
> Unchanged in v3
> Unchanged in v2
> 
>  drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 10 ++++++----
>  1 file changed, 6 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
> index bd92e58b64f3..4cbbbcb619b7 100644
> --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
> +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
> @@ -542,9 +542,10 @@ static int dw_mipi_dsi_host_detach(struct mipi_dsi_host *host,
>  	return 0;
>  }
>  
> -static int dw_mipi_dsi_gen_pkt_hdr_write(struct dw_mipi_dsi *dsi, u32 val)
> +static int dw_mipi_dsi_gen_pkt_hdr_write(struct dw_mipi_dsi *dsi, u32 hdr_val)
>  {
>  	int ret;
> +	u32 val;
>  
>  	ret = readx_poll_timeout(readl, dsi->base + DSI_CMD_PKT_STATUS,
>  				 val, !(val & GEN_CMD_FULL), 1000,
> @@ -554,7 +555,7 @@ static int dw_mipi_dsi_gen_pkt_hdr_write(struct dw_mipi_dsi *dsi, u32 val)
>  		return ret;
>  	}
>  
> -	dsi_write(dsi, DSI_GEN_HDR, val);
> +	dsi_write(dsi, DSI_GEN_HDR, hdr_val);
>  
>  	ret = readx_poll_timeout(readl, dsi->base + DSI_CMD_PKT_STATUS,
>  				 val, val & (GEN_CMD_EMPTY | GEN_PLD_W_EMPTY),
> @@ -587,8 +588,9 @@ static int dw_mipi_dsi_dcs_long_write(struct dw_mipi_dsi *dsi,
>  {
>  	const u32 *tx_buf = msg->tx_buf;
>  	int len = msg->tx_len, pld_data_bytes = sizeof(*tx_buf), ret;
> -	u32 val = GEN_HDATA(msg->tx_len) | GEN_HTYPE(msg->type);
> +	u32 hdr_val = GEN_HDATA(msg->tx_len) | GEN_HTYPE(msg->type);
>  	u32 remainder = 0;
> +	u32 val;
>  
>  	if (msg->tx_len < 3) {
>  		dev_err(dsi->dev, "wrong tx buf length %zu for long write\n",
> @@ -617,7 +619,7 @@ static int dw_mipi_dsi_dcs_long_write(struct dw_mipi_dsi *dsi,
>  		}
>  	}
>  
> -	return dw_mipi_dsi_gen_pkt_hdr_write(dsi, val);
> +	return dw_mipi_dsi_gen_pkt_hdr_write(dsi, hdr_val);
>  }
>  
>  static ssize_t dw_mipi_dsi_host_transfer(struct mipi_dsi_host *host,
> -- 
> 2.11.0.197.gb556de5.dirty
> 
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel

-- 
Sean Paul, Software Engineer, Google / Chromium OS

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#1569204 — [PATCH v3 15/24] drm/rockchip: dw-mipi-dsi: configure PHY before enabling

FromJohn Keeping <john@metanate.com>
Date2017-01-29 15:50 +0100
Subject[PATCH v3 15/24] drm/rockchip: dw-mipi-dsi: configure PHY before enabling
Message-ID<t4YXM-8ez-25@gated-at.bofh.it>
In reply to#1569191
The bias, bandgap and PLL should all be configured before we enable
them.

Signed-off-by: John Keeping <john@metanate.com>
---
v3:
- Squash together two patches that both affect initialization order of
  the PHY
Unchanged in v2

 drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 11 ++++++-----
 1 file changed, 6 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
index 5b3068e9e8db..cfe7e4ba305c 100644
--- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
@@ -413,12 +413,17 @@ static int dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi)
 
 	dw_mipi_dsi_phy_write(dsi, 0x44, HSFREQRANGE_SEL(testdin));
 
-	dw_mipi_dsi_phy_write(dsi, 0x19, PLL_LOOP_DIV_EN | PLL_INPUT_DIV_EN);
 	dw_mipi_dsi_phy_write(dsi, 0x17, INPUT_DIVIDER(dsi->input_div));
 	dw_mipi_dsi_phy_write(dsi, 0x18, LOOP_DIV_LOW_SEL(dsi->feedback_div) |
 					 LOW_PROGRAM_EN);
 	dw_mipi_dsi_phy_write(dsi, 0x18, LOOP_DIV_HIGH_SEL(dsi->feedback_div) |
 					 HIGH_PROGRAM_EN);
+	dw_mipi_dsi_phy_write(dsi, 0x19, PLL_LOOP_DIV_EN | PLL_INPUT_DIV_EN);
+
+	dw_mipi_dsi_phy_write(dsi, 0x22, LOW_PROGRAM_EN |
+					 BIASEXTR_SEL(BIASEXTR_127_7));
+	dw_mipi_dsi_phy_write(dsi, 0x22, HIGH_PROGRAM_EN |
+					 BANDGAP_SEL(BANDGAP_96_10));
 
 	dw_mipi_dsi_phy_write(dsi, 0x20, POWER_CONTROL | INTERNAL_REG_CURRENT |
 					 BIAS_BLOCK_ON | BANDGAP_ON);
@@ -429,10 +434,6 @@ static int dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi)
 					 SETRD_MAX | POWER_MANAGE |
 					 TER_RESISTORS_ON);
 
-	dw_mipi_dsi_phy_write(dsi, 0x22, LOW_PROGRAM_EN |
-					 BIASEXTR_SEL(BIASEXTR_127_7));
-	dw_mipi_dsi_phy_write(dsi, 0x22, HIGH_PROGRAM_EN |
-					 BANDGAP_SEL(BANDGAP_96_10));
 
 	dw_mipi_dsi_phy_write(dsi, 0x70, TLP_PROGRAM_EN | 0xf);
 	dw_mipi_dsi_phy_write(dsi, 0x71, THS_PRE_PROGRAM_EN | 0x55);
-- 
2.11.0.197.gb556de5.dirty

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#1570099 — Re: [PATCH v3 15/24] drm/rockchip: dw-mipi-dsi: configure PHY before enabling

FromSean Paul <seanpaul@chromium.org>
Date2017-01-30 21:30 +0100
SubjectRe: [PATCH v3 15/24] drm/rockchip: dw-mipi-dsi: configure PHY before enabling
Message-ID<t5qKm-8tx-17@gated-at.bofh.it>
In reply to#1569204
On Sun, Jan 29, 2017 at 01:24:35PM +0000, John Keeping wrote:
> The bias, bandgap and PLL should all be configured before we enable
> them.
> 

Do you know why the test codes are hard-coded magic? It'd be nice to make some
sense of them in a future patch.

Reviewed-by: Sean Paul <seanpaul@chromium.org>

> Signed-off-by: John Keeping <john@metanate.com>
> ---
> v3:
> - Squash together two patches that both affect initialization order of
>   the PHY
> Unchanged in v2
> 
>  drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 11 ++++++-----
>  1 file changed, 6 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
> index 5b3068e9e8db..cfe7e4ba305c 100644
> --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
> +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
> @@ -413,12 +413,17 @@ static int dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi)
>  
>  	dw_mipi_dsi_phy_write(dsi, 0x44, HSFREQRANGE_SEL(testdin));
>  
> -	dw_mipi_dsi_phy_write(dsi, 0x19, PLL_LOOP_DIV_EN | PLL_INPUT_DIV_EN);
>  	dw_mipi_dsi_phy_write(dsi, 0x17, INPUT_DIVIDER(dsi->input_div));
>  	dw_mipi_dsi_phy_write(dsi, 0x18, LOOP_DIV_LOW_SEL(dsi->feedback_div) |
>  					 LOW_PROGRAM_EN);
>  	dw_mipi_dsi_phy_write(dsi, 0x18, LOOP_DIV_HIGH_SEL(dsi->feedback_div) |
>  					 HIGH_PROGRAM_EN);
> +	dw_mipi_dsi_phy_write(dsi, 0x19, PLL_LOOP_DIV_EN | PLL_INPUT_DIV_EN);
> +
> +	dw_mipi_dsi_phy_write(dsi, 0x22, LOW_PROGRAM_EN |
> +					 BIASEXTR_SEL(BIASEXTR_127_7));
> +	dw_mipi_dsi_phy_write(dsi, 0x22, HIGH_PROGRAM_EN |
> +					 BANDGAP_SEL(BANDGAP_96_10));
>  
>  	dw_mipi_dsi_phy_write(dsi, 0x20, POWER_CONTROL | INTERNAL_REG_CURRENT |
>  					 BIAS_BLOCK_ON | BANDGAP_ON);
> @@ -429,10 +434,6 @@ static int dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi)
>  					 SETRD_MAX | POWER_MANAGE |
>  					 TER_RESISTORS_ON);
>  
> -	dw_mipi_dsi_phy_write(dsi, 0x22, LOW_PROGRAM_EN |
> -					 BIASEXTR_SEL(BIASEXTR_127_7));
> -	dw_mipi_dsi_phy_write(dsi, 0x22, HIGH_PROGRAM_EN |
> -					 BANDGAP_SEL(BANDGAP_96_10));
>  
>  	dw_mipi_dsi_phy_write(dsi, 0x70, TLP_PROGRAM_EN | 0xf);
>  	dw_mipi_dsi_phy_write(dsi, 0x71, THS_PRE_PROGRAM_EN | 0x55);
> -- 
> 2.11.0.197.gb556de5.dirty
> 
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel

-- 
Sean Paul, Software Engineer, Google / Chromium OS

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#1570680 — Re: [PATCH v3 15/24] drm/rockchip: dw-mipi-dsi: configure PHY before enabling

FromJohn Keeping <john@metanate.com>
Date2017-01-31 13:40 +0100
SubjectRe: [PATCH v3 15/24] drm/rockchip: dw-mipi-dsi: configure PHY before enabling
Message-ID<t5FT4-Ha-17@gated-at.bofh.it>
In reply to#1570099
On Mon, 30 Jan 2017 15:28:08 -0500, Sean Paul wrote:

> On Sun, Jan 29, 2017 at 01:24:35PM +0000, John Keeping wrote:
> > The bias, bandgap and PLL should all be configured before we enable
> > them.
> >   
> 
> Do you know why the test codes are hard-coded magic? It'd be nice to make some
> sense of them in a future patch.

I just kept with the existing style of the code, but it should be
straightforward to add some defines with sensible names.

> Reviewed-by: Sean Paul <seanpaul@chromium.org>
> 
> > Signed-off-by: John Keeping <john@metanate.com>
> > ---
> > v3:
> > - Squash together two patches that both affect initialization order of
> >   the PHY
> > Unchanged in v2
> > 
> >  drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 11 ++++++-----
> >  1 file changed, 6 insertions(+), 5 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
> > index 5b3068e9e8db..cfe7e4ba305c 100644
> > --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
> > +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
> > @@ -413,12 +413,17 @@ static int dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi)
> >  
> >  	dw_mipi_dsi_phy_write(dsi, 0x44, HSFREQRANGE_SEL(testdin));
> >  
> > -	dw_mipi_dsi_phy_write(dsi, 0x19, PLL_LOOP_DIV_EN | PLL_INPUT_DIV_EN);
> >  	dw_mipi_dsi_phy_write(dsi, 0x17, INPUT_DIVIDER(dsi->input_div));
> >  	dw_mipi_dsi_phy_write(dsi, 0x18, LOOP_DIV_LOW_SEL(dsi->feedback_div) |
> >  					 LOW_PROGRAM_EN);
> >  	dw_mipi_dsi_phy_write(dsi, 0x18, LOOP_DIV_HIGH_SEL(dsi->feedback_div) |
> >  					 HIGH_PROGRAM_EN);
> > +	dw_mipi_dsi_phy_write(dsi, 0x19, PLL_LOOP_DIV_EN | PLL_INPUT_DIV_EN);
> > +
> > +	dw_mipi_dsi_phy_write(dsi, 0x22, LOW_PROGRAM_EN |
> > +					 BIASEXTR_SEL(BIASEXTR_127_7));
> > +	dw_mipi_dsi_phy_write(dsi, 0x22, HIGH_PROGRAM_EN |
> > +					 BANDGAP_SEL(BANDGAP_96_10));
> >  
> >  	dw_mipi_dsi_phy_write(dsi, 0x20, POWER_CONTROL | INTERNAL_REG_CURRENT |
> >  					 BIAS_BLOCK_ON | BANDGAP_ON);
> > @@ -429,10 +434,6 @@ static int dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi)
> >  					 SETRD_MAX | POWER_MANAGE |
> >  					 TER_RESISTORS_ON);
> >  
> > -	dw_mipi_dsi_phy_write(dsi, 0x22, LOW_PROGRAM_EN |
> > -					 BIASEXTR_SEL(BIASEXTR_127_7));
> > -	dw_mipi_dsi_phy_write(dsi, 0x22, HIGH_PROGRAM_EN |
> > -					 BANDGAP_SEL(BANDGAP_96_10));
> >  
> >  	dw_mipi_dsi_phy_write(dsi, 0x70, TLP_PROGRAM_EN | 0xf);
> >  	dw_mipi_dsi_phy_write(dsi, 0x71, THS_PRE_PROGRAM_EN | 0x55);
> > -- 
> > 2.11.0.197.gb556de5.dirty
> > 
> > _______________________________________________
> > dri-devel mailing list
> > dri-devel@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/dri-devel  
>

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#1569205 — [PATCH v3 19/24] drm/rockchip: dw-mipi-dsi: use positive check for N{H,V}SYNC

FromJohn Keeping <john@metanate.com>
Date2017-01-29 16:20 +0100
Subject[PATCH v3 19/24] drm/rockchip: dw-mipi-dsi: use positive check for N{H,V}SYNC
Message-ID<t4ZqN-cH-3@gated-at.bofh.it>
In reply to#1569191
This matches other drivers.

Signed-off-by: John Keeping <john@metanate.com>
---
Unchanged in v3
Unchanged in v2

 drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
index be395c3c5c06..f5b15377ef85 100644
--- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
@@ -774,9 +774,9 @@ static void dw_mipi_dsi_dpi_config(struct dw_mipi_dsi *dsi,
 		break;
 	}
 
-	if (!(mode->flags & DRM_MODE_FLAG_PVSYNC))
+	if (mode->flags & DRM_MODE_FLAG_NVSYNC)
 		val |= VSYNC_ACTIVE_LOW;
-	if (!(mode->flags & DRM_MODE_FLAG_PHSYNC))
+	if (mode->flags & DRM_MODE_FLAG_NHSYNC)
 		val |= HSYNC_ACTIVE_LOW;
 
 	dsi_write(dsi, DSI_DPI_VCID, DPI_VID(dsi->channel));
-- 
2.11.0.197.gb556de5.dirty

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#1571017 — Re: [PATCH v3 19/24] drm/rockchip: dw-mipi-dsi: use positive check for N{H, V}SYNC

FromSean Paul <seanpaul@chromium.org>
Date2017-01-31 20:20 +0100
SubjectRe: [PATCH v3 19/24] drm/rockchip: dw-mipi-dsi: use positive check for N{H, V}SYNC
Message-ID<t5M8a-4ww-9@gated-at.bofh.it>
In reply to#1569205
On Sun, Jan 29, 2017 at 01:24:39PM +0000, John Keeping wrote:
> This matches other drivers.
> 

Reviewed-by: Sean Paul <seanpaul@chromium.org>

> Signed-off-by: John Keeping <john@metanate.com>
> ---
> Unchanged in v3
> Unchanged in v2
> 
>  drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
> index be395c3c5c06..f5b15377ef85 100644
> --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
> +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
> @@ -774,9 +774,9 @@ static void dw_mipi_dsi_dpi_config(struct dw_mipi_dsi *dsi,
>  		break;
>  	}
>  
> -	if (!(mode->flags & DRM_MODE_FLAG_PVSYNC))
> +	if (mode->flags & DRM_MODE_FLAG_NVSYNC)
>  		val |= VSYNC_ACTIVE_LOW;
> -	if (!(mode->flags & DRM_MODE_FLAG_PHSYNC))
> +	if (mode->flags & DRM_MODE_FLAG_NHSYNC)
>  		val |= HSYNC_ACTIVE_LOW;
>  
>  	dsi_write(dsi, DSI_DPI_VCID, DPI_VID(dsi->channel));
> -- 
> 2.11.0.197.gb556de5.dirty
> 
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel

-- 
Sean Paul, Software Engineer, Google / Chromium OS

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#1569211 — [PATCH v3 17/24] drm/rockchip: dw-mipi-dsi: improve PLL configuration

FromJohn Keeping <john@metanate.com>
Date2017-01-29 16:20 +0100
Subject[PATCH v3 17/24] drm/rockchip: dw-mipi-dsi: improve PLL configuration
Message-ID<t4ZqO-cH-29@gated-at.bofh.it>
In reply to#1569191
The multiplication ratio for the PLL is required to be even due to the
use of a "by 2 pre-scaler".  Currently we are likely to end up with an
odd multiplier even though there is an equivalent set of parameters with
an even multiplier.

For example, using the 324MHz bit rate with a reference clock of 24MHz
we end up with M = 27, N = 2 whereas the example in the PHY databook
gives M = 54, N = 4 for this bit rate and reference clock.

By walking down through the available multiplier instead of up we are
more likely to hit an even multiplier.  With the above example we do now
get M = 54, N = 4 as given by the databook.

While doing this, change the loop limits to encode the actual limits on
the divisor, which are:

	40MHz >= (pllref / N) >= 5MHz

Signed-off-by: John Keeping <john@metanate.com>
---
Unchanged in v3
Unchanged in v2

 drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
index 85edf6dd2bac..dcb66a21e1f1 100644
--- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
@@ -522,7 +522,7 @@ static int dw_mipi_dsi_get_lane_bps(struct dw_mipi_dsi *dsi,
 	pllref = DIV_ROUND_UP(clk_get_rate(dsi->pllref_clk), USEC_PER_SEC);
 	tmp = pllref;
 
-	for (i = 1; i < 6; i++) {
+	for (i = pllref / 5; i > (pllref / 40); i--) {
 		pre = pllref / i;
 		if ((tmp > (target_mbps % pre)) && (target_mbps / pre < 512)) {
 			tmp = target_mbps % pre;
-- 
2.11.0.197.gb556de5.dirty

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#1571020 — Re: [PATCH v3 17/24] drm/rockchip: dw-mipi-dsi: improve PLL configuration

FromSean Paul <seanpaul@chromium.org>
Date2017-01-31 20:20 +0100
SubjectRe: [PATCH v3 17/24] drm/rockchip: dw-mipi-dsi: improve PLL configuration
Message-ID<t5M8a-4ww-25@gated-at.bofh.it>
In reply to#1569211
On Sun, Jan 29, 2017 at 01:24:37PM +0000, John Keeping wrote:
> The multiplication ratio for the PLL is required to be even due to the
> use of a "by 2 pre-scaler".  Currently we are likely to end up with an
> odd multiplier even though there is an equivalent set of parameters with
> an even multiplier.
> 
> For example, using the 324MHz bit rate with a reference clock of 24MHz
> we end up with M = 27, N = 2 whereas the example in the PHY databook
> gives M = 54, N = 4 for this bit rate and reference clock.
> 
> By walking down through the available multiplier instead of up we are
> more likely to hit an even multiplier.  With the above example we do now
> get M = 54, N = 4 as given by the databook.
> 
> While doing this, change the loop limits to encode the actual limits on
> the divisor, which are:
> 
> 	40MHz >= (pllref / N) >= 5MHz
> 
> Signed-off-by: John Keeping <john@metanate.com>
> ---
> Unchanged in v3
> Unchanged in v2
> 
>  drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
> index 85edf6dd2bac..dcb66a21e1f1 100644
> --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
> +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
> @@ -522,7 +522,7 @@ static int dw_mipi_dsi_get_lane_bps(struct dw_mipi_dsi *dsi,
>  	pllref = DIV_ROUND_UP(clk_get_rate(dsi->pllref_clk), USEC_PER_SEC);
>  	tmp = pllref;
>  
> -	for (i = 1; i < 6; i++) {
> +	for (i = pllref / 5; i > (pllref / 40); i--) {

I've convinced myself that this is right, but it took reading through the commit
message a few times. I think this code would benefit greatly from a comment so
readers don't need to go through git history.

With that,

Reviewed-by: Sean Paul <seanpaul@chromium.org>


>  		pre = pllref / i;
>  		if ((tmp > (target_mbps % pre)) && (target_mbps / pre < 512)) {
>  			tmp = target_mbps % pre;
> -- 
> 2.11.0.197.gb556de5.dirty
> 
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel

-- 
Sean Paul, Software Engineer, Google / Chromium OS

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#1569213 — [PATCH v3 23/24] drm/rockchip: dw-mipi-dsi: add reset control

FromJohn Keeping <john@metanate.com>
Date2017-01-29 16:30 +0100
Subject[PATCH v3 23/24] drm/rockchip: dw-mipi-dsi: add reset control
Message-ID<t4ZAt-ge-5@gated-at.bofh.it>
In reply to#1569191
In order to fully reset the state of the MIPI controller we must assert
this reset.

This is slightly more complicated than it could be in order to maintain
compatibility with device trees that do not specify the reset property.

Signed-off-by: John Keeping <john@metanate.com>
Reviewed-by: Chris Zhong <zyw@rock-chips.com>
---
v3:
- Add Chris' Reviewed-by
Unchanged in v2

 drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 30 ++++++++++++++++++++++++++++++
 1 file changed, 30 insertions(+)

diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
index 58cb8ace2fe8..cf3ca6b0cbdb 100644
--- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
@@ -13,6 +13,7 @@
 #include <linux/module.h>
 #include <linux/of_device.h>
 #include <linux/regmap.h>
+#include <linux/reset.h>
 #include <linux/mfd/syscon.h>
 #include <drm/drm_atomic_helper.h>
 #include <drm/drm_crtc.h>
@@ -1124,6 +1125,7 @@ static int dw_mipi_dsi_bind(struct device *dev, struct device *master,
 			of_match_device(dw_mipi_dsi_dt_ids, dev);
 	const struct dw_mipi_dsi_plat_data *pdata = of_id->data;
 	struct platform_device *pdev = to_platform_device(dev);
+	struct reset_control *apb_rst;
 	struct drm_device *drm = data;
 	struct dw_mipi_dsi *dsi;
 	struct resource *res;
@@ -1162,6 +1164,34 @@ static int dw_mipi_dsi_bind(struct device *dev, struct device *master,
 		return ret;
 	}
 
+	/*
+	 * Note that the reset was not defined in the initial device tree, so
+	 * we have to be prepared for it not being found.
+	 */
+	apb_rst = devm_reset_control_get(dev, "apb");
+	if (IS_ERR(apb_rst)) {
+		if (PTR_ERR(apb_rst) == -ENODEV) {
+			apb_rst = NULL;
+		} else {
+			dev_err(dev, "Unable to get reset control: %d\n", ret);
+			return PTR_ERR(apb_rst);
+		}
+	}
+
+	if (apb_rst) {
+		ret = clk_prepare_enable(dsi->pclk);
+		if (ret) {
+			dev_err(dev, "%s: Failed to enable pclk\n", __func__);
+			return ret;
+		}
+
+		reset_control_assert(apb_rst);
+		usleep_range(10, 20);
+		reset_control_deassert(apb_rst);
+
+		clk_disable_unprepare(dsi->pclk);
+	}
+
 	ret = clk_prepare_enable(dsi->pllref_clk);
 	if (ret) {
 		dev_err(dev, "%s: Failed to enable pllref_clk\n", __func__);
-- 
2.11.0.197.gb556de5.dirty

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#1571032 — Re: [PATCH v3 23/24] drm/rockchip: dw-mipi-dsi: add reset control

FromSean Paul <seanpaul@chromium.org>
Date2017-01-31 20:30 +0100
SubjectRe: [PATCH v3 23/24] drm/rockchip: dw-mipi-dsi: add reset control
Message-ID<t5MhR-4zG-35@gated-at.bofh.it>
In reply to#1569213
On Sun, Jan 29, 2017 at 01:24:43PM +0000, John Keeping wrote:
> In order to fully reset the state of the MIPI controller we must assert
> this reset.
> 
> This is slightly more complicated than it could be in order to maintain
> compatibility with device trees that do not specify the reset property.
> 

I always find it a little grating to see a device managed resource given to a
local variable that is used immediately and only once. However, I think this
might just be one of my twitches. So now that I've aired my grievance, 

Reviewed-by: Sean Paul <seanpaul@chromium.org>

> Signed-off-by: John Keeping <john@metanate.com>
> Reviewed-by: Chris Zhong <zyw@rock-chips.com>
> ---
> v3:
> - Add Chris' Reviewed-by
> Unchanged in v2
> 
>  drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 30 ++++++++++++++++++++++++++++++
>  1 file changed, 30 insertions(+)
> 
> diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
> index 58cb8ace2fe8..cf3ca6b0cbdb 100644
> --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
> +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
> @@ -13,6 +13,7 @@
>  #include <linux/module.h>
>  #include <linux/of_device.h>
>  #include <linux/regmap.h>
> +#include <linux/reset.h>
>  #include <linux/mfd/syscon.h>
>  #include <drm/drm_atomic_helper.h>
>  #include <drm/drm_crtc.h>
> @@ -1124,6 +1125,7 @@ static int dw_mipi_dsi_bind(struct device *dev, struct device *master,
>  			of_match_device(dw_mipi_dsi_dt_ids, dev);
>  	const struct dw_mipi_dsi_plat_data *pdata = of_id->data;
>  	struct platform_device *pdev = to_platform_device(dev);
> +	struct reset_control *apb_rst;
>  	struct drm_device *drm = data;
>  	struct dw_mipi_dsi *dsi;
>  	struct resource *res;
> @@ -1162,6 +1164,34 @@ static int dw_mipi_dsi_bind(struct device *dev, struct device *master,
>  		return ret;
>  	}
>  
> +	/*
> +	 * Note that the reset was not defined in the initial device tree, so
> +	 * we have to be prepared for it not being found.
> +	 */
> +	apb_rst = devm_reset_control_get(dev, "apb");
> +	if (IS_ERR(apb_rst)) {
> +		if (PTR_ERR(apb_rst) == -ENODEV) {
> +			apb_rst = NULL;
> +		} else {
> +			dev_err(dev, "Unable to get reset control: %d\n", ret);
> +			return PTR_ERR(apb_rst);
> +		}
> +	}
> +
> +	if (apb_rst) {
> +		ret = clk_prepare_enable(dsi->pclk);
> +		if (ret) {
> +			dev_err(dev, "%s: Failed to enable pclk\n", __func__);
> +			return ret;
> +		}
> +
> +		reset_control_assert(apb_rst);
> +		usleep_range(10, 20);
> +		reset_control_deassert(apb_rst);
> +
> +		clk_disable_unprepare(dsi->pclk);
> +	}
> +
>  	ret = clk_prepare_enable(dsi->pllref_clk);
>  	if (ret) {
>  		dev_err(dev, "%s: Failed to enable pllref_clk\n", __func__);
> -- 
> 2.11.0.197.gb556de5.dirty
> 
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel

-- 
Sean Paul, Software Engineer, Google / Chromium OS

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#1569214 — [PATCH v3 03/24] drm/rockchip: dw-mipi-dsi: remove mode_set hook

FromJohn Keeping <john@metanate.com>
Date2017-01-29 16:30 +0100
Subject[PATCH v3 03/24] drm/rockchip: dw-mipi-dsi: remove mode_set hook
Message-ID<t4ZAu-ge-19@gated-at.bofh.it>
In reply to#1569191
This is not needed since we can access the mode via the CRTC from the
enable hook.  Also remove the "mode" field that is no longer used.

Signed-off-by: John Keeping <john@metanate.com>
Reviewed-by: Chris Zhong <zyw@rock-chips.com>
---
v3:
- Add Chris' Reviewed-by
New in v2

 drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 13 +------------
 1 file changed, 1 insertion(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
index cdbd25087e83..bd92e58b64f3 100644
--- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
@@ -286,7 +286,6 @@ struct dw_mipi_dsi {
 	u32 format;
 	u16 input_div;
 	u16 feedback_div;
-	struct drm_display_mode *mode;
 
 	const struct dw_mipi_dsi_plat_data *pdata;
 };
@@ -816,15 +815,6 @@ static void dw_mipi_dsi_clear_err(struct dw_mipi_dsi *dsi)
 	dsi_write(dsi, DSI_INT_MSK1, 0);
 }
 
-static void dw_mipi_dsi_encoder_mode_set(struct drm_encoder *encoder,
-					struct drm_display_mode *mode,
-					struct drm_display_mode *adjusted_mode)
-{
-	struct dw_mipi_dsi *dsi = encoder_to_dsi(encoder);
-
-	dsi->mode = adjusted_mode;
-}
-
 static void dw_mipi_dsi_encoder_disable(struct drm_encoder *encoder)
 {
 	struct dw_mipi_dsi *dsi = encoder_to_dsi(encoder);
@@ -854,7 +844,7 @@ static void dw_mipi_dsi_encoder_disable(struct drm_encoder *encoder)
 static void dw_mipi_dsi_encoder_enable(struct drm_encoder *encoder)
 {
 	struct dw_mipi_dsi *dsi = encoder_to_dsi(encoder);
-	struct drm_display_mode *mode = dsi->mode;
+	struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
 	int mux = drm_of_encoder_active_endpoint_id(dsi->dev->of_node, encoder);
 	u32 val;
 	int ret;
@@ -930,7 +920,6 @@ dw_mipi_dsi_encoder_atomic_check(struct drm_encoder *encoder,
 static struct drm_encoder_helper_funcs
 dw_mipi_dsi_encoder_helper_funcs = {
 	.enable = dw_mipi_dsi_encoder_enable,
-	.mode_set = dw_mipi_dsi_encoder_mode_set,
 	.disable = dw_mipi_dsi_encoder_disable,
 	.atomic_check = dw_mipi_dsi_encoder_atomic_check,
 };
-- 
2.11.0.197.gb556de5.dirty

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#1569850 — Re: [PATCH v3 03/24] drm/rockchip: dw-mipi-dsi: remove mode_set hook

FromSean Paul <seanpaul@chromium.org>
Date2017-01-30 16:50 +0100
SubjectRe: [PATCH v3 03/24] drm/rockchip: dw-mipi-dsi: remove mode_set hook
Message-ID<t5mno-5Iu-13@gated-at.bofh.it>
In reply to#1569214
On Sun, Jan 29, 2017 at 01:24:23PM +0000, John Keeping wrote:
> This is not needed since we can access the mode via the CRTC from the
> enable hook.  Also remove the "mode" field that is no longer used.
> 

Reviewed-by: Sean Paul <seanpaul@chromium.org>

> Signed-off-by: John Keeping <john@metanate.com>
> Reviewed-by: Chris Zhong <zyw@rock-chips.com>
> ---
> v3:
> - Add Chris' Reviewed-by
> New in v2
> 
>  drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 13 +------------
>  1 file changed, 1 insertion(+), 12 deletions(-)
> 
> diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
> index cdbd25087e83..bd92e58b64f3 100644
> --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
> +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
> @@ -286,7 +286,6 @@ struct dw_mipi_dsi {
>  	u32 format;
>  	u16 input_div;
>  	u16 feedback_div;
> -	struct drm_display_mode *mode;
>  
>  	const struct dw_mipi_dsi_plat_data *pdata;
>  };
> @@ -816,15 +815,6 @@ static void dw_mipi_dsi_clear_err(struct dw_mipi_dsi *dsi)
>  	dsi_write(dsi, DSI_INT_MSK1, 0);
>  }
>  
> -static void dw_mipi_dsi_encoder_mode_set(struct drm_encoder *encoder,
> -					struct drm_display_mode *mode,
> -					struct drm_display_mode *adjusted_mode)
> -{
> -	struct dw_mipi_dsi *dsi = encoder_to_dsi(encoder);
> -
> -	dsi->mode = adjusted_mode;
> -}
> -
>  static void dw_mipi_dsi_encoder_disable(struct drm_encoder *encoder)
>  {
>  	struct dw_mipi_dsi *dsi = encoder_to_dsi(encoder);
> @@ -854,7 +844,7 @@ static void dw_mipi_dsi_encoder_disable(struct drm_encoder *encoder)
>  static void dw_mipi_dsi_encoder_enable(struct drm_encoder *encoder)
>  {
>  	struct dw_mipi_dsi *dsi = encoder_to_dsi(encoder);
> -	struct drm_display_mode *mode = dsi->mode;
> +	struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
>  	int mux = drm_of_encoder_active_endpoint_id(dsi->dev->of_node, encoder);
>  	u32 val;
>  	int ret;
> @@ -930,7 +920,6 @@ dw_mipi_dsi_encoder_atomic_check(struct drm_encoder *encoder,
>  static struct drm_encoder_helper_funcs
>  dw_mipi_dsi_encoder_helper_funcs = {
>  	.enable = dw_mipi_dsi_encoder_enable,
> -	.mode_set = dw_mipi_dsi_encoder_mode_set,
>  	.disable = dw_mipi_dsi_encoder_disable,
>  	.atomic_check = dw_mipi_dsi_encoder_atomic_check,
>  };
> -- 
> 2.11.0.197.gb556de5.dirty
> 
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel

-- 
Sean Paul, Software Engineer, Google / Chromium OS

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