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[PATCH v3 17/24] drm/rockchip: dw-mipi-dsi: improve PLL configuration

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The multiplication ratio for the PLL is required to be even due to the
use of a "by 2 pre-scaler".  Currently we are likely to end up with an
odd multiplier even though there is an equivalent set of parameters with
an even multiplier.

For example, using the 324MHz bit rate with a reference clock of 24MHz
we end up with M = 27, N = 2 whereas the example in the PHY databook
gives M = 54, N = 4 for this bit rate and reference clock.

By walking down through the available multiplier instead of up we are
more likely to hit an even multiplier.  With the above example we do now
get M = 54, N = 4 as given by the databook.

While doing this, change the loop limits to encode the actual limits on
the divisor, which are:

	40MHz >= (pllref / N) >= 5MHz

Signed-off-by: John Keeping <john@metanate.com>
---
Unchanged in v3
Unchanged in v2

 drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
index 85edf6dd2bac..dcb66a21e1f1 100644
--- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
@@ -522,7 +522,7 @@ static int dw_mipi_dsi_get_lane_bps(struct dw_mipi_dsi *dsi,
 	pllref = DIV_ROUND_UP(clk_get_rate(dsi->pllref_clk), USEC_PER_SEC);
 	tmp = pllref;
 
-	for (i = 1; i < 6; i++) {
+	for (i = pllref / 5; i > (pllref / 40); i--) {
 		pre = pllref / i;
 		if ((tmp > (target_mbps % pre)) && (target_mbps / pre < 512)) {
 			tmp = target_mbps % pre;
-- 
2.11.0.197.gb556de5.dirty

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Thread

[PATCH v3 00/24] drm/rockchip: MIPI fixes & improvements John Keeping <john@metanate.com> - 2017-01-29 15:10 +0100
  [PATCH v3 08/24] drm/rockchip: dw-mipi-dsi: respect message flags John Keeping <john@metanate.com> - 2017-01-29 15:10 +0100
    Re: [PATCH v3 08/24] drm/rockchip: dw-mipi-dsi: respect message flags Sean Paul <seanpaul@chromium.org> - 2017-01-30 19:30 +0100
  [PATCH v3 01/24] drm/rockchip: dw-mipi-dsi: don't configure hardware in mode_set for MIPI John Keeping <john@metanate.com> - 2017-01-29 15:10 +0100
    Re: [PATCH v3 01/24] drm/rockchip: dw-mipi-dsi: don't configure  hardware in mode_set for MIPI Sean Paul <seanpaul@chromium.org> - 2017-01-30 16:40 +0100
  [PATCH v3 24/24] drm/rockchip: dw-mipi-dsi: support read commands John Keeping <john@metanate.com> - 2017-01-29 15:50 +0100
    Re: [PATCH v3 24/24] drm/rockchip: dw-mipi-dsi: support read commands Sean Paul <seanpaul@chromium.org> - 2017-01-30 16:40 +0100
      Re: [PATCH v3 24/24] drm/rockchip: dw-mipi-dsi: support read  commands John Keeping <john@metanate.com> - 2017-01-30 19:40 +0100
  [PATCH v3 11/24] drm/rockchip: dw-mipi-dsi: prepare panel after phy init John Keeping <john@metanate.com> - 2017-01-29 15:50 +0100
  [PATCH v3 05/24] drm/rockchip: dw-mipi-dsi: fix generic packet status check John Keeping <john@metanate.com> - 2017-01-29 15:50 +0100
    Re: [PATCH v3 05/24] drm/rockchip: dw-mipi-dsi: fix generic packet  status check Sean Paul <seanpaul@chromium.org> - 2017-01-30 19:30 +0100
  [PATCH v3 07/24] drm/rockchip: dw-mipi-dsi: include bad value in error message John Keeping <john@metanate.com> - 2017-01-29 15:50 +0100
    Re: [PATCH v3 07/24] drm/rockchip: dw-mipi-dsi: include bad value in  error message Sean Paul <seanpaul@chromium.org> - 2017-01-30 19:10 +0100
  [PATCH v3 20/24] drm/rockchip: vop: test for P{H,V}SYNC John Keeping <john@metanate.com> - 2017-01-29 15:50 +0100
  [PATCH v3 12/24] drm/rockchip: dw-mipi-dsi: allow commands in panel_disable John Keeping <john@metanate.com> - 2017-01-29 15:50 +0100
  [PATCH v3 13/24] drm/rockchip: dw-mipi-dsi: fix escape clock rate John Keeping <john@metanate.com> - 2017-01-29 15:50 +0100
  [PATCH v3 18/24] drm/rockchip: dw-mipi-dsi: use specific poll helper John Keeping <john@metanate.com> - 2017-01-29 15:50 +0100
  [PATCH v3 04/24] drm/rockchip: dw-mipi-dsi: fix command header writes John Keeping <john@metanate.com> - 2017-01-29 15:50 +0100
    Re: [PATCH v3 04/24] drm/rockchip: dw-mipi-dsi: fix command header  writes Sean Paul <seanpaul@chromium.org> - 2017-01-30 17:00 +0100
  [PATCH v3 15/24] drm/rockchip: dw-mipi-dsi: configure PHY before enabling John Keeping <john@metanate.com> - 2017-01-29 15:50 +0100
  [PATCH v3 19/24] drm/rockchip: dw-mipi-dsi: use positive check for N{H,V}SYNC John Keeping <john@metanate.com> - 2017-01-29 16:20 +0100
  [PATCH v3 17/24] drm/rockchip: dw-mipi-dsi: improve PLL configuration John Keeping <john@metanate.com> - 2017-01-29 16:20 +0100
  [PATCH v3 23/24] drm/rockchip: dw-mipi-dsi: add reset control John Keeping <john@metanate.com> - 2017-01-29 16:30 +0100
  [PATCH v3 03/24] drm/rockchip: dw-mipi-dsi: remove mode_set hook John Keeping <john@metanate.com> - 2017-01-29 16:30 +0100
    Re: [PATCH v3 03/24] drm/rockchip: dw-mipi-dsi: remove mode_set hook Sean Paul <seanpaul@chromium.org> - 2017-01-30 16:50 +0100
  [PATCH v3 22/24] drm/rockchip: dw-mipi-dsi: support non-burst modes John Keeping <john@metanate.com> - 2017-01-29 16:30 +0100

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