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| Started by | Corentin Labbe <clabbe.montjoie@gmail.com> |
|---|---|
| First post | 2017-01-16 20:40 +0100 |
| Last post | 2017-01-25 10:20 +0100 |
| Articles | 2 — 2 participants |
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Re: [PATCH v3 8/13] arm64: allwinner: a64: Add MMC nodes Corentin Labbe <clabbe.montjoie@gmail.com> - 2017-01-16 20:40 +0100
Re: [PATCH v3 8/13] arm64: allwinner: a64: Add MMC nodes Maxime Ripard <maxime.ripard@free-electrons.com> - 2017-01-25 10:20 +0100
| From | Corentin Labbe <clabbe.montjoie@gmail.com> |
|---|---|
| Date | 2017-01-16 20:40 +0100 |
| Subject | Re: [PATCH v3 8/13] arm64: allwinner: a64: Add MMC nodes |
| Message-ID | <t0lii-54V-19@gated-at.bofh.it> |
On Mon, Jan 16, 2017 at 05:56:58PM +0100, Maxime Ripard wrote:
> From: Andre Przywara <andre.przywara@arm.com>
>
> The A64 has 3 MMC controllers, one of them being especially targeted to
> eMMC. Among other things, it has a data strobe signal and a 8 bits data
> width.
>
> The two other are more usual controllers that will have a 4 bits width at
> most and no data strobe signal, which limits it to more usual SD or MMC
> peripherals.
>
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> ---
> arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 39 ++++++++++++++++++++-
> 1 file changed, 39 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> index 99b6bb1e141c..143e9706438f 100644
> --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> @@ -299,6 +299,45 @@
> #size-cells = <0>;
> };
>
> + mmc0: mmc@1c0f000 {
> + compatible = "allwinner,sun50i-a64-mmc";
> + reg = <0x01c0f000 0x1000>;
> + clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
> + clock-names = "ahb", "mmc";
> + resets = <&ccu RST_BUS_MMC0>;
> + reset-names = "ahb";
> + interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + mmc1: mmc@1c10000 {
> + compatible = "allwinner,sun50i-a64-mmc";
> + reg = <0x01c10000 0x1000>;
> + clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
> + clock-names = "ahb", "mmc";
> + resets = <&ccu RST_BUS_MMC1>;
> + reset-names = "ahb";
> + interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + mmc2: mmc@1c11000 {
> + compatible = "allwinner,sun50i-a64-emmc";
> + reg = <0x01c11000 0x1000>;
> + clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
> + clock-names = "ahb", "mmc";
> + resets = <&ccu RST_BUS_MMC2>;
> + reset-names = "ahb";
> + interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> gic: interrupt-controller@1c81000 {
> compatible = "arm,gic-400";
> reg = <0x01c81000 0x1000>,
Hello
It seems that mmc node is after i2c@1c2b400 so not in address order.
Regards
Corentin Labbe
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| From | Maxime Ripard <maxime.ripard@free-electrons.com> |
|---|---|
| Date | 2017-01-25 10:20 +0100 |
| Message-ID | <t3rUd-8k5-15@gated-at.bofh.it> |
| In reply to | #1560014 |
[Multipart message — attachments visible in raw view] — view raw
Hi Corentin,
On Mon, Jan 16, 2017 at 08:16:41PM +0100, Corentin Labbe wrote:
> On Mon, Jan 16, 2017 at 05:56:58PM +0100, Maxime Ripard wrote:
> > From: Andre Przywara <andre.przywara@arm.com>
> >
> > The A64 has 3 MMC controllers, one of them being especially targeted to
> > eMMC. Among other things, it has a data strobe signal and a 8 bits data
> > width.
> >
> > The two other are more usual controllers that will have a 4 bits width at
> > most and no data strobe signal, which limits it to more usual SD or MMC
> > peripherals.
> >
> > Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> > Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> > ---
> > arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 39 ++++++++++++++++++++-
> > 1 file changed, 39 insertions(+), 0 deletions(-)
> >
> > diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> > index 99b6bb1e141c..143e9706438f 100644
> > --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> > +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> > @@ -299,6 +299,45 @@
> > #size-cells = <0>;
> > };
> >
> > + mmc0: mmc@1c0f000 {
> > + compatible = "allwinner,sun50i-a64-mmc";
> > + reg = <0x01c0f000 0x1000>;
> > + clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
> > + clock-names = "ahb", "mmc";
> > + resets = <&ccu RST_BUS_MMC0>;
> > + reset-names = "ahb";
> > + interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
> > + status = "disabled";
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + };
> > +
> > + mmc1: mmc@1c10000 {
> > + compatible = "allwinner,sun50i-a64-mmc";
> > + reg = <0x01c10000 0x1000>;
> > + clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
> > + clock-names = "ahb", "mmc";
> > + resets = <&ccu RST_BUS_MMC1>;
> > + reset-names = "ahb";
> > + interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
> > + status = "disabled";
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + };
> > +
> > + mmc2: mmc@1c11000 {
> > + compatible = "allwinner,sun50i-a64-emmc";
> > + reg = <0x01c11000 0x1000>;
> > + clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
> > + clock-names = "ahb", "mmc";
> > + resets = <&ccu RST_BUS_MMC2>;
> > + reset-names = "ahb";
> > + interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
> > + status = "disabled";
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + };
> > +
> > gic: interrupt-controller@1c81000 {
> > compatible = "arm,gic-400";
> > reg = <0x01c81000 0x1000>,
>
> Hello
>
> It seems that mmc node is after i2c@1c2b400 so not in address order.
You're right, I'll fix this in the v3.
Thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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