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[PATCH v2, 1/6] phy: phy-mt65xx-usb3: split SuperSpeed port into two ones

Started byChunfeng Yun <chunfeng.yun@mediatek.com>
First post2017-01-20 09:30 +0100
Last post2017-01-27 21:10 +0100
Articles 5 — 3 participants

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Contents

  [PATCH v2, 1/6] phy: phy-mt65xx-usb3: split SuperSpeed port into two ones Chunfeng Yun <chunfeng.yun@mediatek.com> - 2017-01-20 09:30 +0100
    [PATCH v2, 5/6] arm64: dts: mt8173: move clock from phy node into port nodes Chunfeng Yun <chunfeng.yun@mediatek.com> - 2017-01-20 09:30 +0100
    [PATCH v2, 6/6] dt-bindings: phy-mt65xx-usb: add support for new version phy Chunfeng Yun <chunfeng.yun@mediatek.com> - 2017-01-20 09:30 +0100
      Re: [PATCH v2, 6/6] dt-bindings: phy-mt65xx-usb: add support for new  version phy Matthias Brugger <matthias.bgg@gmail.com> - 2017-01-24 16:30 +0100
      Re: [PATCH v2, 6/6] dt-bindings: phy-mt65xx-usb: add support for new  version phy Rob Herring <robh@kernel.org> - 2017-01-27 21:10 +0100

#1563370 — [PATCH v2, 1/6] phy: phy-mt65xx-usb3: split SuperSpeed port into two ones

FromChunfeng Yun <chunfeng.yun@mediatek.com>
Date2017-01-20 09:30 +0100
Subject[PATCH v2, 1/6] phy: phy-mt65xx-usb3: split SuperSpeed port into two ones
Message-ID<t1CK6-4SH-3@gated-at.bofh.it>
Currently usb3 port in fact includes two sub-ports, but it is not
flexible for some cases, such as following one:
    usb3 port0 includes u2port0 and u3port0;
    usb2 port0 includes u2port1;
If wants to support only HS, we can use u2port0 or u2port1, when
select u2port0, u3port0 is not needed;
If wants to support SS, we can compound u2port0 and u3port0,
or u2port1 and u3port0, if select latter one, u2port0 is not needed.

So it's more flexible to split usb3 port into two ones and also try
best to save power by disabling unnecessary ports.

Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
 drivers/phy/phy-mt65xx-usb3.c |  119 +++++++++++++++++++++--------------------
 1 file changed, 60 insertions(+), 59 deletions(-)

diff --git a/drivers/phy/phy-mt65xx-usb3.c b/drivers/phy/phy-mt65xx-usb3.c
index d972067..93f57d9 100644
--- a/drivers/phy/phy-mt65xx-usb3.c
+++ b/drivers/phy/phy-mt65xx-usb3.c
@@ -30,11 +30,11 @@
 #define SSUSB_SIFSLV_SPLLC		0x0000
 #define SSUSB_SIFSLV_U2FREQ		0x0100
 
-/* offsets of sub-segment in each port registers */
+/* offsets of banks in each u2phy registers */
 #define SSUSB_SIFSLV_U2PHY_COM_BASE	0x0000
-#define SSUSB_SIFSLV_U3PHYD_BASE	0x0100
-#define SSUSB_USB30_PHYA_SIV_B_BASE	0x0300
-#define SSUSB_SIFSLV_U3PHYA_DA_BASE	0x0400
+/* offsets of banks in each u3phy registers */
+#define SSUSB_SIFSLV_U3PHYD_BASE	0x0000
+#define SSUSB_SIFSLV_U3PHYA_BASE	0x0200
 
 #define U3P_USBPHYACR0		(SSUSB_SIFSLV_U2PHY_COM_BASE + 0x0000)
 #define PA0_RG_U2PLL_FORCE_ON		BIT(15)
@@ -49,7 +49,6 @@
 #define PA5_RG_U2_HS_100U_U3_EN	BIT(11)
 
 #define U3P_USBPHYACR6		(SSUSB_SIFSLV_U2PHY_COM_BASE + 0x0018)
-#define PA6_RG_U2_ISO_EN		BIT(31)
 #define PA6_RG_U2_BC11_SW_EN		BIT(23)
 #define PA6_RG_U2_OTG_VBUSCMP_EN	BIT(20)
 #define PA6_RG_U2_SQTH		GENMASK(3, 0)
@@ -91,18 +90,18 @@
 #define P2C_RG_SESSEND			BIT(4)
 #define P2C_RG_AVALID			BIT(2)
 
-#define U3P_U3_PHYA_REG0	(SSUSB_USB30_PHYA_SIV_B_BASE + 0x0000)
+#define U3P_U3_PHYA_REG0	(SSUSB_SIFSLV_U3PHYA_BASE + 0x0000)
 #define P3A_RG_U3_VUSB10_ON		BIT(5)
 
-#define U3P_U3_PHYA_REG6	(SSUSB_USB30_PHYA_SIV_B_BASE + 0x0018)
+#define U3P_U3_PHYA_REG6	(SSUSB_SIFSLV_U3PHYA_BASE + 0x0018)
 #define P3A_RG_TX_EIDLE_CM		GENMASK(31, 28)
 #define P3A_RG_TX_EIDLE_CM_VAL(x)	((0xf & (x)) << 28)
 
-#define U3P_U3_PHYA_REG9	(SSUSB_USB30_PHYA_SIV_B_BASE + 0x0024)
+#define U3P_U3_PHYA_REG9	(SSUSB_SIFSLV_U3PHYA_BASE + 0x0024)
 #define P3A_RG_RX_DAC_MUX		GENMASK(5, 1)
 #define P3A_RG_RX_DAC_MUX_VAL(x)	((0x1f & (x)) << 1)
 
-#define U3P_U3PHYA_DA_REG0	(SSUSB_SIFSLV_U3PHYA_DA_BASE + 0x0000)
+#define U3P_U3PHYA_DA_REG0	(SSUSB_SIFSLV_U3PHYA_BASE + 0x0100)
 #define P3A_RG_XTAL_EXT_EN_U3		GENMASK(11, 10)
 #define P3A_RG_XTAL_EXT_EN_U3_VAL(x)	((0x3 & (x)) << 10)
 
@@ -148,7 +147,7 @@ struct mt65xx_phy_instance {
 
 struct mt65xx_u3phy {
 	struct device *dev;
-	void __iomem *sif_base;	/* include sif2, but exclude port's */
+	void __iomem *sif_base;	/* only shared sif */
 	struct clk *u3phya_ref;	/* reference clock of usb3 anolog phy */
 	const struct mt65xx_phy_pdata *pdata;
 	struct mt65xx_phy_instance **phys;
@@ -178,7 +177,7 @@ static void hs_slew_rate_calibrate(struct mt65xx_u3phy *u3phy,
 	tmp = readl(sif_base + U3P_U2FREQ_FMCR0);
 	tmp &= ~(P2F_RG_CYCLECNT | P2F_RG_MONCLK_SEL);
 	tmp |= P2F_RG_CYCLECNT_VAL(U3P_FM_DET_CYCLE_CNT);
-	tmp |= P2F_RG_MONCLK_SEL_VAL(instance->index);
+	tmp |= P2F_RG_MONCLK_SEL_VAL(instance->index >> 1);
 	writel(tmp, sif_base + U3P_U2FREQ_FMCR0);
 
 	/* enable frequency meter */
@@ -226,6 +225,41 @@ static void hs_slew_rate_calibrate(struct mt65xx_u3phy *u3phy,
 	writel(tmp, instance->port_base + U3P_USBPHYACR5);
 }
 
+static void u3_phy_instance_init(struct mt65xx_u3phy *u3phy,
+	struct mt65xx_phy_instance *instance)
+{
+	void __iomem *port_base = instance->port_base;
+	u32 tmp;
+
+	/* gating PCIe Analog XTAL clock */
+	tmp = readl(u3phy->sif_base + U3P_XTALCTL3);
+	tmp |= XC3_RG_U3_XTAL_RX_PWD | XC3_RG_U3_FRC_XTAL_RX_PWD;
+	writel(tmp, u3phy->sif_base + U3P_XTALCTL3);
+
+	/* gating XSQ */
+	tmp = readl(port_base + U3P_U3PHYA_DA_REG0);
+	tmp &= ~P3A_RG_XTAL_EXT_EN_U3;
+	tmp |= P3A_RG_XTAL_EXT_EN_U3_VAL(2);
+	writel(tmp, port_base + U3P_U3PHYA_DA_REG0);
+
+	tmp = readl(port_base + U3P_U3_PHYA_REG9);
+	tmp &= ~P3A_RG_RX_DAC_MUX;
+	tmp |= P3A_RG_RX_DAC_MUX_VAL(4);
+	writel(tmp, port_base + U3P_U3_PHYA_REG9);
+
+	tmp = readl(port_base + U3P_U3_PHYA_REG6);
+	tmp &= ~P3A_RG_TX_EIDLE_CM;
+	tmp |= P3A_RG_TX_EIDLE_CM_VAL(0xe);
+	writel(tmp, port_base + U3P_U3_PHYA_REG6);
+
+	tmp = readl(port_base + U3P_PHYD_CDR1);
+	tmp &= ~(P3D_RG_CDR_BIR_LTD0 | P3D_RG_CDR_BIR_LTD1);
+	tmp |= P3D_RG_CDR_BIR_LTD0_VAL(0xc) | P3D_RG_CDR_BIR_LTD1_VAL(0x3);
+	writel(tmp, port_base + U3P_PHYD_CDR1);
+
+	dev_dbg(u3phy->dev, "%s(%d)\n", __func__, instance->index);
+}
+
 static void phy_instance_init(struct mt65xx_u3phy *u3phy,
 	struct mt65xx_phy_instance *instance)
 {
@@ -275,26 +309,6 @@ static void phy_instance_init(struct mt65xx_u3phy *u3phy,
 	tmp |= PA6_RG_U2_SQTH_VAL(2);
 	writel(tmp, port_base + U3P_USBPHYACR6);
 
-	tmp = readl(port_base + U3P_U3PHYA_DA_REG0);
-	tmp &= ~P3A_RG_XTAL_EXT_EN_U3;
-	tmp |= P3A_RG_XTAL_EXT_EN_U3_VAL(2);
-	writel(tmp, port_base + U3P_U3PHYA_DA_REG0);
-
-	tmp = readl(port_base + U3P_U3_PHYA_REG9);
-	tmp &= ~P3A_RG_RX_DAC_MUX;
-	tmp |= P3A_RG_RX_DAC_MUX_VAL(4);
-	writel(tmp, port_base + U3P_U3_PHYA_REG9);
-
-	tmp = readl(port_base + U3P_U3_PHYA_REG6);
-	tmp &= ~P3A_RG_TX_EIDLE_CM;
-	tmp |= P3A_RG_TX_EIDLE_CM_VAL(0xe);
-	writel(tmp, port_base + U3P_U3_PHYA_REG6);
-
-	tmp = readl(port_base + U3P_PHYD_CDR1);
-	tmp &= ~(P3D_RG_CDR_BIR_LTD0 | P3D_RG_CDR_BIR_LTD1);
-	tmp |= P3D_RG_CDR_BIR_LTD0_VAL(0xc) | P3D_RG_CDR_BIR_LTD1_VAL(0x3);
-	writel(tmp, port_base + U3P_PHYD_CDR1);
-
 	dev_dbg(u3phy->dev, "%s(%d)\n", __func__, index);
 }
 
@@ -305,13 +319,6 @@ static void phy_instance_power_on(struct mt65xx_u3phy *u3phy,
 	u32 index = instance->index;
 	u32 tmp;
 
-	if (!index) {
-		/* Set RG_SSUSB_VUSB10_ON as 1 after VUSB10 ready */
-		tmp = readl(port_base + U3P_U3_PHYA_REG0);
-		tmp |= P3A_RG_U3_VUSB10_ON;
-		writel(tmp, port_base + U3P_U3_PHYA_REG0);
-	}
-
 	/* (force_suspendm=0) (let suspendm=1, enable usb 480MHz pll) */
 	tmp = readl(port_base + U3P_U2PHYDTM0);
 	tmp &= ~(P2C_FORCE_SUSPENDM | P2C_RG_XCVRSEL);
@@ -324,10 +331,6 @@ static void phy_instance_power_on(struct mt65xx_u3phy *u3phy,
 	writel(tmp, port_base + U3P_USBPHYACR6);
 
 	if (!index) {
-		tmp = readl(u3phy->sif_base + U3P_XTALCTL3);
-		tmp |= XC3_RG_U3_XTAL_RX_PWD | XC3_RG_U3_FRC_XTAL_RX_PWD;
-		writel(tmp, u3phy->sif_base + U3P_XTALCTL3);
-
 		/* switch 100uA current to SSUSB */
 		tmp = readl(port_base + U3P_USBPHYACR5);
 		tmp |= PA5_RG_U2_HS_100U_U3_EN;
@@ -339,12 +342,6 @@ static void phy_instance_power_on(struct mt65xx_u3phy *u3phy,
 	tmp &= ~P2C_RG_SESSEND;
 	writel(tmp, port_base + U3P_U2PHYDTM1);
 
-	/* USB 2.0 slew rate calibration */
-	tmp = readl(port_base + U3P_USBPHYACR5);
-	tmp &= ~PA5_RG_U2_HSTX_SRCTRL;
-	tmp |= PA5_RG_U2_HSTX_SRCTRL_VAL(4);
-	writel(tmp, port_base + U3P_USBPHYACR5);
-
 	if (u3phy->pdata->avoid_rx_sen_degradation && index) {
 		tmp = readl(port_base + U3D_U2PHYDCR0);
 		tmp |= P2C_RG_SIF_U2PLL_FORCE_ON;
@@ -392,12 +389,6 @@ static void phy_instance_power_off(struct mt65xx_u3phy *u3phy,
 	tmp |= P2C_RG_SESSEND;
 	writel(tmp, port_base + U3P_U2PHYDTM1);
 
-	if (!index) {
-		tmp = readl(port_base + U3P_U3_PHYA_REG0);
-		tmp &= ~P3A_RG_U3_VUSB10_ON;
-		writel(tmp, port_base + U3P_U3_PHYA_REG0);
-	}
-
 	if (u3phy->pdata->avoid_rx_sen_degradation && index) {
 		tmp = readl(port_base + U3D_U2PHYDCR0);
 		tmp &= ~P2C_RG_SIF_U2PLL_FORCE_ON;
@@ -437,7 +428,11 @@ static int mt65xx_phy_init(struct phy *phy)
 		return ret;
 	}
 
-	phy_instance_init(u3phy, instance);
+	if (instance->type == PHY_TYPE_USB2)
+		phy_instance_init(u3phy, instance);
+	else
+		u3_phy_instance_init(u3phy, instance);
+
 	return 0;
 }
 
@@ -446,8 +441,10 @@ static int mt65xx_phy_power_on(struct phy *phy)
 	struct mt65xx_phy_instance *instance = phy_get_drvdata(phy);
 	struct mt65xx_u3phy *u3phy = dev_get_drvdata(phy->dev.parent);
 
-	phy_instance_power_on(u3phy, instance);
-	hs_slew_rate_calibrate(u3phy, instance);
+	if (instance->type == PHY_TYPE_USB2) {
+		phy_instance_power_on(u3phy, instance);
+		hs_slew_rate_calibrate(u3phy, instance);
+	}
 	return 0;
 }
 
@@ -456,7 +453,9 @@ static int mt65xx_phy_power_off(struct phy *phy)
 	struct mt65xx_phy_instance *instance = phy_get_drvdata(phy);
 	struct mt65xx_u3phy *u3phy = dev_get_drvdata(phy->dev.parent);
 
-	phy_instance_power_off(u3phy, instance);
+	if (instance->type == PHY_TYPE_USB2)
+		phy_instance_power_off(u3phy, instance);
+
 	return 0;
 }
 
@@ -465,7 +464,9 @@ static int mt65xx_phy_exit(struct phy *phy)
 	struct mt65xx_phy_instance *instance = phy_get_drvdata(phy);
 	struct mt65xx_u3phy *u3phy = dev_get_drvdata(phy->dev.parent);
 
-	phy_instance_exit(u3phy, instance);
+	if (instance->type == PHY_TYPE_USB2)
+		phy_instance_exit(u3phy, instance);
+
 	clk_disable_unprepare(u3phy->u3phya_ref);
 	return 0;
 }
-- 
1.7.9.5

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#1563373 — [PATCH v2, 5/6] arm64: dts: mt8173: move clock from phy node into port nodes

FromChunfeng Yun <chunfeng.yun@mediatek.com>
Date2017-01-20 09:30 +0100
Subject[PATCH v2, 5/6] arm64: dts: mt8173: move clock from phy node into port nodes
Message-ID<t1CK6-4SH-19@gated-at.bofh.it>
In reply to#1563370
there is a reference clock for each port, HighSpeed port is 48M,
and SuperSpeed port is 26M which usually comes from 26M oscillator
directly, but some SoCs is not. it is flexible to move it into port
node.

Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8173.dtsi |    8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
index 1074ed2..2ee0863 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
@@ -755,8 +755,6 @@
 		u3phy: usb-phy@11290000 {
 			compatible = "mediatek,mt8173-u3phy";
 			reg = <0 0x11290000 0 0x800>;
-			clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>;
-			clock-names = "u3phya_ref";
 			#address-cells = <2>;
 			#size-cells = <2>;
 			ranges;
@@ -764,18 +762,24 @@
 
 			u2port0: port@11290800 {
 				reg = <0 0x11290800 0 0x100>;
+				clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>;
+				clock-names = "ref_clk";
 				#phy-cells = <1>;
 				status = "okay";
 			};
 
 			u3port0: port@11290900 {
 				reg = <0 0x11290900 0 0x700>;
+				clocks = <&clk26m>;
+				clock-names = "ref_clk";
 				#phy-cells = <1>;
 				status = "okay";
 			};
 
 			u2port1: port@11291000 {
 				reg = <0 0x11291000 0 0x100>;
+				clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>;
+				clock-names = "ref_clk";
 				#phy-cells = <1>;
 				status = "okay";
 			};
-- 
1.7.9.5

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#1563374 — [PATCH v2, 6/6] dt-bindings: phy-mt65xx-usb: add support for new version phy

FromChunfeng Yun <chunfeng.yun@mediatek.com>
Date2017-01-20 09:30 +0100
Subject[PATCH v2, 6/6] dt-bindings: phy-mt65xx-usb: add support for new version phy
Message-ID<t1CK7-4SH-21@gated-at.bofh.it>
In reply to#1563370
add a new compatible string for "mt2712", and move reference clock
into each port node;

Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
 .../devicetree/bindings/phy/phy-mt65xx-usb.txt     |   91 +++++++++++++++++---
 1 file changed, 77 insertions(+), 14 deletions(-)

diff --git a/Documentation/devicetree/bindings/phy/phy-mt65xx-usb.txt b/Documentation/devicetree/bindings/phy/phy-mt65xx-usb.txt
index 33a2b1e..1d06604 100644
--- a/Documentation/devicetree/bindings/phy/phy-mt65xx-usb.txt
+++ b/Documentation/devicetree/bindings/phy/phy-mt65xx-usb.txt
@@ -6,21 +6,27 @@ This binding describes a usb3.0 phy for mt65xx platforms of Medaitek SoC.
 Required properties (controller (parent) node):
  - compatible	: should be one of
 		  "mediatek,mt2701-u3phy"
+		  "mediatek,mt2712-u3phy"
 		  "mediatek,mt8173-u3phy"
- - reg		: offset and length of register for phy, exclude port's
-		  register.
- - clocks	: a list of phandle + clock-specifier pairs, one for each
-		  entry in clock-names
- - clock-names	: must contain
-		  "u3phya_ref": for reference clock of usb3.0 analog phy.
 
 Required nodes	: a sub-node is required for each port the controller
 		  provides. Address range information including the usual
 		  'reg' property is used inside these nodes to describe
 		  the controller's topology.
 
+Optional properties (controller (parent) node):
+ - reg		: offset and length of register shared by multiple ports,
+		  exclude port's private register. It is needed on mt2701
+		  and mt8173, but not on mt2712.
+
 Required properties (port (child) node):
 - reg		: address and length of the register set for the port.
+- clocks	: a list of phandle + clock-specifier pairs, one for each
+		  entry in clock-names
+- clock-names	: must contain
+		  "ref_clk": 48M reference clock for HighSpeed analog phy; and
+			26M reference clock for SuperSpeed analog phy, sometimes is
+			24M, 25M or 27M, depended on platform.
 - #phy-cells	: should be 1 (See second example)
 		  cell after port phandle is phy type from:
 			- PHY_TYPE_USB2
@@ -31,21 +37,31 @@ Example:
 u3phy: usb-phy@11290000 {
 	compatible = "mediatek,mt8173-u3phy";
 	reg = <0 0x11290000 0 0x800>;
-	clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>;
-	clock-names = "u3phya_ref";
 	#address-cells = <2>;
 	#size-cells = <2>;
 	ranges;
 	status = "okay";
 
-	phy_port0: port@11290800 {
-		reg = <0 0x11290800 0 0x800>;
+	u2port0: port@11290800 {
+		reg = <0 0x11290800 0 0x100>;
+		clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>;
+		clock-names = "ref_clk";
 		#phy-cells = <1>;
 		status = "okay";
 	};
 
-	phy_port1: port@11291000 {
-		reg = <0 0x11291000 0 0x800>;
+	u3port0: port@11290900 {
+		reg = <0 0x11290800 0 0x700>;
+		clocks = <&clk26m>;
+		clock-names = "ref_clk";
+		#phy-cells = <1>;
+		status = "okay";
+	};
+
+	u2port1: port@11291000 {
+		reg = <0 0x11291000 0 0x100>;
+		clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>;
+		clock-names = "ref_clk";
 		#phy-cells = <1>;
 		status = "okay";
 	};
@@ -64,7 +80,54 @@ Example:
 
 usb30: usb@11270000 {
 	...
-	phys = <&phy_port0 PHY_TYPE_USB3>;
-	phy-names = "usb3-0";
+	phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>;
+	phy-names = "usb2-0", "usb3-0";
 	...
 };
+
+
+Layout differences of banks between mt8173/mt2701 and mt2712
+-------------------------------------------------------------
+mt8173 and mt2701:
+port        offset    bank
+shared      0x0000    SPLLC
+            0x0100    FMREG
+u2 port0    0x0800    U2PHY_COM
+u3 port0    0x0900    U3PHYD
+            0x0a00    U3PHYD_BANK2
+            0x0b00    U3PHYA
+            0x0c00    U3PHYA_DA
+u2 port1    0x1000    U2PHY_COM
+u3 port1    0x1100    U3PHYD
+            0x1200    U3PHYD_BANK2
+            0x1300    U3PHYA
+            0x1400    U3PHYA_DA
+u2 port2    0x1800    U2PHY_COM
+            ...
+
+mt2712:
+port        offset    bank
+u2 port0    0x0000    MISC
+            0x0100    FMREG
+            0x0300    U2PHY_COM
+u3 port0    0x0700    SPLLC
+            0x0800    CHIP
+            0x0900    U3PHYD
+            0x0a00    U3PHYD_BANK2
+            0x0b00    U3PHYA
+            0x0c00    U3PHYA_DA
+u2 port1    0x1000    MISC
+            0x1100    FMREG
+            0x1300    U2PHY_COM
+u3 port1    0x1700    SPLLC
+            0x1800    CHIP
+            0x1900    U3PHYD
+            0x1a00    U3PHYD_BANK2
+            0x1b00    U3PHYA
+            0x1c00    U3PHYA_DA
+u2 port2    0x2000    MISC
+            ...
+
+    SPLLC shared by u3 ports and FMREG shared by u2 ports on
+mt8173/mt2701 are put back into each port; a new bank MISC for
+u2 ports and CHIP for u3 ports are added on mt2712.
-- 
1.7.9.5

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#1565942 — Re: [PATCH v2, 6/6] dt-bindings: phy-mt65xx-usb: add support for new version phy

FromMatthias Brugger <matthias.bgg@gmail.com>
Date2017-01-24 16:30 +0100
SubjectRe: [PATCH v2, 6/6] dt-bindings: phy-mt65xx-usb: add support for new version phy
Message-ID<t3bcK-5Zl-25@gated-at.bofh.it>
In reply to#1563374
Hi Chunfeng,

On 01/20/2017 09:18 AM, Chunfeng Yun wrote:
> add a new compatible string for "mt2712", and move reference clock
> into each port node;
>
> Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
> ---
>  .../devicetree/bindings/phy/phy-mt65xx-usb.txt     |   91 +++++++++++++++++---
>  1 file changed, 77 insertions(+), 14 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/phy/phy-mt65xx-usb.txt b/Documentation/devicetree/bindings/phy/phy-mt65xx-usb.txt
> index 33a2b1e..1d06604 100644
> --- a/Documentation/devicetree/bindings/phy/phy-mt65xx-usb.txt
> +++ b/Documentation/devicetree/bindings/phy/phy-mt65xx-usb.txt
> @@ -6,21 +6,27 @@ This binding describes a usb3.0 phy for mt65xx platforms of Medaitek SoC.
>  Required properties (controller (parent) node):
>   - compatible	: should be one of
>  		  "mediatek,mt2701-u3phy"
> +		  "mediatek,mt2712-u3phy"
>  		  "mediatek,mt8173-u3phy"
> - - reg		: offset and length of register for phy, exclude port's
> -		  register.
> - - clocks	: a list of phandle + clock-specifier pairs, one for each
> -		  entry in clock-names
> - - clock-names	: must contain
> -		  "u3phya_ref": for reference clock of usb3.0 analog phy.
>
>  Required nodes	: a sub-node is required for each port the controller
>  		  provides. Address range information including the usual
>  		  'reg' property is used inside these nodes to describe
>  		  the controller's topology.
>
> +Optional properties (controller (parent) node):
> + - reg		: offset and length of register shared by multiple ports,
> +		  exclude port's private register. It is needed on mt2701
> +		  and mt8173, but not on mt2712.
> +
>  Required properties (port (child) node):
>  - reg		: address and length of the register set for the port.
> +- clocks	: a list of phandle + clock-specifier pairs, one for each
> +		  entry in clock-names
> +- clock-names	: must contain
> +		  "ref_clk": 48M reference clock for HighSpeed analog phy; and
> +			26M reference clock for SuperSpeed analog phy, sometimes is
> +			24M, 25M or 27M, depended on platform.
>  - #phy-cells	: should be 1 (See second example)
>  		  cell after port phandle is phy type from:
>  			- PHY_TYPE_USB2

The old bindings will need to be supported by the driver, they have to 
stay here with a comment that they are deprecated.

Regards,
Matthias

> @@ -31,21 +37,31 @@ Example:
>  u3phy: usb-phy@11290000 {
>  	compatible = "mediatek,mt8173-u3phy";
>  	reg = <0 0x11290000 0 0x800>;
> -	clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>;
> -	clock-names = "u3phya_ref";
>  	#address-cells = <2>;
>  	#size-cells = <2>;
>  	ranges;
>  	status = "okay";
>
> -	phy_port0: port@11290800 {
> -		reg = <0 0x11290800 0 0x800>;
> +	u2port0: port@11290800 {
> +		reg = <0 0x11290800 0 0x100>;
> +		clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>;
> +		clock-names = "ref_clk";
>  		#phy-cells = <1>;
>  		status = "okay";
>  	};
>
> -	phy_port1: port@11291000 {
> -		reg = <0 0x11291000 0 0x800>;
> +	u3port0: port@11290900 {
> +		reg = <0 0x11290800 0 0x700>;
> +		clocks = <&clk26m>;
> +		clock-names = "ref_clk";
> +		#phy-cells = <1>;
> +		status = "okay";
> +	};
> +
> +	u2port1: port@11291000 {
> +		reg = <0 0x11291000 0 0x100>;
> +		clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>;
> +		clock-names = "ref_clk";
>  		#phy-cells = <1>;
>  		status = "okay";
>  	};
> @@ -64,7 +80,54 @@ Example:
>
>  usb30: usb@11270000 {
>  	...
> -	phys = <&phy_port0 PHY_TYPE_USB3>;
> -	phy-names = "usb3-0";
> +	phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>;
> +	phy-names = "usb2-0", "usb3-0";
>  	...
>  };
> +
> +
> +Layout differences of banks between mt8173/mt2701 and mt2712
> +-------------------------------------------------------------
> +mt8173 and mt2701:
> +port        offset    bank
> +shared      0x0000    SPLLC
> +            0x0100    FMREG
> +u2 port0    0x0800    U2PHY_COM
> +u3 port0    0x0900    U3PHYD
> +            0x0a00    U3PHYD_BANK2
> +            0x0b00    U3PHYA
> +            0x0c00    U3PHYA_DA
> +u2 port1    0x1000    U2PHY_COM
> +u3 port1    0x1100    U3PHYD
> +            0x1200    U3PHYD_BANK2
> +            0x1300    U3PHYA
> +            0x1400    U3PHYA_DA
> +u2 port2    0x1800    U2PHY_COM
> +            ...
> +
> +mt2712:
> +port        offset    bank
> +u2 port0    0x0000    MISC
> +            0x0100    FMREG
> +            0x0300    U2PHY_COM
> +u3 port0    0x0700    SPLLC
> +            0x0800    CHIP
> +            0x0900    U3PHYD
> +            0x0a00    U3PHYD_BANK2
> +            0x0b00    U3PHYA
> +            0x0c00    U3PHYA_DA
> +u2 port1    0x1000    MISC
> +            0x1100    FMREG
> +            0x1300    U2PHY_COM
> +u3 port1    0x1700    SPLLC
> +            0x1800    CHIP
> +            0x1900    U3PHYD
> +            0x1a00    U3PHYD_BANK2
> +            0x1b00    U3PHYA
> +            0x1c00    U3PHYA_DA
> +u2 port2    0x2000    MISC
> +            ...
> +
> +    SPLLC shared by u3 ports and FMREG shared by u2 ports on
> +mt8173/mt2701 are put back into each port; a new bank MISC for
> +u2 ports and CHIP for u3 ports are added on mt2712.
>

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#1568654 — Re: [PATCH v2, 6/6] dt-bindings: phy-mt65xx-usb: add support for new version phy

FromRob Herring <robh@kernel.org>
Date2017-01-27 21:10 +0100
SubjectRe: [PATCH v2, 6/6] dt-bindings: phy-mt65xx-usb: add support for new version phy
Message-ID<t4l0l-ds-13@gated-at.bofh.it>
In reply to#1563374
On Fri, Jan 20, 2017 at 04:18:41PM +0800, Chunfeng Yun wrote:
> add a new compatible string for "mt2712", and move reference clock
> into each port node;
> 
> Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
> ---
>  .../devicetree/bindings/phy/phy-mt65xx-usb.txt     |   91 +++++++++++++++++---
>  1 file changed, 77 insertions(+), 14 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/phy/phy-mt65xx-usb.txt b/Documentation/devicetree/bindings/phy/phy-mt65xx-usb.txt
> index 33a2b1e..1d06604 100644
> --- a/Documentation/devicetree/bindings/phy/phy-mt65xx-usb.txt
> +++ b/Documentation/devicetree/bindings/phy/phy-mt65xx-usb.txt
> @@ -6,21 +6,27 @@ This binding describes a usb3.0 phy for mt65xx platforms of Medaitek SoC.
>  Required properties (controller (parent) node):
>   - compatible	: should be one of
>  		  "mediatek,mt2701-u3phy"
> +		  "mediatek,mt2712-u3phy"
>  		  "mediatek,mt8173-u3phy"
> - - reg		: offset and length of register for phy, exclude port's
> -		  register.
> - - clocks	: a list of phandle + clock-specifier pairs, one for each
> -		  entry in clock-names
> - - clock-names	: must contain
> -		  "u3phya_ref": for reference clock of usb3.0 analog phy.
>  
>  Required nodes	: a sub-node is required for each port the controller
>  		  provides. Address range information including the usual
>  		  'reg' property is used inside these nodes to describe
>  		  the controller's topology.
>  
> +Optional properties (controller (parent) node):
> + - reg		: offset and length of register shared by multiple ports,

How is this optional?

> +		  exclude port's private register. It is needed on mt2701
> +		  and mt8173, but not on mt2712.
> +
>  Required properties (port (child) node):
>  - reg		: address and length of the register set for the port.
> +- clocks	: a list of phandle + clock-specifier pairs, one for each
> +		  entry in clock-names
> +- clock-names	: must contain
> +		  "ref_clk": 48M reference clock for HighSpeed analog phy; and

_clk is redundant. Just "ref"

> +			26M reference clock for SuperSpeed analog phy, sometimes is
> +			24M, 25M or 27M, depended on platform.
>  - #phy-cells	: should be 1 (See second example)
>  		  cell after port phandle is phy type from:
>  			- PHY_TYPE_USB2
> @@ -31,21 +37,31 @@ Example:
>  u3phy: usb-phy@11290000 {
>  	compatible = "mediatek,mt8173-u3phy";
>  	reg = <0 0x11290000 0 0x800>;
> -	clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>;
> -	clock-names = "u3phya_ref";
>  	#address-cells = <2>;
>  	#size-cells = <2>;
>  	ranges;
>  	status = "okay";
>  
> -	phy_port0: port@11290800 {
> -		reg = <0 0x11290800 0 0x800>;
> +	u2port0: port@11290800 {
> +		reg = <0 0x11290800 0 0x100>;
> +		clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>;
> +		clock-names = "ref_clk";
>  		#phy-cells = <1>;
>  		status = "okay";
>  	};
>  
> -	phy_port1: port@11291000 {
> -		reg = <0 0x11291000 0 0x800>;
> +	u3port0: port@11290900 {
> +		reg = <0 0x11290800 0 0x700>;
> +		clocks = <&clk26m>;
> +		clock-names = "ref_clk";
> +		#phy-cells = <1>;
> +		status = "okay";
> +	};
> +
> +	u2port1: port@11291000 {
> +		reg = <0 0x11291000 0 0x100>;
> +		clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>;
> +		clock-names = "ref_clk";
>  		#phy-cells = <1>;
>  		status = "okay";
>  	};
> @@ -64,7 +80,54 @@ Example:
>  
>  usb30: usb@11270000 {
>  	...
> -	phys = <&phy_port0 PHY_TYPE_USB3>;
> -	phy-names = "usb3-0";
> +	phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>;
> +	phy-names = "usb2-0", "usb3-0";
>  	...
>  };
> +
> +
> +Layout differences of banks between mt8173/mt2701 and mt2712
> +-------------------------------------------------------------
> +mt8173 and mt2701:
> +port        offset    bank
> +shared      0x0000    SPLLC
> +            0x0100    FMREG
> +u2 port0    0x0800    U2PHY_COM
> +u3 port0    0x0900    U3PHYD
> +            0x0a00    U3PHYD_BANK2
> +            0x0b00    U3PHYA
> +            0x0c00    U3PHYA_DA
> +u2 port1    0x1000    U2PHY_COM
> +u3 port1    0x1100    U3PHYD
> +            0x1200    U3PHYD_BANK2
> +            0x1300    U3PHYA
> +            0x1400    U3PHYA_DA
> +u2 port2    0x1800    U2PHY_COM
> +            ...
> +
> +mt2712:
> +port        offset    bank
> +u2 port0    0x0000    MISC
> +            0x0100    FMREG
> +            0x0300    U2PHY_COM
> +u3 port0    0x0700    SPLLC
> +            0x0800    CHIP
> +            0x0900    U3PHYD
> +            0x0a00    U3PHYD_BANK2
> +            0x0b00    U3PHYA
> +            0x0c00    U3PHYA_DA
> +u2 port1    0x1000    MISC
> +            0x1100    FMREG
> +            0x1300    U2PHY_COM
> +u3 port1    0x1700    SPLLC
> +            0x1800    CHIP
> +            0x1900    U3PHYD
> +            0x1a00    U3PHYD_BANK2
> +            0x1b00    U3PHYA
> +            0x1c00    U3PHYA_DA
> +u2 port2    0x2000    MISC
> +            ...
> +
> +    SPLLC shared by u3 ports and FMREG shared by u2 ports on
> +mt8173/mt2701 are put back into each port; a new bank MISC for
> +u2 ports and CHIP for u3 ports are added on mt2712.
> -- 
> 1.7.9.5
>

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