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Groups > linux.kernel > #1563373
| From | Chunfeng Yun <chunfeng.yun@mediatek.com> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | [PATCH v2, 5/6] arm64: dts: mt8173: move clock from phy node into port nodes |
| Date | 2017-01-20 09:30 +0100 |
| Message-ID | <t1CK6-4SH-19@gated-at.bofh.it> (permalink) |
| References | <t1CK6-4SH-3@gated-at.bofh.it> |
| Organization | linux.* mail to news gateway |
there is a reference clock for each port, HighSpeed port is 48M,
and SuperSpeed port is 26M which usually comes from 26M oscillator
directly, but some SoCs is not. it is flexible to move it into port
node.
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8173.dtsi | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
index 1074ed2..2ee0863 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
@@ -755,8 +755,6 @@
u3phy: usb-phy@11290000 {
compatible = "mediatek,mt8173-u3phy";
reg = <0 0x11290000 0 0x800>;
- clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>;
- clock-names = "u3phya_ref";
#address-cells = <2>;
#size-cells = <2>;
ranges;
@@ -764,18 +762,24 @@
u2port0: port@11290800 {
reg = <0 0x11290800 0 0x100>;
+ clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>;
+ clock-names = "ref_clk";
#phy-cells = <1>;
status = "okay";
};
u3port0: port@11290900 {
reg = <0 0x11290900 0 0x700>;
+ clocks = <&clk26m>;
+ clock-names = "ref_clk";
#phy-cells = <1>;
status = "okay";
};
u2port1: port@11291000 {
reg = <0 0x11291000 0 0x100>;
+ clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>;
+ clock-names = "ref_clk";
#phy-cells = <1>;
status = "okay";
};
--
1.7.9.5
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[PATCH v2, 1/6] phy: phy-mt65xx-usb3: split SuperSpeed port into two ones Chunfeng Yun <chunfeng.yun@mediatek.com> - 2017-01-20 09:30 +0100
[PATCH v2, 5/6] arm64: dts: mt8173: move clock from phy node into port nodes Chunfeng Yun <chunfeng.yun@mediatek.com> - 2017-01-20 09:30 +0100
[PATCH v2, 6/6] dt-bindings: phy-mt65xx-usb: add support for new version phy Chunfeng Yun <chunfeng.yun@mediatek.com> - 2017-01-20 09:30 +0100
Re: [PATCH v2, 6/6] dt-bindings: phy-mt65xx-usb: add support for new version phy Matthias Brugger <matthias.bgg@gmail.com> - 2017-01-24 16:30 +0100
Re: [PATCH v2, 6/6] dt-bindings: phy-mt65xx-usb: add support for new version phy Rob Herring <robh@kernel.org> - 2017-01-27 21:10 +0100
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