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[PATCH V3 1/6] clk: tegra: add TEGRA20_CLK_NOR to init table

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  [PATCH V3 1/6] clk: tegra: add TEGRA20_CLK_NOR to init table Mirza Krak <mirza.krak@gmail.com> - 2016-10-27 16:10 +0200
    Re: [PATCH V3 1/6] clk: tegra: add TEGRA20_CLK_NOR to init table Jon Hunter <jonathanh@nvidia.com> - 2016-11-03 11:10 +0100
      Re: [PATCH V3 1/6] clk: tegra: add TEGRA20_CLK_NOR to init table Mirza Krak <mirza.krak@gmail.com> - 2016-11-03 13:30 +0100
        Re: [PATCH V3 1/6] clk: tegra: add TEGRA20_CLK_NOR to init table Mirza Krak <mirza.krak@gmail.com> - 2016-11-03 13:40 +0100
          Re: [PATCH V3 1/6] clk: tegra: add TEGRA20_CLK_NOR to init table Jon Hunter <jonathanh@nvidia.com> - 2016-11-03 14:50 +0100
    Re: [PATCH V3 1/6] clk: tegra: add TEGRA20_CLK_NOR to init table Jon Hunter <jonathanh@nvidia.com> - 2016-11-03 14:50 +0100

#1510228 — [PATCH V3 1/6] clk: tegra: add TEGRA20_CLK_NOR to init table

From: Mirza Krak <mirza.krak@gmail.com>

Add TEGRA20_CLK_NOR to init table and set default rate to 92 MHz which
is max rate.

The maximum rate value of 92 MHz is pulled from the downstream L4T
kernel.

Signed-off-by: Mirza Krak <mirza.krak@gmail.com>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-on: Colibri T20/T30 on EvalBoard V3.x and GMI-Memory Board
---

Changes in v2:
- no changes

Changes in v3:
- Added comment in commit message where I got the maximum rates from.

 drivers/clk/tegra/clk-tegra20.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
index 837e5cb..13d3b5a 100644
--- a/drivers/clk/tegra/clk-tegra20.c
+++ b/drivers/clk/tegra/clk-tegra20.c
@@ -1047,6 +1047,7 @@ static struct tegra_clk_init_table init_table[] __initdata = {
 	{ TEGRA20_CLK_SDMMC3, TEGRA20_CLK_PLL_P, 48000000, 0 },
 	{ TEGRA20_CLK_SDMMC4, TEGRA20_CLK_PLL_P, 48000000, 0 },
 	{ TEGRA20_CLK_SPI, TEGRA20_CLK_PLL_P, 20000000, 0 },
+	{ TEGRA20_CLK_NOR, TEGRA20_CLK_PLL_P, 92000000, 0 },
 	{ TEGRA20_CLK_SBC1, TEGRA20_CLK_PLL_P, 100000000, 0 },
 	{ TEGRA20_CLK_SBC2, TEGRA20_CLK_PLL_P, 100000000, 0 },
 	{ TEGRA20_CLK_SBC3, TEGRA20_CLK_PLL_P, 100000000, 0 },
--
2.1.4

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#1514425

Hi Mirza,

On 27/10/16 15:01, Mirza Krak wrote:
> From: Mirza Krak <mirza.krak@gmail.com>
>
> Add TEGRA20_CLK_NOR to init table and set default rate to 92 MHz which
> is max rate.
>
> The maximum rate value of 92 MHz is pulled from the downstream L4T
> kernel.

Thanks for adding this. I assume that this is from an L4T r16 release 
with a v3.1 kernel. I had a quick poke through the kernel sources for 
v3.1 but was unable to see where this is set. Obviously v3.1 did not 
have CCF and so everything seems to be in the arch/arm/mach-tegra 
directory for setting up clocks. Can you point me to the appropriate 
sources so I can ACK this?

Cheers
Jon

-- 
nvpublic

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#1514483

2016-11-03 11:06 GMT+01:00 Jon Hunter <jonathanh@nvidia.com>:
> Hi Mirza,
>
> On 27/10/16 15:01, Mirza Krak wrote:
>>
>> From: Mirza Krak <mirza.krak@gmail.com>
>>
>> Add TEGRA20_CLK_NOR to init table and set default rate to 92 MHz which
>> is max rate.
>>
>> The maximum rate value of 92 MHz is pulled from the downstream L4T
>> kernel.
>
>
> Thanks for adding this. I assume that this is from an L4T r16 release with a
> v3.1 kernel. I had a quick poke through the kernel sources for v3.1 but was
> unable to see where this is set. Obviously v3.1 did not have CCF and so
> everything seems to be in the arch/arm/mach-tegra directory for setting up
> clocks. Can you point me to the appropriate sources so I can ACK this?

I use the kernel sources provided by Toradex, and these sources are
based on L4T r16 release.

http://git.toradex.com/cgit/linux-toradex.git/tree/arch/arm/mach-tegra/tegra2_clocks.c?h=tegra#n2463



Best Regards
Mirza Krak

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#1514489

2016-11-03 13:26 GMT+01:00 Mirza Krak <mirza.krak@gmail.com>:
> 2016-11-03 11:06 GMT+01:00 Jon Hunter <jonathanh@nvidia.com>:
>> Hi Mirza,
>>
>> On 27/10/16 15:01, Mirza Krak wrote:
>>>
>>> From: Mirza Krak <mirza.krak@gmail.com>
>>>
>>> Add TEGRA20_CLK_NOR to init table and set default rate to 92 MHz which
>>> is max rate.
>>>
>>> The maximum rate value of 92 MHz is pulled from the downstream L4T
>>> kernel.
>>
>>
>> Thanks for adding this. I assume that this is from an L4T r16 release with a
>> v3.1 kernel. I had a quick poke through the kernel sources for v3.1 but was
>> unable to see where this is set. Obviously v3.1 did not have CCF and so
>> everything seems to be in the arch/arm/mach-tegra directory for setting up
>> clocks. Can you point me to the appropriate sources so I can ACK this?
>
> I use the kernel sources provided by Toradex, and these sources are
> based on L4T r16 release.
>
> http://git.toradex.com/cgit/linux-toradex.git/tree/arch/arm/mach-tegra/tegra2_clocks.c?h=tegra#n2463

Ops, pre-mature send.

I also added Marcel from Toradex on CC.

The link to the source are [1] for Tegra2 and  [2] for Tegra3.

[1]. http://git.toradex.com/cgit/linux-toradex.git/tree/arch/arm/mach-tegra/tegra2_clocks.c?h=tegra#n2463
[2]. http://git.toradex.com/cgit/linux-toradex.git/tree/arch/arm/mach-tegra/tegra3_clocks.c?h=tegra#n4353

Best Regards
Mirza

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#1514533

On 03/11/16 12:30, Mirza Krak wrote:
> 2016-11-03 13:26 GMT+01:00 Mirza Krak <mirza.krak@gmail.com>:
>> 2016-11-03 11:06 GMT+01:00 Jon Hunter <jonathanh@nvidia.com>:
>>> Hi Mirza,
>>>
>>> On 27/10/16 15:01, Mirza Krak wrote:
>>>>
>>>> From: Mirza Krak <mirza.krak@gmail.com>
>>>>
>>>> Add TEGRA20_CLK_NOR to init table and set default rate to 92 MHz which
>>>> is max rate.
>>>>
>>>> The maximum rate value of 92 MHz is pulled from the downstream L4T
>>>> kernel.
>>>
>>>
>>> Thanks for adding this. I assume that this is from an L4T r16 release with a
>>> v3.1 kernel. I had a quick poke through the kernel sources for v3.1 but was
>>> unable to see where this is set. Obviously v3.1 did not have CCF and so
>>> everything seems to be in the arch/arm/mach-tegra directory for setting up
>>> clocks. Can you point me to the appropriate sources so I can ACK this?
>>
>> I use the kernel sources provided by Toradex, and these sources are
>> based on L4T r16 release.
>>
>> http://git.toradex.com/cgit/linux-toradex.git/tree/arch/arm/mach-tegra/tegra2_clocks.c?h=tegra#n2463
>
> Ops, pre-mature send.
>
> I also added Marcel from Toradex on CC.
>
> The link to the source are [1] for Tegra2 and  [2] for Tegra3.
>
> [1]. http://git.toradex.com/cgit/linux-toradex.git/tree/arch/arm/mach-tegra/tegra2_clocks.c?h=tegra#n2463
> [2]. http://git.toradex.com/cgit/linux-toradex.git/tree/arch/arm/mach-tegra/tegra3_clocks.c?h=tegra#n4353

Great. Yes I see the same. Thanks!

Jon

-- 
nvpublic

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#1514532

On 27/10/16 15:01, Mirza Krak wrote:
> From: Mirza Krak <mirza.krak@gmail.com>
>
> Add TEGRA20_CLK_NOR to init table and set default rate to 92 MHz which
> is max rate.
>
> The maximum rate value of 92 MHz is pulled from the downstream L4T
> kernel.
>
> Signed-off-by: Mirza Krak <mirza.krak@gmail.com>
> Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> Tested-on: Colibri T20/T30 on EvalBoard V3.x and GMI-Memory Board

Acked-by: Jon Hunter <jonathanh@nvidia.com>

Cheers
Jon

-- 
nvpublic

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