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[PATCH 0/5] KVM: x86: cleanup and minimal speedup for APICv

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  [PATCH 0/5] KVM: x86: cleanup and minimal speedup for APICv Paolo Bonzini <pbonzini@redhat.com> - 2016-10-14 20:30 +0200
    [PATCH 3/5] KVM: x86: do not use KVM_REQ_EVENT for APICv interrupt injection Paolo Bonzini <pbonzini@redhat.com> - 2016-10-14 20:30 +0200
      Re: [PATCH 3/5] KVM: x86: do not use KVM_REQ_EVENT for APICv  interrupt injection Radim Krčmář <rkrcmar@redhat.com> - 2016-10-26 22:10 +0200
    [PATCH 2/5] KVM: x86: do not scan IRR twice on APICv vmentry Paolo Bonzini <pbonzini@redhat.com> - 2016-10-14 20:30 +0200
      Re: [PATCH 2/5] KVM: x86: do not scan IRR twice on APICv vmentry Wanpeng Li <kernellwp@gmail.com> - 2016-10-18 08:10 +0200
      Re: [PATCH 2/5] KVM: x86: do not scan IRR twice on APICv vmentry Radim Krčmář <rkrcmar@redhat.com> - 2016-10-26 22:00 +0200
        Re: [PATCH 2/5] KVM: x86: do not scan IRR twice on APICv vmentry Paolo Bonzini <pbonzini@redhat.com> - 2016-11-03 14:40 +0100
          Re: [PATCH 2/5] KVM: x86: do not scan IRR twice on APICv vmentry "Michael S. Tsirkin" <mst@redhat.com> - 2016-11-03 15:00 +0100
            Re: [PATCH 2/5] KVM: x86: do not scan IRR twice on APICv vmentry Paolo Bonzini <pbonzini@redhat.com> - 2016-11-03 17:10 +0100
          Re: [PATCH 2/5] KVM: x86: do not scan IRR twice on APICv vmentry Radim Krčmář <rkrcmar@redhat.com> - 2016-11-03 16:10 +0100
            Re: [PATCH 2/5] KVM: x86: do not scan IRR twice on APICv vmentry Paolo Bonzini <pbonzini@redhat.com> - 2016-11-03 17:10 +0100
              Re: [PATCH 2/5] KVM: x86: do not scan IRR twice on APICv vmentry Radim Krčmář <rkrcmar@redhat.com> - 2016-11-03 19:10 +0100
                Re: [PATCH 2/5] KVM: x86: do not scan IRR twice on APICv vmentry Paolo Bonzini <pbonzini@redhat.com> - 2016-11-03 19:20 +0100
                  Re: [PATCH 2/5] KVM: x86: do not scan IRR twice on APICv vmentry Radim Krčmář <rkrcmar@redhat.com> - 2016-11-03 19:30 +0100
                    Re: [PATCH 2/5] KVM: x86: do not scan IRR twice on APICv vmentry Radim Krčmář <rkrcmar@redhat.com> - 2016-11-03 21:20 +0100
                      Re: [PATCH 2/5] KVM: x86: do not scan IRR twice on APICv vmentry Paolo Bonzini <pbonzini@redhat.com> - 2016-11-04 10:40 +0100
    [PATCH 1/5] KVM: x86: avoid atomic operations on APICv vmentry Paolo Bonzini <pbonzini@redhat.com> - 2016-10-14 20:30 +0200
      Re: [PATCH 1/5] KVM: x86: avoid atomic operations on APICv vmentry Paolo Bonzini <pbonzini@redhat.com> - 2016-10-14 21:00 +0200
        Re: [PATCH 1/5] KVM: x86: avoid atomic operations on APICv vmentry Nadav Amit <nadav.amit@gmail.com> - 2016-10-14 21:50 +0200
          Re: [PATCH 1/5] KVM: x86: avoid atomic operations on APICv vmentry Paolo Bonzini <pbonzini@redhat.com> - 2016-10-15 09:50 +0200
            Re: [PATCH 1/5] KVM: x86: avoid atomic operations on APICv vmentry "Michael S. Tsirkin" <mst@redhat.com> - 2016-10-16 04:40 +0200
              Re: [PATCH 1/5] KVM: x86: avoid atomic operations on APICv vmentry "Paul E. McKenney" <paulmck@linux.vnet.ibm.com> - 2016-10-19 20:00 +0200
                Re: [PATCH 1/5] KVM: x86: avoid atomic operations on APICv vmentry "Michael S. Tsirkin" <mst@redhat.com> - 2016-10-27 00:00 +0200
      Re: [PATCH 1/5] KVM: x86: avoid atomic operations on APICv vmentry Nadav Amit <nadav.amit@gmail.com> - 2016-10-14 21:00 +0200
      Re: [PATCH 1/5] KVM: x86: avoid atomic operations on APICv vmentry "Michael S. Tsirkin" <mst@redhat.com> - 2016-10-16 05:30 +0200
        Re: [PATCH 1/5] KVM: x86: avoid atomic operations on APICv vmentry Paolo Bonzini <pbonzini@redhat.com> - 2016-10-17 13:10 +0200
      Re: [PATCH 1/5] KVM: x86: avoid atomic operations on APICv vmentry Radim Krčmář <rkrcmar@redhat.com> - 2016-10-26 22:00 +0200
        Re: [PATCH 1/5] KVM: x86: avoid atomic operations on APICv vmentry "Michael S. Tsirkin" <mst@redhat.com> - 2016-10-26 23:50 +0200
          Re: [PATCH 1/5] KVM: x86: avoid atomic operations on APICv vmentry Radim Krčmář <rkrcmar@redhat.com> - 2016-10-27 18:50 +0200
            Re: [PATCH 1/5] KVM: x86: avoid atomic operations on APICv vmentry "Michael S. Tsirkin" <mst@redhat.com> - 2016-10-27 19:00 +0200
              Re: [PATCH 1/5] KVM: x86: avoid atomic operations on APICv vmentry Radim Krčmář <rkrcmar@redhat.com> - 2016-10-27 19:10 +0200
                Re: [PATCH 1/5] KVM: x86: avoid atomic operations on APICv vmentry Paolo Bonzini <pbonzini@redhat.com> - 2016-10-28 11:40 +0200
                  Re: [PATCH 1/5] KVM: x86: avoid atomic operations on APICv vmentry "Michael S. Tsirkin" <mst@redhat.com> - 2016-10-29 00:10 +0200
    [PATCH 5/5] KVM: vmx: clear pending interrupts on KVM_SET_LAPIC Paolo Bonzini <pbonzini@redhat.com> - 2016-10-14 20:30 +0200
      Re: [PATCH 5/5] KVM: vmx: clear pending interrupts on KVM_SET_LAPIC Radim Krčmář <rkrcmar@redhat.com> - 2016-10-26 22:10 +0200
    Re: [PATCH 0/5] KVM: x86: cleanup and minimal speedup for APICv "Michael S. Tsirkin" <mst@redhat.com> - 2016-10-27 00:00 +0200

Page 2 of 2 — ← Prev page 1 [2]

#1501389 — Re: [PATCH 1/5] KVM: x86: avoid atomic operations on APICv vmentry

On Sat, Oct 15, 2016 at 03:47:45AM -0400, Paolo Bonzini wrote:
> 
> > > On Oct 14, 2016, at 11:56 AM, Paolo Bonzini <pbonzini@redhat.com> wrote:
> > >>> 
> > >>> 	for (i = 0; i <= 7; i++) {
> > >>> -		pir_val = xchg(&pir[i], 0);
> > >>> -		if (pir_val)
> > >>> +		pir_val = READ_ONCE(pir[i]);
> > >> 
> > >> Out of curiosity, do you really need this READ_ONCE?
> > > 
> > > The answer can only be "depends on the compiler's whims". :)
> > > If you think of READ_ONCE as a C11 relaxed atomic load, then yes.
> > 
> > Hm.. So the idea is to make the code "race-free” in the sense
> > that every concurrent memory access is done using READ_ONCE/WRITE_ONCE?
> > 
> > If that is the case, I think there are many other cases that need to be
> > changed, for example apic->irr_pending and vcpu->arch.pv.pv_unhalted.
> 
> There is no documentation for this in the kernel tree unfortunately.
> But yes, I think we should do that.  Using READ_ONCE/WRITE_ONCE around
> memory barriers is a start.
> 
> Paolo

I'm beginning to think that if a value is always (maybe except for init
where we don't much care about the code size anyway) accessed through
*_ONCE macros, we should just mark it volatile and be done with it. The
code will look cleaner, and there will be less space for errors
like forgetting *_ONCE macros.

Would such code (where all accesses are done through
READ_ONCE/WRITE_ONCE otherwise) be an exception to
volatile-considered-harmful.txt rules?

Cc Paul and Jonathan (for volatile-considered-harmful.txt).


-- 
MST

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#1504205 — Re: [PATCH 1/5] KVM: x86: avoid atomic operations on APICv vmentry

On Sun, Oct 16, 2016 at 05:29:24AM +0300, Michael S. Tsirkin wrote:
> On Sat, Oct 15, 2016 at 03:47:45AM -0400, Paolo Bonzini wrote:
> > 
> > > > On Oct 14, 2016, at 11:56 AM, Paolo Bonzini <pbonzini@redhat.com> wrote:
> > > >>> 
> > > >>> 	for (i = 0; i <= 7; i++) {
> > > >>> -		pir_val = xchg(&pir[i], 0);
> > > >>> -		if (pir_val)
> > > >>> +		pir_val = READ_ONCE(pir[i]);
> > > >> 
> > > >> Out of curiosity, do you really need this READ_ONCE?
> > > > 
> > > > The answer can only be "depends on the compiler's whims". :)
> > > > If you think of READ_ONCE as a C11 relaxed atomic load, then yes.
> > > 
> > > Hm.. So the idea is to make the code "race-free” in the sense
> > > that every concurrent memory access is done using READ_ONCE/WRITE_ONCE?
> > > 
> > > If that is the case, I think there are many other cases that need to be
> > > changed, for example apic->irr_pending and vcpu->arch.pv.pv_unhalted.
> > 
> > There is no documentation for this in the kernel tree unfortunately.
> > But yes, I think we should do that.  Using READ_ONCE/WRITE_ONCE around
> > memory barriers is a start.
> > 
> > Paolo
> 
> I'm beginning to think that if a value is always (maybe except for init
> where we don't much care about the code size anyway) accessed through
> *_ONCE macros, we should just mark it volatile and be done with it. The
> code will look cleaner, and there will be less space for errors
> like forgetting *_ONCE macros.
> 
> Would such code (where all accesses are done through
> READ_ONCE/WRITE_ONCE otherwise) be an exception to
> volatile-considered-harmful.txt rules?
> 
> Cc Paul and Jonathan (for volatile-considered-harmful.txt).

One concern would be the guy reading the code, to whom it might not
be obvious that the underlying access was volatile, especially if
the reference was a few levels down.

							Thanx, Paul

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#1509885 — Re: [PATCH 1/5] KVM: x86: avoid atomic operations on APICv vmentry

On Wed, Oct 19, 2016 at 04:45:48AM -0700, Paul E. McKenney wrote:
> On Sun, Oct 16, 2016 at 05:29:24AM +0300, Michael S. Tsirkin wrote:
> > On Sat, Oct 15, 2016 at 03:47:45AM -0400, Paolo Bonzini wrote:
> > > 
> > > > > On Oct 14, 2016, at 11:56 AM, Paolo Bonzini <pbonzini@redhat.com> wrote:
> > > > >>> 
> > > > >>> 	for (i = 0; i <= 7; i++) {
> > > > >>> -		pir_val = xchg(&pir[i], 0);
> > > > >>> -		if (pir_val)
> > > > >>> +		pir_val = READ_ONCE(pir[i]);
> > > > >> 
> > > > >> Out of curiosity, do you really need this READ_ONCE?
> > > > > 
> > > > > The answer can only be "depends on the compiler's whims". :)
> > > > > If you think of READ_ONCE as a C11 relaxed atomic load, then yes.
> > > > 
> > > > Hm.. So the idea is to make the code "race-free” in the sense
> > > > that every concurrent memory access is done using READ_ONCE/WRITE_ONCE?
> > > > 
> > > > If that is the case, I think there are many other cases that need to be
> > > > changed, for example apic->irr_pending and vcpu->arch.pv.pv_unhalted.
> > > 
> > > There is no documentation for this in the kernel tree unfortunately.
> > > But yes, I think we should do that.  Using READ_ONCE/WRITE_ONCE around
> > > memory barriers is a start.
> > > 
> > > Paolo
> > 
> > I'm beginning to think that if a value is always (maybe except for init
> > where we don't much care about the code size anyway) accessed through
> > *_ONCE macros, we should just mark it volatile and be done with it. The
> > code will look cleaner, and there will be less space for errors
> > like forgetting *_ONCE macros.
> > 
> > Would such code (where all accesses are done through
> > READ_ONCE/WRITE_ONCE otherwise) be an exception to
> > volatile-considered-harmful.txt rules?
> > 
> > Cc Paul and Jonathan (for volatile-considered-harmful.txt).
> 
> One concern would be the guy reading the code, to whom it might not
> be obvious that the underlying access was volatile, especially if
> the reference was a few levels down.
> 
> 							Thanx, Paul

So the guy reading the code will think access is unsafe, check it up and
realise it's fine.  Is this a big deal?  Isn't it better than the
reverse where one forgets to use READ_ONCE and gets a runtime bug?

My point is that this text:

	The key point to understand with regard to volatile is that its purpose is
	to suppress optimization, which is almost never what one really wants to do.

doesn't seem to apply anymore since we have hundreds of users of
READ_ONCE the point of which is exactly to suppress optimization.

I'm guessing this was written when we only had barrier() which is quite
unlike READ_ONCE in that it's not tied to a specific memory reference.

-- 
MST

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#1501149 — Re: [PATCH 1/5] KVM: x86: avoid atomic operations on APICv vmentry

> 
> diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c
> index 23b99f305382..63a442aefc12 100644
> --- a/arch/x86/kvm/lapic.c
> +++ b/arch/x86/kvm/lapic.c
> @@ -342,9 +342,11 @@ void __kvm_apic_update_irr(u32 *pir, void *regs)
> 	u32 i, pir_val;
> 
> 	for (i = 0; i <= 7; i++) {
> -		pir_val = xchg(&pir[i], 0);
> -		if (pir_val)
> +		pir_val = READ_ONCE(pir[i]);

Out of curiosity, do you really need this READ_ONCE?

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#1501399 — Re: [PATCH 1/5] KVM: x86: avoid atomic operations on APICv vmentry

On Fri, Oct 14, 2016 at 08:21:27PM +0200, Paolo Bonzini wrote:
> On some benchmarks (e.g. netperf with ioeventfd disabled), APICv
> posted interrupts turn out to be slower than interrupt injection via
> KVM_REQ_EVENT.
> 
> This patch optimizes a bit the IRR update, avoiding expensive atomic
> operations in the common case where PI.ON=0 at vmentry or the PIR vector
> is mostly zero.  This saves at least 20 cycles (1%) per vmexit, as
> measured by kvm-unit-tests' inl_from_qemu test (20 runs):
> 
>               | enable_apicv=1  |  enable_apicv=0
>               | mean     stdev  |  mean     stdev
>     ----------|-----------------|------------------
>     before    | 5826     32.65  |  5765     47.09
>     after     | 5809     43.42  |  5777     77.02
> 
> Of course, any change in the right column is just placebo effect. :)
> The savings are bigger if interrupts are frequent.
> 
> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
> ---
>  arch/x86/kvm/lapic.c | 6 ++++--
>  arch/x86/kvm/vmx.c   | 9 ++++++++-
>  2 files changed, 12 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c
> index 23b99f305382..63a442aefc12 100644
> --- a/arch/x86/kvm/lapic.c
> +++ b/arch/x86/kvm/lapic.c
> @@ -342,9 +342,11 @@ void __kvm_apic_update_irr(u32 *pir, void *regs)
>  	u32 i, pir_val;
>  
>  	for (i = 0; i <= 7; i++) {
> -		pir_val = xchg(&pir[i], 0);
> -		if (pir_val)
> +		pir_val = READ_ONCE(pir[i]);
> +		if (pir_val) {
> +			pir_val = xchg(&pir[i], 0);
>  			*((u32 *)(regs + APIC_IRR + i * 0x10)) |= pir_val;
> +		}
>  	}
>  }
>  EXPORT_SYMBOL_GPL(__kvm_apic_update_irr);

gcc doesn't seem to unroll this loop and it's
probably worth unrolling it

The following seems to do the trick for me on upstream - I didn't
benchmark it though. Is there a kvm unit test for interrupts?

--->

kvm: unroll the loop in __kvm_apic_update_irr.

This is hot data path in interrupt-rich workloads, worth unrolling.

Signed-off-by: Michael S. Tsirkin <mst@redhat.com>


diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c
index b62c852..0c3462c 100644
--- a/arch/x86/kvm/lapic.c
+++ b/arch/x86/kvm/lapic.c
@@ -337,7 +337,8 @@ static u8 count_vectors(void *bitmap)
 	return count;
 }
 
-void __kvm_apic_update_irr(u32 *pir, void *regs)
+void __attribute__((optimize("unroll-loops")))
+__kvm_apic_update_irr(u32 *pir, void *regs)
 {
 	u32 i, pir_val;
 

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#1501873 — Re: [PATCH 1/5] KVM: x86: avoid atomic operations on APICv vmentry

On 16/10/2016 05:21, Michael S. Tsirkin wrote:
> On Fri, Oct 14, 2016 at 08:21:27PM +0200, Paolo Bonzini wrote:
>> On some benchmarks (e.g. netperf with ioeventfd disabled), APICv
>> posted interrupts turn out to be slower than interrupt injection via
>> KVM_REQ_EVENT.
>>
>> This patch optimizes a bit the IRR update, avoiding expensive atomic
>> operations in the common case where PI.ON=0 at vmentry or the PIR vector
>> is mostly zero.  This saves at least 20 cycles (1%) per vmexit, as
>> measured by kvm-unit-tests' inl_from_qemu test (20 runs):
>>
>>               | enable_apicv=1  |  enable_apicv=0
>>               | mean     stdev  |  mean     stdev
>>     ----------|-----------------|------------------
>>     before    | 5826     32.65  |  5765     47.09
>>     after     | 5809     43.42  |  5777     77.02
>>
>> Of course, any change in the right column is just placebo effect. :)
>> The savings are bigger if interrupts are frequent.
>>
>> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
>> ---
>>  arch/x86/kvm/lapic.c | 6 ++++--
>>  arch/x86/kvm/vmx.c   | 9 ++++++++-
>>  2 files changed, 12 insertions(+), 3 deletions(-)
>>
>> diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c
>> index 23b99f305382..63a442aefc12 100644
>> --- a/arch/x86/kvm/lapic.c
>> +++ b/arch/x86/kvm/lapic.c
>> @@ -342,9 +342,11 @@ void __kvm_apic_update_irr(u32 *pir, void *regs)
>>  	u32 i, pir_val;
>>  
>>  	for (i = 0; i <= 7; i++) {
>> -		pir_val = xchg(&pir[i], 0);
>> -		if (pir_val)
>> +		pir_val = READ_ONCE(pir[i]);
>> +		if (pir_val) {
>> +			pir_val = xchg(&pir[i], 0);
>>  			*((u32 *)(regs + APIC_IRR + i * 0x10)) |= pir_val;
>> +		}
>>  	}
>>  }
>>  EXPORT_SYMBOL_GPL(__kvm_apic_update_irr);
> 
> gcc doesn't seem to unroll this loop and it's
> probably worth unrolling it
> 
> The following seems to do the trick for me on upstream - I didn't
> benchmark it though. Is there a kvm unit test for interrupts?

No, not yet.  Purely from a branch-prediction point of view I wouldn't
be so sure that it's worth unrolling it.  Because of the xchg you cannot
make the code branchless, and having a branch per iteration puts some
pressure on the BTB.

This is only a hot path in workloads that have a lot of interrupts and a
lot of vmexits.  If it's always the same interrupt (actually the same
group of 32 interrupts) that triggers, then the branch predictor will
predict the history very easily (e.g. 00001000 00001000 00001000...).

Paolo

> --->
> 
> kvm: unroll the loop in __kvm_apic_update_irr.
> 
> This is hot data path in interrupt-rich workloads, worth unrolling.
> 
> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
> 
> 
> diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c
> index b62c852..0c3462c 100644
> --- a/arch/x86/kvm/lapic.c
> +++ b/arch/x86/kvm/lapic.c
> @@ -337,7 +337,8 @@ static u8 count_vectors(void *bitmap)
>  	return count;
>  }
>  
> -void __kvm_apic_update_irr(u32 *pir, void *regs)
> +void __attribute__((optimize("unroll-loops")))
> +__kvm_apic_update_irr(u32 *pir, void *regs)
>  {
>  	u32 i, pir_val;
>  
> --
> To unsubscribe from this list: send the line "unsubscribe kvm" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> 

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#1509765 — Re: [PATCH 1/5] KVM: x86: avoid atomic operations on APICv vmentry

2016-10-14 20:21+0200, Paolo Bonzini:
> On some benchmarks (e.g. netperf with ioeventfd disabled), APICv
> posted interrupts turn out to be slower than interrupt injection via
> KVM_REQ_EVENT.
> 
> This patch optimizes a bit the IRR update, avoiding expensive atomic
> operations in the common case where PI.ON=0 at vmentry or the PIR vector
> is mostly zero.  This saves at least 20 cycles (1%) per vmexit, as
> measured by kvm-unit-tests' inl_from_qemu test (20 runs):
> 
>               | enable_apicv=1  |  enable_apicv=0
>               | mean     stdev  |  mean     stdev
>     ----------|-----------------|------------------
>     before    | 5826     32.65  |  5765     47.09
>     after     | 5809     43.42  |  5777     77.02
> 
> Of course, any change in the right column is just placebo effect. :)
> The savings are bigger if interrupts are frequent.
> 
> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
> ---
> diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
> @@ -521,6 +521,12 @@ static inline void pi_set_sn(struct pi_desc *pi_desc)
>  			(unsigned long *)&pi_desc->control);
>  }
>  
> +static inline void pi_clear_on(struct pi_desc *pi_desc)
> +{
> +	clear_bit(POSTED_INTR_ON,
> +  		  (unsigned long *)&pi_desc->control);
   ^^
   bad whitespace.

> +}

We should add an explicit smp_mb__after_atomic() for extra correctness,
because clear_bit() does not guarantee a memory barrier and we must make
sure that pir reads can't be reordered before it.
x86 clear_bit() currently uses locked instruction, though.

> +
>  static inline int pi_test_on(struct pi_desc *pi_desc)
>  {
>  	return test_bit(POSTED_INTR_ON,

Other than that,

Reviewed-by: Radim Krčmář <rkrcmar@redhat.com>

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#1509875 — Re: [PATCH 1/5] KVM: x86: avoid atomic operations on APICv vmentry

On Wed, Oct 26, 2016 at 09:53:45PM +0200, Radim Krčmář wrote:
> 2016-10-14 20:21+0200, Paolo Bonzini:
> > On some benchmarks (e.g. netperf with ioeventfd disabled), APICv
> > posted interrupts turn out to be slower than interrupt injection via
> > KVM_REQ_EVENT.
> > 
> > This patch optimizes a bit the IRR update, avoiding expensive atomic
> > operations in the common case where PI.ON=0 at vmentry or the PIR vector
> > is mostly zero.  This saves at least 20 cycles (1%) per vmexit, as
> > measured by kvm-unit-tests' inl_from_qemu test (20 runs):
> > 
> >               | enable_apicv=1  |  enable_apicv=0
> >               | mean     stdev  |  mean     stdev
> >     ----------|-----------------|------------------
> >     before    | 5826     32.65  |  5765     47.09
> >     after     | 5809     43.42  |  5777     77.02
> > 
> > Of course, any change in the right column is just placebo effect. :)
> > The savings are bigger if interrupts are frequent.
> > 
> > Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
> > ---
> > diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
> > @@ -521,6 +521,12 @@ static inline void pi_set_sn(struct pi_desc *pi_desc)
> >  			(unsigned long *)&pi_desc->control);
> >  }
> >  
> > +static inline void pi_clear_on(struct pi_desc *pi_desc)
> > +{
> > +	clear_bit(POSTED_INTR_ON,
> > +  		  (unsigned long *)&pi_desc->control);
>    ^^
>    bad whitespace.
> 
> > +}
> 
> We should add an explicit smp_mb__after_atomic() for extra correctness,
> because clear_bit() does not guarantee a memory barrier and we must make
> sure that pir reads can't be reordered before it.
> x86 clear_bit() currently uses locked instruction, though.

smp_mb__after_atomic is empty on x86 so it's
a documentation thing, not a correctness thing anyway.

> > +
> >  static inline int pi_test_on(struct pi_desc *pi_desc)
> >  {
> >  	return test_bit(POSTED_INTR_ON,
> 
> Other than that,
> 
> Reviewed-by: Radim Krčmář <rkrcmar@redhat.com>

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#1510476 — Re: [PATCH 1/5] KVM: x86: avoid atomic operations on APICv vmentry

2016-10-27 00:42+0300, Michael S. Tsirkin:
> On Wed, Oct 26, 2016 at 09:53:45PM +0200, Radim Krčmář wrote:
>> 2016-10-14 20:21+0200, Paolo Bonzini:
>> > On some benchmarks (e.g. netperf with ioeventfd disabled), APICv
>> > posted interrupts turn out to be slower than interrupt injection via
>> > KVM_REQ_EVENT.
>> > 
>> > This patch optimizes a bit the IRR update, avoiding expensive atomic
>> > operations in the common case where PI.ON=0 at vmentry or the PIR vector
>> > is mostly zero.  This saves at least 20 cycles (1%) per vmexit, as
>> > measured by kvm-unit-tests' inl_from_qemu test (20 runs):
>> > 
>> >               | enable_apicv=1  |  enable_apicv=0
>> >               | mean     stdev  |  mean     stdev
>> >     ----------|-----------------|------------------
>> >     before    | 5826     32.65  |  5765     47.09
>> >     after     | 5809     43.42  |  5777     77.02
>> > 
>> > Of course, any change in the right column is just placebo effect. :)
>> > The savings are bigger if interrupts are frequent.
>> > 
>> > Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
>> > ---
>> > diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
>> > @@ -521,6 +521,12 @@ static inline void pi_set_sn(struct pi_desc *pi_desc)
>> >  			(unsigned long *)&pi_desc->control);
>> >  }
>> >  
>> > +static inline void pi_clear_on(struct pi_desc *pi_desc)
>> > +{
>> > +	clear_bit(POSTED_INTR_ON,
>> > +  		  (unsigned long *)&pi_desc->control);
>> > +}
>> 
>> We should add an explicit smp_mb__after_atomic() for extra correctness,
>> because clear_bit() does not guarantee a memory barrier and we must make
>> sure that pir reads can't be reordered before it.
>> x86 clear_bit() currently uses locked instruction, though.
> 
> smp_mb__after_atomic is empty on x86 so it's
> a documentation thing, not a correctness thing anyway.

All atomics currently contain a barrier, but the code is also
future-proofing, not just documentation: implementation of clear_bit()
could drop the barrier and smp_mb__after_atomic() would then become a
real barrier.

Adding dma_mb__after_atomic() would be even better as this bug could
happen even on a uniprocessor with an assigned device, but people who
buy a SMP chip to run a UP kernel deserve it.

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#1510489 — Re: [PATCH 1/5] KVM: x86: avoid atomic operations on APICv vmentry

On Thu, Oct 27, 2016 at 06:44:00PM +0200, Radim Krčmář wrote:
> 2016-10-27 00:42+0300, Michael S. Tsirkin:
> > On Wed, Oct 26, 2016 at 09:53:45PM +0200, Radim Krčmář wrote:
> >> 2016-10-14 20:21+0200, Paolo Bonzini:
> >> > On some benchmarks (e.g. netperf with ioeventfd disabled), APICv
> >> > posted interrupts turn out to be slower than interrupt injection via
> >> > KVM_REQ_EVENT.
> >> > 
> >> > This patch optimizes a bit the IRR update, avoiding expensive atomic
> >> > operations in the common case where PI.ON=0 at vmentry or the PIR vector
> >> > is mostly zero.  This saves at least 20 cycles (1%) per vmexit, as
> >> > measured by kvm-unit-tests' inl_from_qemu test (20 runs):
> >> > 
> >> >               | enable_apicv=1  |  enable_apicv=0
> >> >               | mean     stdev  |  mean     stdev
> >> >     ----------|-----------------|------------------
> >> >     before    | 5826     32.65  |  5765     47.09
> >> >     after     | 5809     43.42  |  5777     77.02
> >> > 
> >> > Of course, any change in the right column is just placebo effect. :)
> >> > The savings are bigger if interrupts are frequent.
> >> > 
> >> > Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
> >> > ---
> >> > diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
> >> > @@ -521,6 +521,12 @@ static inline void pi_set_sn(struct pi_desc *pi_desc)
> >> >  			(unsigned long *)&pi_desc->control);
> >> >  }
> >> >  
> >> > +static inline void pi_clear_on(struct pi_desc *pi_desc)
> >> > +{
> >> > +	clear_bit(POSTED_INTR_ON,
> >> > +  		  (unsigned long *)&pi_desc->control);
> >> > +}
> >> 
> >> We should add an explicit smp_mb__after_atomic() for extra correctness,
> >> because clear_bit() does not guarantee a memory barrier and we must make
> >> sure that pir reads can't be reordered before it.
> >> x86 clear_bit() currently uses locked instruction, though.
> > 
> > smp_mb__after_atomic is empty on x86 so it's
> > a documentation thing, not a correctness thing anyway.
> 
> All atomics currently contain a barrier, but the code is also
> future-proofing, not just documentation: implementation of clear_bit()
> could drop the barrier and smp_mb__after_atomic() would then become a
> real barrier.
> 
> Adding dma_mb__after_atomic() would be even better as this bug could
> happen even on a uniprocessor with an assigned device, but people who
> buy a SMP chip to run a UP kernel deserve it.

Not doing dma so does not seem to make sense ...
Why do you need a barrier on a UP kernel?

-- 
MST

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#1510501 — Re: [PATCH 1/5] KVM: x86: avoid atomic operations on APICv vmentry

2016-10-27 19:51+0300, Michael S. Tsirkin:
> On Thu, Oct 27, 2016 at 06:44:00PM +0200, Radim Krčmář wrote:
>> 2016-10-27 00:42+0300, Michael S. Tsirkin:
>> > On Wed, Oct 26, 2016 at 09:53:45PM +0200, Radim Krčmář wrote:
>> >> 2016-10-14 20:21+0200, Paolo Bonzini:
>> >> > On some benchmarks (e.g. netperf with ioeventfd disabled), APICv
>> >> > posted interrupts turn out to be slower than interrupt injection via
>> >> > KVM_REQ_EVENT.
>> >> > 
>> >> > This patch optimizes a bit the IRR update, avoiding expensive atomic
>> >> > operations in the common case where PI.ON=0 at vmentry or the PIR vector
>> >> > is mostly zero.  This saves at least 20 cycles (1%) per vmexit, as
>> >> > measured by kvm-unit-tests' inl_from_qemu test (20 runs):
>> >> > 
>> >> >               | enable_apicv=1  |  enable_apicv=0
>> >> >               | mean     stdev  |  mean     stdev
>> >> >     ----------|-----------------|------------------
>> >> >     before    | 5826     32.65  |  5765     47.09
>> >> >     after     | 5809     43.42  |  5777     77.02
>> >> > 
>> >> > Of course, any change in the right column is just placebo effect. :)
>> >> > The savings are bigger if interrupts are frequent.
>> >> > 
>> >> > Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
>> >> > ---
>> >> > diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
>> >> > @@ -521,6 +521,12 @@ static inline void pi_set_sn(struct pi_desc *pi_desc)
>> >> >  			(unsigned long *)&pi_desc->control);
>> >> >  }
>> >> >  
>> >> > +static inline void pi_clear_on(struct pi_desc *pi_desc)
>> >> > +{
>> >> > +	clear_bit(POSTED_INTR_ON,
>> >> > +  		  (unsigned long *)&pi_desc->control);
>> >> > +}
>> >> 
>> >> We should add an explicit smp_mb__after_atomic() for extra correctness,
>> >> because clear_bit() does not guarantee a memory barrier and we must make
>> >> sure that pir reads can't be reordered before it.
>> >> x86 clear_bit() currently uses locked instruction, though.
>> > 
>> > smp_mb__after_atomic is empty on x86 so it's
>> > a documentation thing, not a correctness thing anyway.
>> 
>> All atomics currently contain a barrier, but the code is also
>> future-proofing, not just documentation: implementation of clear_bit()
>> could drop the barrier and smp_mb__after_atomic() would then become a
>> real barrier.
>> 
>> Adding dma_mb__after_atomic() would be even better as this bug could
>> happen even on a uniprocessor with an assigned device, but people who
>> buy a SMP chip to run a UP kernel deserve it.
> 
> Not doing dma so does not seem to make sense ...

IOMMU does -- it writes to the PIR and sets ON asynchronously.

> Why do you need a barrier on a UP kernel?

If pi_clear_on() doesn't contain a memory barrier (possible future),
then we have the following race: (pir[0] begins as 0.)

    KVM                           |  IOMMU
   -------------------------------+-------------
   pir_val = ACCESS_ONCE(pir[0])  |
                                  | pir[0] = 123
                                  | pi_set_on()
   pi_clear_on()                  |
   if (pir_val)                   |

ACCESS_ONCE() does not prevent the CPU to prefetch pir[0] (ACCESS_ONCE
does nothing in this patch), so if there was 0 in pir[0] before IOMMU
wrote to it, then our optimization to avoid the xchg would yield a false
negative and the interrupt would be lost.

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#1510994 — Re: [PATCH 1/5] KVM: x86: avoid atomic operations on APICv vmentry

On 27/10/2016 19:06, Radim Krčmář wrote:
> 2016-10-27 19:51+0300, Michael S. Tsirkin:
>> On Thu, Oct 27, 2016 at 06:44:00PM +0200, Radim Krčmář wrote:
>>> 2016-10-27 00:42+0300, Michael S. Tsirkin:
>>>> On Wed, Oct 26, 2016 at 09:53:45PM +0200, Radim Krčmář wrote:
>>>>> 2016-10-14 20:21+0200, Paolo Bonzini:
>>>>>> On some benchmarks (e.g. netperf with ioeventfd disabled), APICv
>>>>>> posted interrupts turn out to be slower than interrupt injection via
>>>>>> KVM_REQ_EVENT.
>>>>>>
>>>>>> This patch optimizes a bit the IRR update, avoiding expensive atomic
>>>>>> operations in the common case where PI.ON=0 at vmentry or the PIR vector
>>>>>> is mostly zero.  This saves at least 20 cycles (1%) per vmexit, as
>>>>>> measured by kvm-unit-tests' inl_from_qemu test (20 runs):
>>>>>>
>>>>>>               | enable_apicv=1  |  enable_apicv=0
>>>>>>               | mean     stdev  |  mean     stdev
>>>>>>     ----------|-----------------|------------------
>>>>>>     before    | 5826     32.65  |  5765     47.09
>>>>>>     after     | 5809     43.42  |  5777     77.02
>>>>>>
>>>>>> Of course, any change in the right column is just placebo effect. :)
>>>>>> The savings are bigger if interrupts are frequent.
>>>>>>
>>>>>> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
>>>>>> ---
>>>>>> diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
>>>>>> @@ -521,6 +521,12 @@ static inline void pi_set_sn(struct pi_desc *pi_desc)
>>>>>>  			(unsigned long *)&pi_desc->control);
>>>>>>  }
>>>>>>  
>>>>>> +static inline void pi_clear_on(struct pi_desc *pi_desc)
>>>>>> +{
>>>>>> +	clear_bit(POSTED_INTR_ON,
>>>>>> +  		  (unsigned long *)&pi_desc->control);
>>>>>> +}
>>>>>
>>>>> We should add an explicit smp_mb__after_atomic() for extra correctness,
>>>>> because clear_bit() does not guarantee a memory barrier and we must make
>>>>> sure that pir reads can't be reordered before it.
>>>>> x86 clear_bit() currently uses locked instruction, though.
>>>>
>>>> smp_mb__after_atomic is empty on x86 so it's
>>>> a documentation thing, not a correctness thing anyway.
>>>
>>> All atomics currently contain a barrier, but the code is also
>>> future-proofing, not just documentation: implementation of clear_bit()
>>> could drop the barrier and smp_mb__after_atomic() would then become a
>>> real barrier.
>>>
>>> Adding dma_mb__after_atomic() would be even better as this bug could
>>> happen even on a uniprocessor with an assigned device, but people who
>>> buy a SMP chip to run a UP kernel deserve it.
>>
>> Not doing dma so does not seem to make sense ...
> 
> IOMMU does -- it writes to the PIR and sets ON asynchronously.

I can use either __smp_mb__after_atomic or virt_mb__after_atomic.  The
difference is documentation only, since all of them are
compiler-barriers only on x86.

Preferences?

Thanks,

Paolo

>> Why do you need a barrier on a UP kernel?
> 
> If pi_clear_on() doesn't contain a memory barrier (possible future),
> then we have the following race: (pir[0] begins as 0.)
> 
>     KVM                           |  IOMMU
>    -------------------------------+-------------
>    pir_val = ACCESS_ONCE(pir[0])  |
>                                   | pir[0] = 123
>                                   | pi_set_on()
>    pi_clear_on()                  |
>    if (pir_val)                   |
> 
> ACCESS_ONCE() does not prevent the CPU to prefetch pir[0] (ACCESS_ONCE
> does nothing in this patch), so if there was 0 in pir[0] before IOMMU
> wrote to it, then our optimization to avoid the xchg would yield a false
> negative and the interrupt would be lost.
> 

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#1511453 — Re: [PATCH 1/5] KVM: x86: avoid atomic operations on APICv vmentry

On Fri, Oct 28, 2016 at 11:39:44AM +0200, Paolo Bonzini wrote:
> 
> 
> On 27/10/2016 19:06, Radim Krčmář wrote:
> > 2016-10-27 19:51+0300, Michael S. Tsirkin:
> >> On Thu, Oct 27, 2016 at 06:44:00PM +0200, Radim Krčmář wrote:
> >>> 2016-10-27 00:42+0300, Michael S. Tsirkin:
> >>>> On Wed, Oct 26, 2016 at 09:53:45PM +0200, Radim Krčmář wrote:
> >>>>> 2016-10-14 20:21+0200, Paolo Bonzini:
> >>>>>> On some benchmarks (e.g. netperf with ioeventfd disabled), APICv
> >>>>>> posted interrupts turn out to be slower than interrupt injection via
> >>>>>> KVM_REQ_EVENT.
> >>>>>>
> >>>>>> This patch optimizes a bit the IRR update, avoiding expensive atomic
> >>>>>> operations in the common case where PI.ON=0 at vmentry or the PIR vector
> >>>>>> is mostly zero.  This saves at least 20 cycles (1%) per vmexit, as
> >>>>>> measured by kvm-unit-tests' inl_from_qemu test (20 runs):
> >>>>>>
> >>>>>>               | enable_apicv=1  |  enable_apicv=0
> >>>>>>               | mean     stdev  |  mean     stdev
> >>>>>>     ----------|-----------------|------------------
> >>>>>>     before    | 5826     32.65  |  5765     47.09
> >>>>>>     after     | 5809     43.42  |  5777     77.02
> >>>>>>
> >>>>>> Of course, any change in the right column is just placebo effect. :)
> >>>>>> The savings are bigger if interrupts are frequent.
> >>>>>>
> >>>>>> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
> >>>>>> ---
> >>>>>> diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
> >>>>>> @@ -521,6 +521,12 @@ static inline void pi_set_sn(struct pi_desc *pi_desc)
> >>>>>>  			(unsigned long *)&pi_desc->control);
> >>>>>>  }
> >>>>>>  
> >>>>>> +static inline void pi_clear_on(struct pi_desc *pi_desc)
> >>>>>> +{
> >>>>>> +	clear_bit(POSTED_INTR_ON,
> >>>>>> +  		  (unsigned long *)&pi_desc->control);
> >>>>>> +}
> >>>>>
> >>>>> We should add an explicit smp_mb__after_atomic() for extra correctness,
> >>>>> because clear_bit() does not guarantee a memory barrier and we must make
> >>>>> sure that pir reads can't be reordered before it.
> >>>>> x86 clear_bit() currently uses locked instruction, though.
> >>>>
> >>>> smp_mb__after_atomic is empty on x86 so it's
> >>>> a documentation thing, not a correctness thing anyway.
> >>>
> >>> All atomics currently contain a barrier, but the code is also
> >>> future-proofing, not just documentation: implementation of clear_bit()
> >>> could drop the barrier and smp_mb__after_atomic() would then become a
> >>> real barrier.
> >>>
> >>> Adding dma_mb__after_atomic() would be even better as this bug could
> >>> happen even on a uniprocessor with an assigned device, but people who
> >>> buy a SMP chip to run a UP kernel deserve it.
> >>
> >> Not doing dma so does not seem to make sense ...
> > 
> > IOMMU does -- it writes to the PIR and sets ON asynchronously.
> 
> I can use either __smp_mb__after_atomic or virt_mb__after_atomic.  The
> difference is documentation only, since all of them are
> compiler-barriers only on x86.

A comment is also an option.

> Preferences?
> 
> Thanks,
> 
> Paolo

virt_ is for a VM guest. Pls don't use for host side code.
I thought it's clear enough but maybe I should add
more documentation.

> >> Why do you need a barrier on a UP kernel?
> > 
> > If pi_clear_on() doesn't contain a memory barrier (possible future),
> > then we have the following race: (pir[0] begins as 0.)
> > 
> >     KVM                           |  IOMMU
> >    -------------------------------+-------------
> >    pir_val = ACCESS_ONCE(pir[0])  |
> >                                   | pir[0] = 123
> >                                   | pi_set_on()
> >    pi_clear_on()                  |
> >    if (pir_val)                   |
> > 
> > ACCESS_ONCE() does not prevent the CPU to prefetch pir[0] (ACCESS_ONCE
> > does nothing in this patch), so if there was 0 in pir[0] before IOMMU
> > wrote to it, then our optimization to avoid the xchg would yield a false
> > negative and the interrupt would be lost.
> > 

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#1501133 — [PATCH 5/5] KVM: vmx: clear pending interrupts on KVM_SET_LAPIC

Pending interrupts might be in the PI descriptor when the
LAPIC is restored from an external state; we do not want
them to be injected.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
 arch/x86/kvm/lapic.c | 3 +--
 arch/x86/kvm/vmx.c   | 9 +++++++++
 2 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c
index 255b5e1658f6..271cb9c22777 100644
--- a/arch/x86/kvm/lapic.c
+++ b/arch/x86/kvm/lapic.c
@@ -2088,8 +2088,7 @@ int kvm_apic_set_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s)
 				1 : count_vectors(apic->regs + APIC_ISR);
 	apic->highest_isr_cache = -1;
 	if (vcpu->arch.apicv_active) {
-		if (kvm_x86_ops->apicv_post_state_restore)
-			kvm_x86_ops->apicv_post_state_restore(vcpu);
+		kvm_x86_ops->apicv_post_state_restore(vcpu);
 		kvm_x86_ops->hwapic_irr_update(vcpu,
 				apic_find_highest_irr(apic));
 		kvm_x86_ops->hwapic_isr_update(vcpu,
diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
index 1e4ff8c2cdbe..290d80f9fcbd 100644
--- a/arch/x86/kvm/vmx.c
+++ b/arch/x86/kvm/vmx.c
@@ -8617,6 +8617,14 @@ static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
 	vmx_hwapic_irr_update(vcpu, max_irr);
 }
 
+static void vmx_apicv_post_state_restore(struct kvm_vcpu *vcpu)
+{
+	struct vcpu_vmx *vmx = to_vmx(vcpu);
+
+	pi_clear_on(&vmx->pi_desc);
+	memset(vmx->pi_desc.pir, 0, sizeof(vmx->pi_desc.pir));
+}
+
 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
 {
 	if (!kvm_vcpu_apicv_active(vcpu))
@@ -11327,6 +11335,7 @@ static struct kvm_x86_ops vmx_x86_ops = {
 	.get_enable_apicv = vmx_get_enable_apicv,
 	.refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl,
 	.load_eoi_exitmap = vmx_load_eoi_exitmap,
+	.apicv_post_state_restore = vmx_apicv_post_state_restore,
 	.hwapic_irr_update = vmx_hwapic_irr_update,
 	.hwapic_isr_update = vmx_hwapic_isr_update,
 	.sync_pir_to_irr = vmx_sync_pir_to_irr,
-- 
1.8.3.1

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#1509785 — Re: [PATCH 5/5] KVM: vmx: clear pending interrupts on KVM_SET_LAPIC

2016-10-14 20:21+0200, Paolo Bonzini:
> Pending interrupts might be in the PI descriptor when the
> LAPIC is restored from an external state; we do not want
> them to be injected.
> 
> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
> ---

Reviewed-by: Radim Krčmář <rkrcmar@redhat.com>

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#1509882

On Fri, Oct 14, 2016 at 08:21:26PM +0200, Paolo Bonzini wrote:
> On some benchmarks (e.g. netperf with ioeventfd disabled), APICv
> posted interrupts turn out to be slower than interrupt injection via
> KVM_REQ_EVENT.
> 
> These patches save 40 cycles on kvm-unit-tests "inl" tests (1-2%), but I
> suspect the effect is bigger on workloads that inject interrupts heavily.
> 
> Patches 1-2 are micro-optimization of the APICv vmentry code.
> 
> The interesting one is patch 3.  The aim is for APICv to not use
> KVM_REQ_EVENT at all for interrupts, therefore turning APICv's weakness
> (having to look at PIR on every vmentry) into a strength (because
> checking PIR.ON is cheaper than processing KVM_REQ_EVENT).  I find that
> the new code overall makes more sense than the old one, and I like that
> more of the logic is contained within vmx_deliver_posted_interrupt and
> vmx_sync_pir_to_irr.  KVM_REQ_EVENT did protect from mistakes, so the new
> code is more delicate, but I still prefer that to duct tape. :)
> 
> Patches 4 and 5 are other cleanups.

FWIW, series

Acked-by: Michael S. Tsirkin <mst@redhat.com>

I still think we should make pir volatile but we
can argue about that later.

> Paolo
> 
> Paolo Bonzini (5):
>   KVM: x86: avoid atomic operations on APICv vmentry
>   KVM: x86: do not scan IRR twice on APICv vmentry
>   KVM: x86: do not use KVM_REQ_EVENT for APICv interrupt injection
>   KVM: x86: remove unnecessary sync_pir_to_irr
>   KVM: vmx: clear pending interrupts on KVM_SET_LAPIC
> 
>  arch/x86/kvm/lapic.c | 45 +++++++++++++++++++++++++++++----------------
>  arch/x86/kvm/lapic.h |  4 ++--
>  arch/x86/kvm/vmx.c   | 44 ++++++++++++++++++++++++++++++++------------
>  arch/x86/kvm/x86.c   | 45 +++++++++++++++++++++++++--------------------
>  4 files changed, 88 insertions(+), 50 deletions(-)
> 
> -- 
> 1.8.3.1

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