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| Started by | Vincent Siles <vincent.siles@provenrun.com> |
|---|---|
| First post | 2016-09-08 11:40 +0200 |
| Last post | 2016-09-08 12:00 +0200 |
| Articles | 3 — 2 participants |
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lsl / lsr possible confusion in v7_flush_dcache_all Vincent Siles <vincent.siles@provenrun.com> - 2016-09-08 11:40 +0200
Re: lsl / lsr possible confusion in v7_flush_dcache_all Will Deacon <will.deacon@arm.com> - 2016-09-08 11:40 +0200
Re: lsl / lsr possible confusion in v7_flush_dcache_all Vincent Siles <vincent.siles@provenrun.com> - 2016-09-08 12:00 +0200
| From | Vincent Siles <vincent.siles@provenrun.com> |
|---|---|
| Date | 2016-09-08 11:40 +0200 |
| Subject | lsl / lsr possible confusion in v7_flush_dcache_all |
| Message-ID | <sf3Yl-417-7@gated-at.bofh.it> |
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Hi ! While reading the v7_flush_dcache_all (arch/arm/mm/cache-v7.S), I stumbled upon this line: # r10 is the current cache level 127: add r2, r10, r10, lsr #1 @ work out 3x current cache level If we want r2 to be 3 * r10, we should compute r10 + (r10 << 1), which is lsl, not lsr. I check for a recent kernel, the issue seems to still be here: repo: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git revision: d71f058617564750261b673ea9b3352382b9cde4 Best regards, Vincent Siles
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| From | Will Deacon <will.deacon@arm.com> |
|---|---|
| Date | 2016-09-08 11:40 +0200 |
| Message-ID | <sf3Yl-417-13@gated-at.bofh.it> |
| In reply to | #1478971 |
On Thu, Sep 08, 2016 at 11:15:20AM +0200, Vincent Siles wrote: > While reading the v7_flush_dcache_all (arch/arm/mm/cache-v7.S), I > stumbled upon this line: > > # r10 is the current cache level > 127: add r2, r10, r10, lsr #1 @ work out 3x current cache level > > If we want r2 to be 3 * r10, we should compute r10 + (r10 << 1), which > is lsl, not lsr. > > I check for a recent kernel, the issue seems to still be here: > repo: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git > revision: d71f058617564750261b673ea9b3352382b9cde4 This code is take pretty much verbatim from the ARM ARM and, despite being fairly obfuscated, does what it says on the tin. r10 is incremented by 2 each time round the loop, so this is basically doing 2i + (2i / 2). Will
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| From | Vincent Siles <vincent.siles@provenrun.com> |
|---|---|
| Date | 2016-09-08 12:00 +0200 |
| Message-ID | <sf4hI-47K-29@gated-at.bofh.it> |
| In reply to | #1478972 |
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Oh, right. I missed that ! Thank you for the help. Best, Vincent On 08-09-16 10:38:01, Will Deacon wrote: > On Thu, Sep 08, 2016 at 11:15:20AM +0200, Vincent Siles wrote: > > While reading the v7_flush_dcache_all (arch/arm/mm/cache-v7.S), I > > stumbled upon this line: > > > > # r10 is the current cache level > > 127: add r2, r10, r10, lsr #1 @ work out 3x current cache level > > > > If we want r2 to be 3 * r10, we should compute r10 + (r10 << 1), which > > is lsl, not lsr. > > > > I check for a recent kernel, the issue seems to still be here: > > repo: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git > > revision: d71f058617564750261b673ea9b3352382b9cde4 > > This code is take pretty much verbatim from the ARM ARM and, despite > being fairly obfuscated, does what it says on the tin. r10 is incremented > by 2 each time round the loop, so this is basically doing 2i + (2i / 2). > > Will
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