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[PATCH 2/2] ARM: dts: exynos: Fix mismatched values of SD drive strengh configuration on exynos4415

Started byKrzysztof Kozlowski <k.kozlowski@samsung.com>
First post2016-09-01 10:40 +0200
Last post2016-09-01 13:30 +0200
Articles 4 — 3 participants

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  [PATCH 2/2] ARM: dts: exynos: Fix mismatched values of SD drive  strengh configuration on exynos4415 Krzysztof Kozlowski <k.kozlowski@samsung.com> - 2016-09-01 10:40 +0200
    Re: [PATCH 2/2] ARM: dts: exynos: Fix mismatched values of SD drive  strengh configuration on exynos4415 Javier Martinez Canillas <javier@osg.samsung.com> - 2016-09-01 12:30 +0200
    Re: [PATCH 2/2] ARM: dts: exynos: Fix mismatched values of SD drive  strengh configuration on exynos4415 Krzysztof Kozlowski <k.kozlowski@samsung.com> - 2016-09-01 13:30 +0200
    Re: [PATCH 2/2] ARM: dts: exynos: Fix mismatched values of SD drive  strengh configuration on exynos4415 Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> - 2016-09-01 13:30 +0200

#1474170 — [PATCH 2/2] ARM: dts: exynos: Fix mismatched values of SD drive strengh configuration on exynos4415

FromKrzysztof Kozlowski <k.kozlowski@samsung.com>
Date2016-09-01 10:40 +0200
Subject[PATCH 2/2] ARM: dts: exynos: Fix mismatched values of SD drive strengh configuration on exynos4415
Message-ID<scvHr-78u-7@gated-at.bofh.it>
The pinctrl drive strength register on exynos4415 is 2-bit wide for each
pin.  The pins for SD2 were configured with value of 4.  The driver does
not validate the value so this overflow effectively set a bit 1 in
adjacent pins thus configuring them to drive strength 2x.

The author's intention was probably to set drive strength of 4x.
All other SD pins are configured with drive strength of 4x.  Fix these
with same pattern.

Fixes: 9246e7ff24c5 ("ARM: dts: Add dts files for exynos4415 SoC")
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
---
 arch/arm/boot/dts/exynos4415-pinctrl.dtsi | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm/boot/dts/exynos4415-pinctrl.dtsi b/arch/arm/boot/dts/exynos4415-pinctrl.dtsi
index f54aee53b6ec..76cfd872ead3 100644
--- a/arch/arm/boot/dts/exynos4415-pinctrl.dtsi
+++ b/arch/arm/boot/dts/exynos4415-pinctrl.dtsi
@@ -480,14 +480,14 @@
 		samsung,pins = "gpk2-0";
 		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
 		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-		samsung,pin-drv = <4>;
+		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
 	};
 
 	sd2_cmd: sd2-cmd {
 		samsung,pins = "gpk2-1";
 		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
 		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-		samsung,pin-drv = <4>;
+		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
 	};
 
 	sd2_cd: sd2-cd {
@@ -501,14 +501,14 @@
 		samsung,pins = "gpk2-3";
 		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
 		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
-		samsung,pin-drv = <4>;
+		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
 	};
 
 	sd2_bus4: sd2-bus-width4 {
 		samsung,pins = "gpk2-4", "gpk2-5", "gpk2-6";
 		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
 		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
-		samsung,pin-drv = <4>;
+		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
 	};
 
 	cam_port_b_io: cam-port-b-io {
-- 
1.9.1

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#1474259

FromJavier Martinez Canillas <javier@osg.samsung.com>
Date2016-09-01 12:30 +0200
Message-ID<scxpU-vd-35@gated-at.bofh.it>
In reply to#1474170
Hello Krzysztof,

On 09/01/2016 10:37 AM, Krzysztof Kozlowski wrote:
> The pinctrl drive strength register on exynos4415 is 2-bit wide for each
> pin.  The pins for SD2 were configured with value of 4.  The driver does
> not validate the value so this overflow effectively set a bit 1 in
> adjacent pins thus configuring them to drive strength 2x.
> 
> The author's intention was probably to set drive strength of 4x.
> All other SD pins are configured with drive strength of 4x.  Fix these
> with same pattern.
> 
> Fixes: 9246e7ff24c5 ("ARM: dts: Add dts files for exynos4415 SoC")
> Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
> ---

Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>

Best regards,
-- 
Javier Martinez Canillas
Open Source Group
Samsung Research America

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#1474324

FromKrzysztof Kozlowski <k.kozlowski@samsung.com>
Date2016-09-01 13:30 +0200
Message-ID<scylZ-1an-61@gated-at.bofh.it>
In reply to#1474170
On 09/01/2016 01:21 PM, Bartlomiej Zolnierkiewicz wrote:
> BTW This reminds me that there are still no board files for Exynos4415
> SoC based boards so maybe we should consider removal of its support?

Fine with me. I would ack such patches so (anyone) please go ahead. :)

Best regards,
Krzysztof

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#1474332

FromBartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Date2016-09-01 13:30 +0200
Message-ID<scylZ-1an-63@gated-at.bofh.it>
In reply to#1474170
Hi,

On Thursday, September 01, 2016 10:37:02 AM Krzysztof Kozlowski wrote:
> The pinctrl drive strength register on exynos4415 is 2-bit wide for each
> pin.  The pins for SD2 were configured with value of 4.  The driver does
> not validate the value so this overflow effectively set a bit 1 in
> adjacent pins thus configuring them to drive strength 2x.
> 
> The author's intention was probably to set drive strength of 4x.
> All other SD pins are configured with drive strength of 4x.  Fix these
> with same pattern.
> 
> Fixes: 9246e7ff24c5 ("ARM: dts: Add dts files for exynos4415 SoC")
> Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>

Reviewed-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>

BTW This reminds me that there are still no board files for Exynos4415
SoC based boards so maybe we should consider removal of its support?

> ---
>  arch/arm/boot/dts/exynos4415-pinctrl.dtsi | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/exynos4415-pinctrl.dtsi b/arch/arm/boot/dts/exynos4415-pinctrl.dtsi
> index f54aee53b6ec..76cfd872ead3 100644
> --- a/arch/arm/boot/dts/exynos4415-pinctrl.dtsi
> +++ b/arch/arm/boot/dts/exynos4415-pinctrl.dtsi
> @@ -480,14 +480,14 @@
>  		samsung,pins = "gpk2-0";
>  		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
>  		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> -		samsung,pin-drv = <4>;
> +		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
>  	};
>  
>  	sd2_cmd: sd2-cmd {
>  		samsung,pins = "gpk2-1";
>  		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
>  		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> -		samsung,pin-drv = <4>;
> +		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
>  	};
>  
>  	sd2_cd: sd2-cd {
> @@ -501,14 +501,14 @@
>  		samsung,pins = "gpk2-3";
>  		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
>  		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> -		samsung,pin-drv = <4>;
> +		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
>  	};
>  
>  	sd2_bus4: sd2-bus-width4 {
>  		samsung,pins = "gpk2-4", "gpk2-5", "gpk2-6";
>  		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
>  		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> -		samsung,pin-drv = <4>;
> +		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
>  	};
>  
>  	cam_port_b_io: cam-port-b-io {

Best regards,
--
Bartlomiej Zolnierkiewicz
Samsung R&D Institute Poland
Samsung Electronics

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