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Groups > linux.kernel > #1557303 > unrolled thread
| Started by | Kishon Vijay Abraham I <kishon@ti.com> |
|---|---|
| First post | 2017-01-12 11:30 +0100 |
| Last post | 2017-01-12 11:50 +0100 |
| Articles | 20 on this page of 42 — 3 participants |
Back to article view | Back to linux.kernel
[PATCH 00/37] PCI: Support for configurable PCI endpoint Kishon Vijay Abraham I <kishon@ti.com> - 2017-01-12 11:30 +0100
[PATCH 23/37] PCI: dwc: Add *ops* to start and stop pcie link Kishon Vijay Abraham I <kishon@ti.com> - 2017-01-12 11:30 +0100
[PATCH 26/37] PCI: dwc: dra7xx: Facilitate wrapper and msi interrupts to be enabled independently Kishon Vijay Abraham I <kishon@ti.com> - 2017-01-12 11:40 +0100
[PATCH 32/37] Documentation: misc-devices: Add Documentation for pci-endpoint-test driver Kishon Vijay Abraham I <kishon@ti.com> - 2017-01-12 11:40 +0100
[PATCH 09/37] PCI: dwc: designware: Parse *num-lanes* property in dw_pcie_setup_rc Kishon Vijay Abraham I <kishon@ti.com> - 2017-01-12 11:40 +0100
Re: [PATCH 09/37] PCI: dwc: designware: Parse *num-lanes* property in dw_pcie_setup_rc Joao Pinto <Joao.Pinto@synopsys.com> - 2017-01-13 18:30 +0100
Re: [PATCH 09/37] PCI: dwc: designware: Parse *num-lanes* property in dw_pcie_setup_rc Kishon Vijay Abraham I <kishon@ti.com> - 2017-01-16 06:30 +0100
Re: [PATCH 09/37] PCI: dwc: designware: Parse *num-lanes* property in dw_pcie_setup_rc Joao Pinto <Joao.Pinto@synopsys.com> - 2017-01-16 11:30 +0100
[PATCH 29/37] PCI: dwc: dra7xx: Workaround for errata id i870 Kishon Vijay Abraham I <kishon@ti.com> - 2017-01-12 11:40 +0100
[PATCH 07/37] PCI: dwc: designware: Get device pointer at the start of dw_pcie_host_init Kishon Vijay Abraham I <kishon@ti.com> - 2017-01-12 11:40 +0100
Re: [PATCH 07/37] PCI: dwc: designware: Get device pointer at the start of dw_pcie_host_init Joao Pinto <Joao.Pinto@synopsys.com> - 2017-01-13 18:30 +0100
[PATCH 20/37] Documentation: PCI: Add binding documentation for pci-test endpoint function Kishon Vijay Abraham I <kishon@ti.com> - 2017-01-12 11:40 +0100
[PATCH 33/37] tools: PCI: Add a userspace tool to test PCI endpoint Kishon Vijay Abraham I <kishon@ti.com> - 2017-01-12 11:40 +0100
[PATCH 35/37] MAINTAINERS: add PCI EP maintainer Kishon Vijay Abraham I <kishon@ti.com> - 2017-01-12 11:40 +0100
[PATCH 37/37] ARM: dts: DRA7: Add pcie1 dt node for EP mode Kishon Vijay Abraham I <kishon@ti.com> - 2017-01-12 11:40 +0100
[PATCH 30/37] dt-bindings: PCI: dra7xx: Add dt bindings to enable legacy mode Kishon Vijay Abraham I <kishon@ti.com> - 2017-01-12 11:40 +0100
[PATCH 17/37] Documentation: PCI: Guide to use pci endpoint configfs Kishon Vijay Abraham I <kishon@ti.com> - 2017-01-12 11:40 +0100
[PATCH 34/37] tools: PCI: Add sample test script to invoke pcitest Kishon Vijay Abraham I <kishon@ti.com> - 2017-01-12 11:40 +0100
[PATCH 22/37] PCI: dwc: Modify dbi accessors to access data of 4/2/1 bytes Kishon Vijay Abraham I <kishon@ti.com> - 2017-01-12 11:40 +0100
[PATCH 15/37] Documentation: PCI: Guide to use PCI Endpoint Core Layer Kishon Vijay Abraham I <kishon@ti.com> - 2017-01-12 11:40 +0100
[PATCH 36/37] ARM: DRA7: clockdomain: Change the CLKTRCTRL of CM_PCIE_CLKSTCTRL to SW_WKUP Kishon Vijay Abraham I <kishon@ti.com> - 2017-01-12 11:40 +0100
Re: [PATCH 36/37] ARM: DRA7: clockdomain: Change the CLKTRCTRL of CM_PCIE_CLKSTCTRL to SW_WKUP Tony Lindgren <tony@atomide.com> - 2017-01-13 18:20 +0100
Re: [PATCH 36/37] ARM: DRA7: clockdomain: Change the CLKTRCTRL of CM_PCIE_CLKSTCTRL to SW_WKUP Kishon Vijay Abraham I <kishon@ti.com> - 2017-01-16 07:10 +0100
[PATCH 05/37] PCI: dwc: Add platform_set_drvdata Kishon Vijay Abraham I <kishon@ti.com> - 2017-01-12 11:40 +0100
Re: [PATCH 05/37] PCI: dwc: Add platform_set_drvdata Joao Pinto <Joao.Pinto@synopsys.com> - 2017-01-13 18:20 +0100
[PATCH 19/37] PCI: endpoint: functions: Add an EP function to test PCI Kishon Vijay Abraham I <kishon@ti.com> - 2017-01-12 11:40 +0100
[PATCH 18/37] Documentation: PCI: Add specification for the *pci test* function device Kishon Vijay Abraham I <kishon@ti.com> - 2017-01-12 11:40 +0100
[PATCH 25/37] dt-bindings: PCI: Add dt bindings for pci designware EP mode Kishon Vijay Abraham I <kishon@ti.com> - 2017-01-12 11:40 +0100
[PATCH 27/37] PCI: dwc: dra7xx: Add EP mode support Kishon Vijay Abraham I <kishon@ti.com> - 2017-01-12 11:40 +0100
[PATCH 28/37] dt-bindings: PCI: dra7xx: Add dt bindings for pci dra7xx EP mode Kishon Vijay Abraham I <kishon@ti.com> - 2017-01-12 11:40 +0100
[PATCH 31/37] misc: Add host side pci driver for pci test function device Kishon Vijay Abraham I <kishon@ti.com> - 2017-01-12 11:40 +0100
[PATCH 24/37] PCI: dwc: designware: Add EP mode support Kishon Vijay Abraham I <kishon@ti.com> - 2017-01-12 11:40 +0100
[PATCH 21/37] PCI: dwc: Modify dbi accessors to take dbi_base as argument Kishon Vijay Abraham I <kishon@ti.com> - 2017-01-12 11:40 +0100
[PATCH 10/37] PCI: dwc: designware: Fix style errors in pcie-designware.c Kishon Vijay Abraham I <kishon@ti.com> - 2017-01-12 11:50 +0100
Re: [PATCH 10/37] PCI: dwc: designware: Fix style errors in pcie-designware.c Joao Pinto <Joao.Pinto@synopsys.com> - 2017-01-13 17:50 +0100
[PATCH 11/37] PCI: dwc: Split pcie-designware.c into host and core files Kishon Vijay Abraham I <kishon@ti.com> - 2017-01-12 11:50 +0100
Re: [PATCH 11/37] PCI: dwc: Split pcie-designware.c into host and core files Joao Pinto <Joao.Pinto@synopsys.com> - 2017-01-13 18:00 +0100
Re: [PATCH 11/37] PCI: dwc: Split pcie-designware.c into host and core files Kishon Vijay Abraham I <kishon@ti.com> - 2017-01-16 06:30 +0100
Re: [PATCH 11/37] PCI: dwc: Split pcie-designware.c into host and core files Joao Pinto <Joao.Pinto@synopsys.com> - 2017-01-16 11:30 +0100
Re: [PATCH 11/37] PCI: dwc: Split pcie-designware.c into host and core files Kishon Vijay Abraham I <kishon@ti.com> - 2017-01-16 12:40 +0100
Re: [PATCH 11/37] PCI: dwc: Split pcie-designware.c into host and core files Joao Pinto <Joao.Pinto@synopsys.com> - 2017-01-16 14:40 +0100
[PATCH 03/37] PCI: dwc: dra7xx: Populate cpu_addr_fixup ops Kishon Vijay Abraham I <kishon@ti.com> - 2017-01-12 11:50 +0100
Page 1 of 3 [1] 2 3 Next page →
| From | Kishon Vijay Abraham I <kishon@ti.com> |
|---|---|
| Date | 2017-01-12 11:30 +0100 |
| Subject | [PATCH 00/37] PCI: Support for configurable PCI endpoint |
| Message-ID | <sYKNQ-2Nu-3@gated-at.bofh.it> |
The RFC series that was sent before this patch series can be found at [1].
The patches are split here so that it can be better reviewed.
This main purpose of this patch series is to
*) add PCI endpoint core layer
*) modifie designware/dra7xx driver to be configured in EP mode
*) add a PCI endpoint *test* function driver and corresponding host
driver
Major Improvements from RFC:
*) support multi-function devices (hw supported not virtual)
*) Access host side buffers
*) Raise MSI interrupts
*) Add user space program to use the host side PCI driver
*) Adapt all other users of designware to use the new design (only
compile tested. Since I have only dra7xx boards, the new design
has only been tested in dra7xx. I'd require the help of others
to test the platforms they have access to).
This patch series has been developed on top of 4.10-rc1, [2] & [3]
[1] -> https://lwn.net/Articles/700605/
[2] -> https://lkml.org/lkml/2016/12/28/34
[3] -> https://lkml.org/lkml/2017/1/11/238
I've also pushed the tree to
git://git.ti.com/linux-phy/linux-phy.git pci_ep_v1
Using PCI EPF Test:
ON THE EP SIDE:
***************
/* EP function is configured using configfs */
# mount -t configfs none /sys/kernel/config
/* PCI EP core layer creates "pci_ep" entry in configfs */
# cd /sys/kernel/config/pci_ep/
/*
* This is the 1st step in creating an endpoint function. This
* creates the endpoint device.
*/
# mkdir dev
/*
* dev has 2 entries. *epc* for binding a EPC device and *epf*
* is a directory containing all the functions of the endpoint
*/
# ls dev
epc epf
/*
* This creates the endpoint function device *instance*. The string
* before the .<num> suffix will identify the driver this
* EP function will bind to.
* Just pci_epf_test is also valid. The .<num> suffix is used
* if there are multiple PCI controllers and all of them wants
* to use the same function.
*/
# mkdir dev/epf/pci_epf_test.0
/*
* When the above command is given, the function device will
* also be bound to a function driver. To find the list of
* function drivers available in the system, use the following
* command. To create a new driver, the following can be referred
* drivers/pci/endpoint/functions/pci-epf-test.c
*/
# ls /sys/bus/pci-epf/drivers
pci_epf_test
/* Now configure the endpoint function */
/* These are the fields that can be configured */
# ls dev/epf/pci_epf_test.0/
baseclass_code function progif_code subsys_id
cache_line_size interrupt_pin revid subsys_vendor_id
deviceid msi_interrupts subclass_code vendorid
/* The function driver will populate these fields with default values */
# cat dev/epf/pci_epf_test.0/vendorid
0xffff
# cat dev/epf/pci_epf_test.0/interrupt_pin
0x0001
/* The user can configure any of these fields */
# echo 0x104c > dev/epf/pci_epf_test.0/vendorid
# echo 16 > dev/epf/pci_epf_test.0/msi_interrupts
/*
* Next is binding this function driver to the controller driver. In
* order to find the possible controller drivers that this function
* driver can be bound to, the following sysfs entry can be used
*/
# ls /sys/class/pci_epc/
51000000.pci
/* Now bind the function driver to the controller driver */
# echo "51000000.pcie_ep" > epc
[ 494.743487] dra7-pcie 51000000.pcie: no free inbound window
[ 494.749367] pci_epf_test pci_epf_test.0: failed to set BAR4
[ 494.755238] dra7-pcie 51000000.pcie: no free inbound window
[ 494.761451] pci_epf_test pci_epf_test.0: failed to set BAR5
/*
* the above error messages are due to non availability of free
* inbound windows. So the function drivers in dra7xx can use
* only 4 (BAR0..BAR3) BARs
*/
/****** PCI endpoint is configured ******/
ON THE HOST SIDE:
*****************
# ./pcitest.sh
BAR tests
BAR0: OKAY
BAR1: OKAY
BAR2: OKAY
BAR3: OKAY
BAR4: NOT OKAY
BAR5: NOT OKAY
Interrupt tests
LEGACY IRQ: NOT OKAY
MSI1: OKAY
MSI2: OKAY
MSI3: OKAY
MSI4: OKAY
MSI5: OKAY
MSI6: OKAY
MSI7: OKAY
MSI8: OKAY
MSI9: OKAY
MSI10: OKAY
MSI11: OKAY
MSI12: OKAY
MSI13: OKAY
MSI14: OKAY
MSI15: OKAY
MSI16: OKAY
MSI17: NOT OKAY
MSI18: NOT OKAY
MSI19: NOT OKAY
MSI20: NOT OKAY
MSI21: NOT OKAY
MSI22: NOT OKAY
MSI23: NOT OKAY
MSI24: NOT OKAY
MSI25: NOT OKAY
MSI26: NOT OKAY
MSI27: NOT OKAY
MSI28: NOT OKAY
MSI29: NOT OKAY
MSI30: NOT OKAY
MSI31: NOT OKAY
MSI32: NOT OKAY
Read Tests
READ ( 1 bytes): OKAY
READ ( 1024 bytes): OKAY
READ ( 1025 bytes): OKAY
READ (1024000 bytes): OKAY
READ (1024001 bytes): OKAY
Write Tests
WRITE ( 1 bytes): OKAY
WRITE ( 1024 bytes): OKAY
WRITE ( 1025 bytes): OKAY
WRITE (1024000 bytes): OKAY
WRITE (1024001 bytes): OKAY
Copy Tests
COPY ( 1 bytes): OKAY
COPY ( 1024 bytes): OKAY
COPY ( 1025 bytes): OKAY
COPY (1024000 bytes): OKAY
COPY (1024001 bytes): OKAY
Kishon Vijay Abraham I (37):
PCI: dwc: dra7xx: Group all host related setup in add_pcie_port
PCI: dwc: designware: Add new *ops* for cpu addr fixup
PCI: dwc: dra7xx: Populate cpu_addr_fixup ops
PCI: dwc: designware: Move the register defines to designware header
file
PCI: dwc: Add platform_set_drvdata
PCI: dwc: Rename cfg_read/cfg_write to read/write
PCI: dwc: designware: Get device pointer at the start of
dw_pcie_host_init
PCI: dwc: Split *struct pcie_port* into host only and core structures
PCI: dwc: designware: Parse *num-lanes* property in dw_pcie_setup_rc
PCI: dwc: designware: Fix style errors in pcie-designware.c
PCI: dwc: Split pcie-designware.c into host and core files
PCI: dwc: Create a new config symbol to enable pci dwc host
PCI: dwc: Remove dependency of designware to CONFIG_PCI
PCI: endpoint: Add EP core layer to enable EP controller and EP
functions
Documentation: PCI: Guide to use PCI Endpoint Core Layer
PCI: endpoint: Introduce configfs entry for configuring EP functions
Documentation: PCI: Guide to use pci endpoint configfs
Documentation: PCI: Add specification for the *pci test* function
device
PCI: endpoint: functions: Add an EP function to test PCI
Documentation: PCI: Add binding documentation for pci-test endpoint
function
PCI: dwc: Modify dbi accessors to take dbi_base as argument
PCI: dwc: Modify dbi accessors to access data of 4/2/1 bytes
PCI: dwc: Add *ops* to start and stop pcie link
PCI: dwc: designware: Add EP mode support
dt-bindings: PCI: Add dt bindings for pci designware EP mode
PCI: dwc: dra7xx: Facilitate wrapper and msi interrupts to be enabled
independently
PCI: dwc: dra7xx: Add EP mode support
dt-bindings: PCI: dra7xx: Add dt bindings for pci dra7xx EP mode
PCI: dwc: dra7xx: Workaround for errata id i870
dt-bindings: PCI: dra7xx: Add dt bindings to enable legacy mode
misc: Add host side pci driver for pci test function device
Documentation: misc-devices: Add Documentation for pci-endpoint-test
driver
tools: PCI: Add a userspace tool to test PCI endpoint
tools: PCI: Add sample test script to invoke pcitest
MAINTAINERS: add PCI EP maintainer
ARM: DRA7: clockdomain: Change the CLKTRCTRL of CM_PCIE_CLKSTCTRL to
SW_WKUP
ARM: dts: DRA7: Add pcie1 dt node for EP mode
Documentation/PCI/00-INDEX | 8 +
.../PCI/endpoint/function/binding/pci-test.txt | 17 +
Documentation/PCI/endpoint/pci-endpoint-cfs.txt | 84 ++
Documentation/PCI/endpoint/pci-endpoint.txt | 190 +++++
Documentation/PCI/endpoint/pci-test-function.txt | 66 ++
.../devicetree/bindings/pci/designware-pcie.txt | 26 +-
Documentation/devicetree/bindings/pci/ti-pci.txt | 41 +-
Documentation/misc-devices/pci-endpoint-test.txt | 35 +
MAINTAINERS | 9 +
arch/arm/boot/dts/am572x-idk.dts | 7 +-
arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi | 7 +-
arch/arm/boot/dts/dra7-evm.dts | 4 +
arch/arm/boot/dts/dra7.dtsi | 22 +-
arch/arm/boot/dts/dra72-evm-common.dtsi | 4 +
arch/arm/mach-omap2/clockdomains7xx_data.c | 2 +-
drivers/Makefile | 5 +
drivers/misc/Kconfig | 7 +
drivers/misc/Makefile | 1 +
drivers/misc/pci_endpoint_test.c | 533 ++++++++++++
drivers/pci/Kconfig | 1 +
drivers/pci/Makefile | 3 -
drivers/pci/dwc/Kconfig | 73 +-
drivers/pci/dwc/Makefile | 6 +-
drivers/pci/dwc/pci-dra7xx.c | 372 +++++++--
drivers/pci/dwc/pci-exynos.c | 83 +-
drivers/pci/dwc/pci-imx6.c | 142 ++--
drivers/pci/dwc/pci-keystone-dw.c | 91 +-
drivers/pci/dwc/pci-keystone.c | 56 +-
drivers/pci/dwc/pci-keystone.h | 4 +-
drivers/pci/dwc/pci-layerscape.c | 93 ++-
drivers/pci/dwc/pcie-armada8k.c | 92 ++-
drivers/pci/dwc/pcie-artpec6.c | 51 +-
drivers/pci/dwc/pcie-designware-ep.c | 342 ++++++++
drivers/pci/dwc/pcie-designware-host.c | 620 ++++++++++++++
drivers/pci/dwc/pcie-designware-plat.c | 29 +-
drivers/pci/dwc/pcie-designware.c | 868 ++++----------------
drivers/pci/dwc/pcie-designware.h | 254 +++++-
drivers/pci/dwc/pcie-hisi.c | 60 +-
drivers/pci/dwc/pcie-qcom.c | 72 +-
drivers/pci/dwc/pcie-spear13xx.c | 85 +-
drivers/pci/endpoint/Kconfig | 25 +
drivers/pci/endpoint/Makefile | 7 +
drivers/pci/endpoint/functions/Kconfig | 12 +
drivers/pci/endpoint/functions/Makefile | 5 +
drivers/pci/endpoint/functions/pci-epf-test.c | 513 ++++++++++++
drivers/pci/endpoint/pci-ep-cfs.c | 427 ++++++++++
drivers/pci/endpoint/pci-epc-core.c | 548 ++++++++++++
drivers/pci/endpoint/pci-epc-mem.c | 143 ++++
drivers/pci/endpoint/pci-epf-core.c | 347 ++++++++
include/linux/mod_devicetable.h | 10 +
include/linux/pci-epc.h | 141 ++++
include/linux/pci-epf.h | 160 ++++
include/uapi/linux/Kbuild | 1 +
include/uapi/linux/pcitest.h | 19 +
tools/pci/pcitest.c | 186 +++++
tools/pci/pcitest.sh | 56 ++
56 files changed, 5880 insertions(+), 1185 deletions(-)
create mode 100644 Documentation/PCI/endpoint/function/binding/pci-test.txt
create mode 100644 Documentation/PCI/endpoint/pci-endpoint-cfs.txt
create mode 100644 Documentation/PCI/endpoint/pci-endpoint.txt
create mode 100644 Documentation/PCI/endpoint/pci-test-function.txt
create mode 100644 Documentation/misc-devices/pci-endpoint-test.txt
create mode 100644 drivers/misc/pci_endpoint_test.c
create mode 100644 drivers/pci/dwc/pcie-designware-ep.c
create mode 100644 drivers/pci/dwc/pcie-designware-host.c
create mode 100644 drivers/pci/endpoint/Kconfig
create mode 100644 drivers/pci/endpoint/Makefile
create mode 100644 drivers/pci/endpoint/functions/Kconfig
create mode 100644 drivers/pci/endpoint/functions/Makefile
create mode 100644 drivers/pci/endpoint/functions/pci-epf-test.c
create mode 100644 drivers/pci/endpoint/pci-ep-cfs.c
create mode 100644 drivers/pci/endpoint/pci-epc-core.c
create mode 100644 drivers/pci/endpoint/pci-epc-mem.c
create mode 100644 drivers/pci/endpoint/pci-epf-core.c
create mode 100644 include/linux/pci-epc.h
create mode 100644 include/linux/pci-epf.h
create mode 100644 include/uapi/linux/pcitest.h
create mode 100644 tools/pci/pcitest.c
create mode 100644 tools/pci/pcitest.sh
--
1.7.9.5
[toc] | [next] | [standalone]
| From | Kishon Vijay Abraham I <kishon@ti.com> |
|---|---|
| Date | 2017-01-12 11:30 +0100 |
| Subject | [PATCH 23/37] PCI: dwc: Add *ops* to start and stop pcie link |
| Message-ID | <sYKNR-2Nu-43@gated-at.bofh.it> |
| In reply to | #1557303 |
Add start_link and stop_link ops in dw_pcie_ops to start or stop
the link. This will be used by endpoint functions to start the
link once the setup has been done.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
drivers/pci/dwc/pcie-designware.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/pci/dwc/pcie-designware.h b/drivers/pci/dwc/pcie-designware.h
index 0ef6ae7..25b3b8b 100644
--- a/drivers/pci/dwc/pcie-designware.h
+++ b/drivers/pci/dwc/pcie-designware.h
@@ -149,6 +149,8 @@ struct dw_pcie_ops {
void (*write_dbi)(struct dw_pcie *pcie, void __iomem *base, u32 reg,
int size, u32 val);
int (*link_up)(struct dw_pcie *pcie);
+ int (*start_link)(struct dw_pcie *pcie);
+ void (*stop_link)(struct dw_pcie *pcie);
};
struct dw_pcie {
--
1.7.9.5
[toc] | [prev] | [next] | [standalone]
| From | Kishon Vijay Abraham I <kishon@ti.com> |
|---|---|
| Date | 2017-01-12 11:40 +0100 |
| Subject | [PATCH 26/37] PCI: dwc: dra7xx: Facilitate wrapper and msi interrupts to be enabled independently |
| Message-ID | <sYKXv-2QD-1@gated-at.bofh.it> |
| In reply to | #1557303 |
No functional change. Split dra7xx_pcie_enable_interrupts into
dra7xx_pcie_enable_wrapper_interrupts and dra7xx_pcie_enable_msi_interrupts
so that wrapper interrupts and msi interrupts can be enabled independently.
This is in preparation for adding EP mode support to dra7xx driver since
EP mode doesn't have to enable msi_interrupts.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
drivers/pci/dwc/pci-dra7xx.c | 24 ++++++++++++++++++------
1 file changed, 18 insertions(+), 6 deletions(-)
diff --git a/drivers/pci/dwc/pci-dra7xx.c b/drivers/pci/dwc/pci-dra7xx.c
index 8a1fccd..eb3a9c6 100644
--- a/drivers/pci/dwc/pci-dra7xx.c
+++ b/drivers/pci/dwc/pci-dra7xx.c
@@ -140,18 +140,30 @@ static int dra7xx_pcie_establish_link(struct dra7xx_pcie *dra7xx)
return dw_pcie_wait_for_link(pci);
}
-static void dra7xx_pcie_enable_interrupts(struct dra7xx_pcie *dra7xx)
+static void dra7xx_pcie_enable_msi_interrupts(struct dra7xx_pcie *dra7xx)
{
- dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN,
- ~INTERRUPTS);
- dra7xx_pcie_writel(dra7xx,
- PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MAIN, INTERRUPTS);
dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI,
~LEG_EP_INTERRUPTS & ~MSI);
- dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MSI,
+
+ dra7xx_pcie_writel(dra7xx,
+ PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MSI,
MSI | LEG_EP_INTERRUPTS);
}
+static void dra7xx_pcie_enable_wrapper_interrupts(struct dra7xx_pcie *dra7xx)
+{
+ dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN,
+ ~INTERRUPTS);
+ dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MAIN,
+ INTERRUPTS);
+}
+
+static void dra7xx_pcie_enable_interrupts(struct dra7xx_pcie *dra7xx)
+{
+ dra7xx_pcie_enable_wrapper_interrupts(dra7xx);
+ dra7xx_pcie_enable_msi_interrupts(dra7xx);
+}
+
static void dra7xx_pcie_host_init(struct pcie_port *pp)
{
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
--
1.7.9.5
[toc] | [prev] | [next] | [standalone]
| From | Kishon Vijay Abraham I <kishon@ti.com> |
|---|---|
| Date | 2017-01-12 11:40 +0100 |
| Subject | [PATCH 32/37] Documentation: misc-devices: Add Documentation for pci-endpoint-test driver |
| Message-ID | <sYKXv-2QD-11@gated-at.bofh.it> |
| In reply to | #1557303 |
Add Documentation for pci-endpoint-test driver. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> --- Documentation/misc-devices/pci-endpoint-test.txt | 35 ++++++++++++++++++++++ 1 file changed, 35 insertions(+) create mode 100644 Documentation/misc-devices/pci-endpoint-test.txt diff --git a/Documentation/misc-devices/pci-endpoint-test.txt b/Documentation/misc-devices/pci-endpoint-test.txt new file mode 100644 index 0000000..4385718 --- /dev/null +++ b/Documentation/misc-devices/pci-endpoint-test.txt @@ -0,0 +1,35 @@ +Driver for PCI Endpoint Test Function + +This driver should be used as a host side driver if the root complex is +connected to a configurable pci endpoint running *pci_epf_test* function +driver configured according to [1]. + +The "pci_endpoint_test" driver can be used to perform the following tests. + +The PCI driver for the test device performs the following tests + *) verifying addresses programmed in BAR + *) raise legacy IRQ + *) raise MSI IRQ + *) read data + *) write data + *) copy data + +This misc driver creates /dev/pci-endpoint-test.<num> for every +*pci_epf_test* function connected to the root complex and "ioctls" +should be used to perform the above tests. + +ioctl +----- + PCITEST_BAR: Tests the BAR. The number of the BAR that has to be tested + should be passed as argument. + PCITEST_LEGACY_IRQ: Tests legacy IRQ + PCITEST_MSI: Tests message signalled interrupts. The MSI number that has + to be tested should be passed as argument. + PCITEST_WRITE: Perform write tests. The size of the buffer should be passed + as argument. + PCITEST_READ: Perform read tests. The size of the buffer should be passed + as argument. + PCITEST_COPY: Perform read tests. The size of the buffer should be passed + as argument. + +[1] -> Documentation/PCI/endpoint/function/binding/pci-test.txt -- 1.7.9.5
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| From | Kishon Vijay Abraham I <kishon@ti.com> |
|---|---|
| Date | 2017-01-12 11:40 +0100 |
| Subject | [PATCH 09/37] PCI: dwc: designware: Parse *num-lanes* property in dw_pcie_setup_rc |
| Message-ID | <sYKXv-2QD-3@gated-at.bofh.it> |
| In reply to | #1557303 |
*num-lanes* dt property is parsed in dw_pcie_host_init. However
*num-lanes* property is applicable to both root complex mode and
endpoint mode. As a first step, move the parsing of this property
outside dw_pcie_host_init. This is in preparation for splitting
pcie-designware.c to pcie-designware.c and pcie-designware-host.c
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
drivers/pci/dwc/pcie-designware.c | 18 +++++++++++-------
drivers/pci/dwc/pcie-designware.h | 1 -
2 files changed, 11 insertions(+), 8 deletions(-)
diff --git a/drivers/pci/dwc/pcie-designware.c b/drivers/pci/dwc/pcie-designware.c
index 00a0fdc..89cdb6b 100644
--- a/drivers/pci/dwc/pcie-designware.c
+++ b/drivers/pci/dwc/pcie-designware.c
@@ -551,10 +551,6 @@ int dw_pcie_host_init(struct pcie_port *pp)
}
}
- ret = of_property_read_u32(np, "num-lanes", &pci->lanes);
- if (ret)
- pci->lanes = 0;
-
ret = of_property_read_u32(np, "num-viewport", &pci->num_viewport);
if (ret)
pci->num_viewport = 2;
@@ -751,18 +747,26 @@ static int dw_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
void dw_pcie_setup_rc(struct pcie_port *pp)
{
+ int ret;
+ u32 lanes;
u32 val;
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
+ struct device *dev = pci->dev;
+ struct device_node *np = dev->of_node;
/* get iATU unroll support */
pci->iatu_unroll_enabled = dw_pcie_iatu_unroll_enabled(pci);
dev_dbg(pci->dev, "iATU unroll: %s\n",
pci->iatu_unroll_enabled ? "enabled" : "disabled");
+ ret = of_property_read_u32(np, "num-lanes", &lanes);
+ if (ret)
+ lanes = 0;
+
/* set the number of lanes */
val = dw_pcie_readl_dbi(pci, PCIE_PORT_LINK_CONTROL);
val &= ~PORT_LINK_MODE_MASK;
- switch (pci->lanes) {
+ switch (lanes) {
case 1:
val |= PORT_LINK_MODE_1_LANES;
break;
@@ -776,7 +780,7 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
val |= PORT_LINK_MODE_8_LANES;
break;
default:
- dev_err(pci->dev, "num-lanes %u: invalid value\n", pci->lanes);
+ dev_err(pci->dev, "num-lanes %u: invalid value\n", lanes);
return;
}
dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, val);
@@ -784,7 +788,7 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
/* set link width speed control register */
val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
val &= ~PORT_LOGIC_LINK_WIDTH_MASK;
- switch (pci->lanes) {
+ switch (lanes) {
case 1:
val |= PORT_LOGIC_LINK_WIDTH_1_LANES;
break;
diff --git a/drivers/pci/dwc/pcie-designware.h b/drivers/pci/dwc/pcie-designware.h
index d4b3d43..491fbe3 100644
--- a/drivers/pci/dwc/pcie-designware.h
+++ b/drivers/pci/dwc/pcie-designware.h
@@ -148,7 +148,6 @@ struct dw_pcie_ops {
struct dw_pcie {
struct device *dev;
void __iomem *dbi_base;
- u32 lanes;
u32 num_viewport;
u8 iatu_unroll_enabled;
struct pcie_port pp;
--
1.7.9.5
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| From | Joao Pinto <Joao.Pinto@synopsys.com> |
|---|---|
| Date | 2017-01-13 18:30 +0100 |
| Subject | Re: [PATCH 09/37] PCI: dwc: designware: Parse *num-lanes* property in dw_pcie_setup_rc |
| Message-ID | <sZdPQ-3DF-37@gated-at.bofh.it> |
| In reply to | #1557307 |
Hi,
Às 10:25 AM de 1/12/2017, Kishon Vijay Abraham I escreveu:
> *num-lanes* dt property is parsed in dw_pcie_host_init. However
> *num-lanes* property is applicable to both root complex mode and
> endpoint mode. As a first step, move the parsing of this property
> outside dw_pcie_host_init. This is in preparation for splitting
> pcie-designware.c to pcie-designware.c and pcie-designware-host.c
>
> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
> ---
> drivers/pci/dwc/pcie-designware.c | 18 +++++++++++-------
> drivers/pci/dwc/pcie-designware.h | 1 -
> 2 files changed, 11 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/pci/dwc/pcie-designware.c b/drivers/pci/dwc/pcie-designware.c
> index 00a0fdc..89cdb6b 100644
> --- a/drivers/pci/dwc/pcie-designware.c
> +++ b/drivers/pci/dwc/pcie-designware.c
> @@ -551,10 +551,6 @@ int dw_pcie_host_init(struct pcie_port *pp)
> }
> }
>
> - ret = of_property_read_u32(np, "num-lanes", &pci->lanes);
> - if (ret)
> - pci->lanes = 0;
> -
> ret = of_property_read_u32(np, "num-viewport", &pci->num_viewport);
> if (ret)
> pci->num_viewport = 2;
> @@ -751,18 +747,26 @@ static int dw_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
>
> void dw_pcie_setup_rc(struct pcie_port *pp)
> {
> + int ret;
> + u32 lanes;
> u32 val;
> struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> + struct device *dev = pci->dev;
> + struct device_node *np = dev->of_node;
>
> /* get iATU unroll support */
> pci->iatu_unroll_enabled = dw_pcie_iatu_unroll_enabled(pci);
> dev_dbg(pci->dev, "iATU unroll: %s\n",
> pci->iatu_unroll_enabled ? "enabled" : "disabled");
>
> + ret = of_property_read_u32(np, "num-lanes", &lanes);
> + if (ret)
> + lanes = 0;
You moved from host_init to root complex setup function, which in my opinion did
not improve (in this scope).
I suggest that instead of making so much intermediary patches, which is nice to
understand your development sequence, but hard to review. Wouldn't be better to
condense some of the patches? We would have a cloear vision of the final product :)
Joao
> +
> /* set the number of lanes */
> val = dw_pcie_readl_dbi(pci, PCIE_PORT_LINK_CONTROL);
> val &= ~PORT_LINK_MODE_MASK;
> - switch (pci->lanes) {
> + switch (lanes) {
> case 1:
> val |= PORT_LINK_MODE_1_LANES;
> break;
> @@ -776,7 +780,7 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
> val |= PORT_LINK_MODE_8_LANES;
> break;
> default:
> - dev_err(pci->dev, "num-lanes %u: invalid value\n", pci->lanes);
> + dev_err(pci->dev, "num-lanes %u: invalid value\n", lanes);
> return;
> }
> dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, val);
> @@ -784,7 +788,7 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
> /* set link width speed control register */
> val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
> val &= ~PORT_LOGIC_LINK_WIDTH_MASK;
> - switch (pci->lanes) {
> + switch (lanes) {
> case 1:
> val |= PORT_LOGIC_LINK_WIDTH_1_LANES;
> break;
> diff --git a/drivers/pci/dwc/pcie-designware.h b/drivers/pci/dwc/pcie-designware.h
> index d4b3d43..491fbe3 100644
> --- a/drivers/pci/dwc/pcie-designware.h
> +++ b/drivers/pci/dwc/pcie-designware.h
> @@ -148,7 +148,6 @@ struct dw_pcie_ops {
> struct dw_pcie {
> struct device *dev;
> void __iomem *dbi_base;
> - u32 lanes;
> u32 num_viewport;
> u8 iatu_unroll_enabled;
> struct pcie_port pp;
>
[toc] | [prev] | [next] | [standalone]
| From | Kishon Vijay Abraham I <kishon@ti.com> |
|---|---|
| Date | 2017-01-16 06:30 +0100 |
| Subject | Re: [PATCH 09/37] PCI: dwc: designware: Parse *num-lanes* property in dw_pcie_setup_rc |
| Message-ID | <t081I-49t-7@gated-at.bofh.it> |
| In reply to | #1558624 |
Hi,
On Friday 13 January 2017 10:43 PM, Joao Pinto wrote:
> Hi,
>
> Às 10:25 AM de 1/12/2017, Kishon Vijay Abraham I escreveu:
>> *num-lanes* dt property is parsed in dw_pcie_host_init. However
>> *num-lanes* property is applicable to both root complex mode and
>> endpoint mode. As a first step, move the parsing of this property
>> outside dw_pcie_host_init. This is in preparation for splitting
>> pcie-designware.c to pcie-designware.c and pcie-designware-host.c
>>
>> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
>> ---
>> drivers/pci/dwc/pcie-designware.c | 18 +++++++++++-------
>> drivers/pci/dwc/pcie-designware.h | 1 -
>> 2 files changed, 11 insertions(+), 8 deletions(-)
>>
>> diff --git a/drivers/pci/dwc/pcie-designware.c b/drivers/pci/dwc/pcie-designware.c
>> index 00a0fdc..89cdb6b 100644
>> --- a/drivers/pci/dwc/pcie-designware.c
>> +++ b/drivers/pci/dwc/pcie-designware.c
>> @@ -551,10 +551,6 @@ int dw_pcie_host_init(struct pcie_port *pp)
>> }
>> }
>>
>> - ret = of_property_read_u32(np, "num-lanes", &pci->lanes);
>> - if (ret)
>> - pci->lanes = 0;
>> -
>> ret = of_property_read_u32(np, "num-viewport", &pci->num_viewport);
>> if (ret)
>> pci->num_viewport = 2;
>> @@ -751,18 +747,26 @@ static int dw_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
>>
>> void dw_pcie_setup_rc(struct pcie_port *pp)
>> {
>> + int ret;
>> + u32 lanes;
>> u32 val;
>> struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>> + struct device *dev = pci->dev;
>> + struct device_node *np = dev->of_node;
>>
>> /* get iATU unroll support */
>> pci->iatu_unroll_enabled = dw_pcie_iatu_unroll_enabled(pci);
>> dev_dbg(pci->dev, "iATU unroll: %s\n",
>> pci->iatu_unroll_enabled ? "enabled" : "disabled");
>>
>> + ret = of_property_read_u32(np, "num-lanes", &lanes);
>> + if (ret)
>> + lanes = 0;
>
> You moved from host_init to root complex setup function, which in my opinion did
> not improve (in this scope).
>
> I suggest that instead of making so much intermediary patches, which is nice to
> understand your development sequence, but hard to review. Wouldn't be better to
> condense some of the patches? We would have a cloear vision of the final product :)
I thought the other way. If squashing patches is easier to review, I'll do it.
Btw, thanks for reviewing.
Cheers
Kishon
[toc] | [prev] | [next] | [standalone]
| From | Joao Pinto <Joao.Pinto@synopsys.com> |
|---|---|
| Date | 2017-01-16 11:30 +0100 |
| Subject | Re: [PATCH 09/37] PCI: dwc: designware: Parse *num-lanes* property in dw_pcie_setup_rc |
| Message-ID | <t0cI2-7wv-13@gated-at.bofh.it> |
| In reply to | #1559449 |
Hi,
Às 5:19 AM de 1/16/2017, Kishon Vijay Abraham I escreveu:
> Hi,
>
> On Friday 13 January 2017 10:43 PM, Joao Pinto wrote:
>> Hi,
>>
>> Às 10:25 AM de 1/12/2017, Kishon Vijay Abraham I escreveu:
>>> *num-lanes* dt property is parsed in dw_pcie_host_init. However
>>> *num-lanes* property is applicable to both root complex mode and
>>> endpoint mode. As a first step, move the parsing of this property
>>> outside dw_pcie_host_init. This is in preparation for splitting
>>> pcie-designware.c to pcie-designware.c and pcie-designware-host.c
>>>
>>> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
>>> ---
>>> drivers/pci/dwc/pcie-designware.c | 18 +++++++++++-------
>>> drivers/pci/dwc/pcie-designware.h | 1 -
>>> 2 files changed, 11 insertions(+), 8 deletions(-)
>>>
>>> diff --git a/drivers/pci/dwc/pcie-designware.c b/drivers/pci/dwc/pcie-designware.c
>>> index 00a0fdc..89cdb6b 100644
>>> --- a/drivers/pci/dwc/pcie-designware.c
>>> +++ b/drivers/pci/dwc/pcie-designware.c
>>> @@ -551,10 +551,6 @@ int dw_pcie_host_init(struct pcie_port *pp)
>>> }
>>> }
>>>
>>> - ret = of_property_read_u32(np, "num-lanes", &pci->lanes);
>>> - if (ret)
>>> - pci->lanes = 0;
>>> -
>>> ret = of_property_read_u32(np, "num-viewport", &pci->num_viewport);
>>> if (ret)
>>> pci->num_viewport = 2;
>>> @@ -751,18 +747,26 @@ static int dw_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
>>>
>>> void dw_pcie_setup_rc(struct pcie_port *pp)
>>> {
>>> + int ret;
>>> + u32 lanes;
>>> u32 val;
>>> struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>>> + struct device *dev = pci->dev;
>>> + struct device_node *np = dev->of_node;
>>>
>>> /* get iATU unroll support */
>>> pci->iatu_unroll_enabled = dw_pcie_iatu_unroll_enabled(pci);
>>> dev_dbg(pci->dev, "iATU unroll: %s\n",
>>> pci->iatu_unroll_enabled ? "enabled" : "disabled");
>>>
>>> + ret = of_property_read_u32(np, "num-lanes", &lanes);
>>> + if (ret)
>>> + lanes = 0;
>>
>> You moved from host_init to root complex setup function, which in my opinion did
>> not improve (in this scope).
>>
>> I suggest that instead of making so much intermediary patches, which is nice to
>> understand your development sequence, but hard to review. Wouldn't be better to
>> condense some of the patches? We would have a cloear vision of the final product :)
>
> I thought the other way. If squashing patches is easier to review, I'll do it.
I understand. To break it in small pieces is good to understand clearly what is
done and how was done, but I would break too much. That's a personal opinion of
course, lets see what others say :).
Thanks,
Joao
>
> Btw, thanks for reviewing.
>
> Cheers
> Kishon
>
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| From | Kishon Vijay Abraham I <kishon@ti.com> |
|---|---|
| Date | 2017-01-12 11:40 +0100 |
| Subject | [PATCH 29/37] PCI: dwc: dra7xx: Workaround for errata id i870 |
| Message-ID | <sYKXv-2QD-5@gated-at.bofh.it> |
| In reply to | #1557303 |
According to errata i870, access to the PCIe slave port
that are not 32-bit aligned will result in incorrect mapping
to TLP Address and Byte enable fields.
Accessing non 32-bit aligned data causes incorrect data in the target
buffer if memcpy is used. Implement the workaround for this
errata here.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
drivers/pci/dwc/pci-dra7xx.c | 50 ++++++++++++++++++++++++++++++++++++++++++
1 file changed, 50 insertions(+)
diff --git a/drivers/pci/dwc/pci-dra7xx.c b/drivers/pci/dwc/pci-dra7xx.c
index 333aa56..7666e3e 100644
--- a/drivers/pci/dwc/pci-dra7xx.c
+++ b/drivers/pci/dwc/pci-dra7xx.c
@@ -26,6 +26,8 @@
#include <linux/pm_runtime.h>
#include <linux/resource.h>
#include <linux/types.h>
+#include <linux/mfd/syscon.h>
+#include <linux/regmap.h>
#include "pcie-designware.h"
@@ -531,6 +533,48 @@ static int dra7xx_pcie_enable_phy(struct dra7xx_pcie *dra7xx)
{},
};
+/*
+ * dra7xx_pcie_ep_legacy_mode: workaround for AM572x/AM571x Errata i870
+ * @dra7xx: the dra7xx device where the workaround should be applied
+ *
+ * Access to the PCIe slave port that are not 32-bit aligned will result
+ * in incorrect mapping to TLP Address and Byte enable fields. Therefore,
+ * byte and half-word accesses are not possible to byte offset 0x1, 0x2, or
+ * 0x3.
+ *
+ * To avoid this issue set PCIE_SS1_AXI2OCP_LEGACY_MODE_ENABLE to 1.
+ */
+static int dra7xx_pcie_ep_legacy_mode(struct device *dev)
+{
+ int ret;
+ struct device_node *np = dev->of_node;
+ struct regmap *regmap;
+ unsigned int reg;
+ unsigned int field;
+
+ regmap = syscon_regmap_lookup_by_phandle(np, "syscon-legacy-mode");
+ if (IS_ERR(regmap)) {
+ dev_dbg(dev, "can't get syscon-legacy-mode\n");
+ return -EINVAL;
+ }
+
+ if (of_property_read_u32_index(np, "syscon-legacy-mode", 1, ®)) {
+ dev_err(dev, "couldn't get legacy mode register offset\n");
+ return -EINVAL;
+ }
+
+ if (of_property_read_u32_index(np, "syscon-legacy-mode", 2, &field)) {
+ dev_err(dev, "can't get bit field for setting legacy mode\n");
+ return -EINVAL;
+ }
+
+ ret = regmap_update_bits(regmap, reg, field, field);
+ if (ret)
+ dev_err(dev, "failed to set legacy mode\n");
+
+ return ret;
+}
+
static int __init dra7xx_pcie_probe(struct platform_device *pdev)
{
u32 reg;
@@ -643,6 +687,7 @@ static int __init dra7xx_pcie_probe(struct platform_device *pdev)
case DW_PCIE_RC_TYPE:
dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_DEVICE_TYPE,
DEVICE_TYPE_RC);
+
ret = dra7xx_add_pcie_port(dra7xx, pdev);
if (ret < 0)
goto err_gpio;
@@ -650,6 +695,11 @@ static int __init dra7xx_pcie_probe(struct platform_device *pdev)
case DW_PCIE_EP_TYPE:
dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_DEVICE_TYPE,
DEVICE_TYPE_EP);
+
+ ret = dra7xx_pcie_ep_legacy_mode(dev);
+ if (ret)
+ goto err_gpio;
+
ret = dra7xx_add_pcie_ep(dra7xx, pdev);
if (ret < 0)
goto err_gpio;
--
1.7.9.5
[toc] | [prev] | [next] | [standalone]
| From | Kishon Vijay Abraham I <kishon@ti.com> |
|---|---|
| Date | 2017-01-12 11:40 +0100 |
| Subject | [PATCH 07/37] PCI: dwc: designware: Get device pointer at the start of dw_pcie_host_init |
| Message-ID | <sYKXv-2QD-9@gated-at.bofh.it> |
| In reply to | #1557303 |
No functional change. Get device pointer at the beginning of
dw_pcie_host_init instead of getting it all over dw_pcie_host_init.
This is in preparation for splitting struct pcie_port into host and
core structures (Once split pcie_port will not have device pointer).
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
drivers/pci/dwc/pcie-designware.c | 33 +++++++++++++++++----------------
1 file changed, 17 insertions(+), 16 deletions(-)
diff --git a/drivers/pci/dwc/pcie-designware.c b/drivers/pci/dwc/pcie-designware.c
index d0ea310..330596b 100644
--- a/drivers/pci/dwc/pcie-designware.c
+++ b/drivers/pci/dwc/pcie-designware.c
@@ -449,8 +449,9 @@ static u8 dw_pcie_iatu_unroll_enabled(struct pcie_port *pp)
int dw_pcie_host_init(struct pcie_port *pp)
{
- struct device_node *np = pp->dev->of_node;
- struct platform_device *pdev = to_platform_device(pp->dev);
+ struct device *dev = pp->dev;
+ struct device_node *np = dev->of_node;
+ struct platform_device *pdev = to_platform_device(dev);
struct pci_bus *bus, *child;
struct resource *cfg_res;
int i, ret;
@@ -464,14 +465,14 @@ int dw_pcie_host_init(struct pcie_port *pp)
pp->cfg0_base = cfg_res->start;
pp->cfg1_base = cfg_res->start + pp->cfg0_size;
} else if (!pp->va_cfg0_base) {
- dev_err(pp->dev, "missing *config* reg space\n");
+ dev_err(dev, "missing *config* reg space\n");
}
ret = of_pci_get_host_bridge_resources(np, 0, 0xff, &res, &pp->io_base);
if (ret)
return ret;
- ret = devm_request_pci_bus_resources(&pdev->dev, &res);
+ ret = devm_request_pci_bus_resources(dev, &res);
if (ret)
goto error;
@@ -481,7 +482,7 @@ int dw_pcie_host_init(struct pcie_port *pp)
case IORESOURCE_IO:
ret = pci_remap_iospace(win->res, pp->io_base);
if (ret) {
- dev_warn(pp->dev, "error %d: failed to map resource %pR\n",
+ dev_warn(dev, "error %d: failed to map resource %pR\n",
ret, win->res);
resource_list_destroy_entry(win);
} else {
@@ -511,10 +512,10 @@ int dw_pcie_host_init(struct pcie_port *pp)
}
if (!pp->dbi_base) {
- pp->dbi_base = devm_ioremap(pp->dev, pp->cfg->start,
+ pp->dbi_base = devm_ioremap(dev, pp->cfg->start,
resource_size(pp->cfg));
if (!pp->dbi_base) {
- dev_err(pp->dev, "error with ioremap\n");
+ dev_err(dev, "error with ioremap\n");
ret = -ENOMEM;
goto error;
}
@@ -523,20 +524,20 @@ int dw_pcie_host_init(struct pcie_port *pp)
pp->mem_base = pp->mem->start;
if (!pp->va_cfg0_base) {
- pp->va_cfg0_base = devm_ioremap(pp->dev, pp->cfg0_base,
+ pp->va_cfg0_base = devm_ioremap(dev, pp->cfg0_base,
pp->cfg0_size);
if (!pp->va_cfg0_base) {
- dev_err(pp->dev, "error with ioremap in function\n");
+ dev_err(dev, "error with ioremap in function\n");
ret = -ENOMEM;
goto error;
}
}
if (!pp->va_cfg1_base) {
- pp->va_cfg1_base = devm_ioremap(pp->dev, pp->cfg1_base,
+ pp->va_cfg1_base = devm_ioremap(dev, pp->cfg1_base,
pp->cfg1_size);
if (!pp->va_cfg1_base) {
- dev_err(pp->dev, "error with ioremap\n");
+ dev_err(dev, "error with ioremap\n");
ret = -ENOMEM;
goto error;
}
@@ -552,11 +553,11 @@ int dw_pcie_host_init(struct pcie_port *pp)
if (IS_ENABLED(CONFIG_PCI_MSI)) {
if (!pp->ops->msi_host_init) {
- pp->irq_domain = irq_domain_add_linear(pp->dev->of_node,
+ pp->irq_domain = irq_domain_add_linear(dev->of_node,
MAX_MSI_IRQS, &msi_domain_ops,
&dw_pcie_msi_chip);
if (!pp->irq_domain) {
- dev_err(pp->dev, "irq domain init failed\n");
+ dev_err(dev, "irq domain init failed\n");
ret = -ENXIO;
goto error;
}
@@ -575,12 +576,12 @@ int dw_pcie_host_init(struct pcie_port *pp)
pp->root_bus_nr = pp->busn->start;
if (IS_ENABLED(CONFIG_PCI_MSI)) {
- bus = pci_scan_root_bus_msi(pp->dev, pp->root_bus_nr,
+ bus = pci_scan_root_bus_msi(dev, pp->root_bus_nr,
&dw_pcie_ops, pp, &res,
&dw_pcie_msi_chip);
- dw_pcie_msi_chip.dev = pp->dev;
+ dw_pcie_msi_chip.dev = dev;
} else
- bus = pci_scan_root_bus(pp->dev, pp->root_bus_nr, &dw_pcie_ops,
+ bus = pci_scan_root_bus(dev, pp->root_bus_nr, &dw_pcie_ops,
pp, &res);
if (!bus) {
ret = -ENOMEM;
--
1.7.9.5
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| From | Joao Pinto <Joao.Pinto@synopsys.com> |
|---|---|
| Date | 2017-01-13 18:30 +0100 |
| Subject | Re: [PATCH 07/37] PCI: dwc: designware: Get device pointer at the start of dw_pcie_host_init |
| Message-ID | <sZdPR-3DF-45@gated-at.bofh.it> |
| In reply to | #1557309 |
Hi! Às 10:25 AM de 1/12/2017, Kishon Vijay Abraham I escreveu: > No functional change. Get device pointer at the beginning of > dw_pcie_host_init instead of getting it all over dw_pcie_host_init. > This is in preparation for splitting struct pcie_port into host and > core structures (Once split pcie_port will not have device pointer). > I think change should be condense with another patch to reduce the patch-set number and to give it real meaning. I understand why you are breaking so much the patch, it is has a lot of changes, but in my opinion is too much fragmented. Thanks Joao
[toc] | [prev] | [next] | [standalone]
| From | Kishon Vijay Abraham I <kishon@ti.com> |
|---|---|
| Date | 2017-01-12 11:40 +0100 |
| Subject | [PATCH 20/37] Documentation: PCI: Add binding documentation for pci-test endpoint function |
| Message-ID | <sYKXw-2QD-25@gated-at.bofh.it> |
| In reply to | #1557303 |
Add binding documentation for pci-test endpoint function that helps in adding and configuring pci-test endpoint function. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> --- Documentation/PCI/00-INDEX | 2 ++ .../PCI/endpoint/function/binding/pci-test.txt | 17 +++++++++++++++++ 2 files changed, 19 insertions(+) create mode 100644 Documentation/PCI/endpoint/function/binding/pci-test.txt diff --git a/Documentation/PCI/00-INDEX b/Documentation/PCI/00-INDEX index 4e5a283..53717b7 100644 --- a/Documentation/PCI/00-INDEX +++ b/Documentation/PCI/00-INDEX @@ -18,3 +18,5 @@ endpoint/pci-endpoint-cfs.txt - guide to use configfs to configure the pci endpoint function. endpoint/pci-test-function.txt - specification of *pci test* function device. +endpoint/function/binding/ + - binding documentation for pci endpoint function diff --git a/Documentation/PCI/endpoint/function/binding/pci-test.txt b/Documentation/PCI/endpoint/function/binding/pci-test.txt new file mode 100644 index 0000000..7358240 --- /dev/null +++ b/Documentation/PCI/endpoint/function/binding/pci-test.txt @@ -0,0 +1,17 @@ +PCI TEST ENDPOINT FUNCTION + +name: Should be "pci_epf_test" to bind to the pci_epf_test driver. + +Configurable Fields: +vendorid : should be 0x104c +deviceid : should be 0xffff +revid : dont't care +progif_code : don't care +subclass_code : don't care +baseclass_code : should be 0xff +cache_line_size : don't care +subsys_vendor_id : don't care +subsys_id : don't care +interrupt_pin : Should be 1 - INTA, 2 - INTB, 3 - INTC, 4 -INTD +msi_interrupts : Should be 1 to 32 depending on the number of msi interrupts + to test -- 1.7.9.5
[toc] | [prev] | [next] | [standalone]
| From | Kishon Vijay Abraham I <kishon@ti.com> |
|---|---|
| Date | 2017-01-12 11:40 +0100 |
| Subject | [PATCH 33/37] tools: PCI: Add a userspace tool to test PCI endpoint |
| Message-ID | <sYKXv-2QD-13@gated-at.bofh.it> |
| In reply to | #1557303 |
Add a userspace tool to invoke the ioctls exposed by the
PCI endpoint test driver to perform various PCI tests.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
tools/pci/pcitest.c | 186 +++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 186 insertions(+)
create mode 100644 tools/pci/pcitest.c
diff --git a/tools/pci/pcitest.c b/tools/pci/pcitest.c
new file mode 100644
index 0000000..39b5b0b
--- /dev/null
+++ b/tools/pci/pcitest.c
@@ -0,0 +1,186 @@
+/**
+ * Userspace PCI Endpoint Test Module
+ *
+ * Copyright (C) 2017 Texas Instruments
+ * Author: Kishon Vijay Abraham I <kishon@ti.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 of
+ * the License as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <errno.h>
+#include <fcntl.h>
+#include <stdbool.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <sys/ioctl.h>
+#include <time.h>
+#include <unistd.h>
+
+#include <linux/pcitest.h>
+
+#define BILLION 1E9
+
+static char *result[] = { "NOT OKAY", "OKAY" };
+
+struct pci_test {
+ char *device;
+ char barnum;
+ bool legacyirq;
+ unsigned int msinum;
+ bool read;
+ bool write;
+ bool copy;
+ unsigned long size;
+};
+
+static int run_test(struct pci_test *test)
+{
+ long ret;
+ int fd;
+ struct timespec start, end;
+ double time;
+
+ fd = open(test->device, O_RDWR);
+ if (fd < 0) {
+ perror("can't open PCI Endpoint Test device");
+ return fd;
+ }
+
+ if (test->barnum >= 0 && test->barnum <= 5) {
+ ret = ioctl(fd, PCITEST_BAR, test->barnum);
+ fprintf(stdout, "BAR%d:\t\t", test->barnum);
+ if (ret < 0)
+ fprintf(stdout, "TEST FAILED\n");
+ else
+ fprintf(stdout, "%s\n", result[ret]);
+ }
+
+ if (test->legacyirq) {
+ ret = ioctl(fd, PCITEST_LEGACY_IRQ, 0);
+ fprintf(stdout, "LEGACY IRQ:\t");
+ if (ret < 0)
+ fprintf(stdout, "TEST FAILED\n");
+ else
+ fprintf(stdout, "%s\n", result[ret]);
+ }
+
+ if (test->msinum > 0 && test->msinum <= 32) {
+ ret = ioctl(fd, PCITEST_MSI, test->msinum);
+ fprintf(stdout, "MSI%d:\t\t", test->msinum);
+ if (ret < 0)
+ fprintf(stdout, "TEST FAILED\n");
+ else
+ fprintf(stdout, "%s\n", result[ret]);
+ }
+
+ if (test->write) {
+ ret = ioctl(fd, PCITEST_WRITE, test->size);
+ fprintf(stdout, "WRITE (%7ld bytes):\t\t", test->size);
+ if (ret < 0)
+ fprintf(stdout, "TEST FAILED\n");
+ else
+ fprintf(stdout, "%s\n", result[ret]);
+ }
+
+ if (test->read) {
+ ret = ioctl(fd, PCITEST_READ, test->size);
+ fprintf(stdout, "READ (%7ld bytes):\t\t", test->size);
+ if (ret < 0)
+ fprintf(stdout, "TEST FAILED\n");
+ else
+ fprintf(stdout, "%s\n", result[ret]);
+ }
+
+ if (test->copy) {
+ ret = ioctl(fd, PCITEST_COPY, test->size);
+ fprintf(stdout, "COPY (%7ld bytes):\t\t", test->size);
+ if (ret < 0)
+ fprintf(stdout, "TEST FAILED\n");
+ else
+ fprintf(stdout, "%s\n", result[ret]);
+ }
+
+ fflush(stdout);
+}
+
+int main(int argc, char **argv)
+{
+ int c;
+ struct pci_test *test;
+
+ test = calloc(1, sizeof(*test));
+ if (!test) {
+ perror("Fail to allocate memory for pci_test\n");
+ return -ENOMEM;
+ }
+
+ /* since '0' is a valid BAR number, initialize it to -1 */
+ test->barnum = -1;
+
+ /* set default size as 100KB */
+ test->size = 0x19000;
+
+ /* set default endpoint device */
+ test->device = "/dev/pci-endpoint-test.0";
+
+ while ((c = getopt(argc, argv, "D:b:m:lrwcs:")) != EOF)
+ switch (c) {
+ case 'D':
+ test->device = optarg;
+ continue;
+ case 'b':
+ test->barnum = atoi(optarg);
+ if (test->barnum < 0 || test->barnum > 5)
+ goto usage;
+ continue;
+ case 'l':
+ test->legacyirq = true;
+ continue;
+ case 'm':
+ test->msinum = atoi(optarg);
+ if (test->msinum < 1 || test->msinum > 32)
+ goto usage;
+ continue;
+ case 'r':
+ test->read = true;
+ continue;
+ case 'w':
+ test->write = true;
+ continue;
+ case 'c':
+ test->copy = true;
+ continue;
+ case 's':
+ test->size = strtoul(optarg, NULL, 0);
+ continue;
+ case '?':
+ case 'h':
+ default:
+usage:
+ fprintf(stderr,
+ "usage: %s [options]\n"
+ "Options:\n"
+ "\t-D <dev> pci endpoint test device {default: /dev/pci-endpoint-test.0}\n"
+ "\t-b <bar num> BAR test (bar number between 0..5)\n"
+ "\t-m <msi num> MSI test (msi number between 1..32)\n"
+ "\t-r Read buffer test\n"
+ "\t-w Write buffer test\n"
+ "\t-c Copy buffer test\n"
+ "\t-s <size> Size of buffer {default: 100KB}\n",
+ argv[0]);
+ return -EINVAL;
+ }
+
+ run_test(test);
+ return 0;
+}
--
1.7.9.5
[toc] | [prev] | [next] | [standalone]
| From | Kishon Vijay Abraham I <kishon@ti.com> |
|---|---|
| Date | 2017-01-12 11:40 +0100 |
| Subject | [PATCH 35/37] MAINTAINERS: add PCI EP maintainer |
| Message-ID | <sYKXv-2QD-17@gated-at.bofh.it> |
| In reply to | #1557303 |
Add maintainer for the newly introduced PCI EP framework. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> --- MAINTAINERS | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 8672f18..021f676 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -9407,6 +9407,15 @@ F: include/linux/pci* F: arch/x86/pci/ F: arch/x86/kernel/quirks.c +PCI EP SUBSYSTEM +M: Kishon Vijay Abraham I <kishon@ti.com> +L: linux-pci@vger.kernel.org +T: git git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git +S: Supported +F: drivers/pci/endpoint/ +F: drivers/misc/pci_endpoint_test.c +F: tools/pci/ + PCI DRIVER FOR ALTERA PCIE IP M: Ley Foon Tan <lftan@altera.com> L: rfi@lists.rocketboards.org (moderated for non-subscribers) -- 1.7.9.5
[toc] | [prev] | [next] | [standalone]
| From | Kishon Vijay Abraham I <kishon@ti.com> |
|---|---|
| Date | 2017-01-12 11:40 +0100 |
| Subject | [PATCH 37/37] ARM: dts: DRA7: Add pcie1 dt node for EP mode |
| Message-ID | <sYKXw-2QD-21@gated-at.bofh.it> |
| In reply to | #1557303 |
Add pcie1 dt node in order for the controller to operate in
endpoint mode. However since none of the dra7 based boards have
slots configured to operate in endpoint mode, keep EP mode
disabled.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
arch/arm/boot/dts/am572x-idk.dts | 7 ++++++-
arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi | 7 ++++++-
arch/arm/boot/dts/dra7-evm.dts | 4 ++++
arch/arm/boot/dts/dra7.dtsi | 22 +++++++++++++++++++++-
arch/arm/boot/dts/dra72-evm-common.dtsi | 4 ++++
5 files changed, 41 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/am572x-idk.dts b/arch/arm/boot/dts/am572x-idk.dts
index 1540f7a..2ca2839 100644
--- a/arch/arm/boot/dts/am572x-idk.dts
+++ b/arch/arm/boot/dts/am572x-idk.dts
@@ -88,6 +88,11 @@
load-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
};
-&pcie1 {
+&pcie1_rc {
+ status = "okay";
+ gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>;
+};
+
+&pcie1_ep {
gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>;
};
diff --git a/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi b/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi
index 78bee26..079a7e1 100644
--- a/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi
+++ b/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi
@@ -556,7 +556,12 @@
};
};
-&pcie1 {
+&pcie1_rc {
+ status = "ok";
+ gpios = <&gpio2 8 GPIO_ACTIVE_LOW>;
+};
+
+&pcie1_ep {
gpios = <&gpio2 8 GPIO_ACTIVE_LOW>;
};
diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
index 132f2be..fd0aa3a 100644
--- a/arch/arm/boot/dts/dra7-evm.dts
+++ b/arch/arm/boot/dts/dra7-evm.dts
@@ -937,3 +937,7 @@
status = "okay";
};
};
+
+&pcie1_rc {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index addb753..bf9c668 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -272,7 +272,11 @@
#address-cells = <1>;
ranges = <0x51000000 0x51000000 0x3000
0x0 0x20000000 0x10000000>;
- pcie1: pcie@51000000 {
+ /**
+ * To enable PCI endpoint mode, disable the pcie1_rc
+ * node and enable pcie1_ep mode.
+ */
+ pcie1_rc: pcie@51000000 {
compatible = "ti,dra7-pcie";
reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>;
reg-names = "rc_dbics", "ti_conf", "config";
@@ -293,12 +297,28 @@
<0 0 0 2 &pcie1_intc 2>,
<0 0 0 3 &pcie1_intc 3>,
<0 0 0 4 &pcie1_intc 4>;
+ status = "disabled";
pcie1_intc: interrupt-controller {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
};
};
+
+ pcie1_ep: pcie_ep@51000000 {
+ compatible = "ti,dra7-pcie-ep";
+ reg = <0x51000000 0x28>, <0x51002000 0x14c>, <0x51001000 0x28>, <0x1000 0x10000000>;
+ reg-names = "ep_dbics", "ti_conf", "ep_dbics2", "addr_space";
+ interrupts = <0 232 0x4>;
+ num-lanes = <1>;
+ num-ib-windows = <4>;
+ num-ob-windows = <16>;
+ ti,hwmods = "pcie1";
+ phys = <&pcie1_phy>;
+ phy-names = "pcie-phy0";
+ syscon-legacy-mode = <&scm_conf1 0x14 2>;
+ status = "disabled";
+ };
};
axi@1 {
diff --git a/arch/arm/boot/dts/dra72-evm-common.dtsi b/arch/arm/boot/dts/dra72-evm-common.dtsi
index e50fbee..5d9762c 100644
--- a/arch/arm/boot/dts/dra72-evm-common.dtsi
+++ b/arch/arm/boot/dts/dra72-evm-common.dtsi
@@ -545,3 +545,7 @@
status = "okay";
};
};
+
+&pcie1_rc {
+ status = "okay";
+};
--
1.7.9.5
[toc] | [prev] | [next] | [standalone]
| From | Kishon Vijay Abraham I <kishon@ti.com> |
|---|---|
| Date | 2017-01-12 11:40 +0100 |
| Subject | [PATCH 30/37] dt-bindings: PCI: dra7xx: Add dt bindings to enable legacy mode |
| Message-ID | <sYKXw-2QD-27@gated-at.bofh.it> |
| In reply to | #1557303 |
Update device tree binding documentation of TI's dra7xx PCI controller to include property for enabling legacy mode. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> --- Documentation/devicetree/bindings/pci/ti-pci.txt | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/ti-pci.txt b/Documentation/devicetree/bindings/pci/ti-pci.txt index 62f5f59..ed85e8e 100644 --- a/Documentation/devicetree/bindings/pci/ti-pci.txt +++ b/Documentation/devicetree/bindings/pci/ti-pci.txt @@ -39,6 +39,10 @@ DEVICE MODE - interrupts : one interrupt entries must be specified for main interrupt. - num-ib-windows : number of inbound address translation windows - num-ob-windows : number of outbound address translation windows + - syscon-legacy-mode: phandle to the syscon dt node. The 1st argument should + contain the register offset within syscon and the 2nd + argument should contain the bit field for setting the + legacy mode Optional Property: - gpios : Should be added if a gpio line is required to drive PERST# line -- 1.7.9.5
[toc] | [prev] | [next] | [standalone]
| From | Kishon Vijay Abraham I <kishon@ti.com> |
|---|---|
| Date | 2017-01-12 11:40 +0100 |
| Subject | [PATCH 17/37] Documentation: PCI: Guide to use pci endpoint configfs |
| Message-ID | <sYKXw-2QD-19@gated-at.bofh.it> |
| In reply to | #1557303 |
Add Documentation to help users use pci endpoint to configure pci endpoint function and to bind the endpoint function with endpoint controller. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> --- Documentation/PCI/00-INDEX | 2 + Documentation/PCI/endpoint/pci-endpoint-cfs.txt | 84 +++++++++++++++++++++++ 2 files changed, 86 insertions(+) create mode 100644 Documentation/PCI/endpoint/pci-endpoint-cfs.txt diff --git a/Documentation/PCI/00-INDEX b/Documentation/PCI/00-INDEX index ba950b2..f84a23c 100644 --- a/Documentation/PCI/00-INDEX +++ b/Documentation/PCI/00-INDEX @@ -14,3 +14,5 @@ pcieaer-howto.txt - the PCI Express Advanced Error Reporting Driver Guide HOWTO endpoint/pci-endpoint.txt - guide to add endpoint controller driver and endpoint function driver. +endpoint/pci-endpoint-cfs.txt + - guide to use configfs to configure the pci endpoint function. diff --git a/Documentation/PCI/endpoint/pci-endpoint-cfs.txt b/Documentation/PCI/endpoint/pci-endpoint-cfs.txt new file mode 100644 index 0000000..b1f1613 --- /dev/null +++ b/Documentation/PCI/endpoint/pci-endpoint-cfs.txt @@ -0,0 +1,84 @@ + CONFIGURING PCI ENDPOINT USING CONFIGFS + Kishon Vijay Abraham I <kishon@ti.com> + +The PCI Endpoint Core exposes configfs entry (pci_ep) in order to configure the +PCI endpoint function and in order to bind the endpoint function +with the endpoint controller. (For introducing other mechanisms to +configure the PCI Endpoint Function refer [1]). + +*) Mounting configfs + +The PCI Endpoint Core layer creates pci_ep directory in the mounted configfs +directory. configfs can be mounted using the following command. + + mount -t configfs none /sys/kernel/config + +*) Directory Structure + +The pci_ep configfs directory structure has been created to reflect the +natural tree like structure of PCI devices. So every directory created +inside pci_ep represents a EPC device and every directory created inside +epf directory represents EPF device. + +/sys/kernel/config/pci_ep/ + | <dir>/ --------------------------------------> [2] + | epc + | epf/ + | <dir>/ --------------------------> [3] + | vendorid + | deviceid + | revid + | progif_code + | subclass_code + | baseclass_code + | cache_line_size + | subsys_vendor_id + | subsys_id + | interrupt_pin + | function + +*) Creating configfs entry for EPC + +Any directory created inside *pci_ep* represents an EPC device. In the above +directory structure [2] represents an EPC device. It consists of + + *) epc: Use it to associate the configfs entry to an actual EPC device. + The list of valid entries for this field can be obtained from + ls /sys/class/pci_epc/ + + *) epf: Directory that contains all the endpoint functions. The name + of the created directory determines the driver this particular + epf device will be bound to. The name can be obtained either + from the function binding documentation [4] or + ls /sys/bus/pci-epf/drivers + + If more than one endpoint function device has to be bound to + the same driver, then the directory should be created using + the following notation + mkdir <name>.<num> + +*) Creating configfs entry for EPF + +Any directory created inside *epf* directory represents an EPF device. In the +above directory structure, [3] represents an EPF device. It consists of the +following entries that can be used to configure the standard configuration +header of the endpoint function. (These entries are created by the +framework when any new directory is created inside epf directory.) + + | vendorid + | deviceid + | revid + | progif_code + | subclass_code + | baseclass_code + | cache_line_size + | subsys_vendor_id + | subsys_id + | interrupt_pin + +The following entry identifies the function driver that is bound to the +function device + | function + +[1] -> Documentation/PCI/endpoint/pci-endpoint.txt +[4] -> Documentation/PCI/endpoint/function/binding/ -- 1.7.9.5
[toc] | [prev] | [next] | [standalone]
| From | Kishon Vijay Abraham I <kishon@ti.com> |
|---|---|
| Date | 2017-01-12 11:40 +0100 |
| Subject | [PATCH 34/37] tools: PCI: Add sample test script to invoke pcitest |
| Message-ID | <sYKXw-2QD-31@gated-at.bofh.it> |
| In reply to | #1557303 |
Add a simple test script that invokes the pcitest userspace tool to perform all the PCI endpoint tests (BAR tests, interrupt tests, read tests, write tests and copy tests). Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> --- tools/pci/pcitest.sh | 56 ++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 56 insertions(+) create mode 100644 tools/pci/pcitest.sh diff --git a/tools/pci/pcitest.sh b/tools/pci/pcitest.sh new file mode 100644 index 0000000..5442bbe --- /dev/null +++ b/tools/pci/pcitest.sh @@ -0,0 +1,56 @@ +#!/bin/sh + +echo "BAR tests" +echo + +bar=0 + +while [ $bar -lt 6 ] +do + pcitest -b $bar + bar=`expr $bar + 1` +done +echo + +echo "Interrupt tests" +echo + +pcitest -l +msi=1 + +while [ $msi -lt 33 ] +do + pcitest -m $msi + msi=`expr $msi + 1` +done +echo + +echo "Read Tests" +echo + +pcitest -r -s 1 +pcitest -r -s 1024 +pcitest -r -s 1025 +pcitest -r -s 1024000 +pcitest -r -s 1024001 +echo + +echo "Write Tests" +echo + +pcitest -w -s 1 +pcitest -w -s 1024 +pcitest -w -s 1025 +pcitest -w -s 1024000 +pcitest -w -s 1024001 +echo + +echo "Copy Tests" +echo + +pcitest -c -s 1 +pcitest -c -s 1024 +pcitest -c -s 1025 +pcitest -c -s 1024000 +pcitest -c -s 1024001 +echo -- 1.7.9.5
[toc] | [prev] | [next] | [standalone]
| From | Kishon Vijay Abraham I <kishon@ti.com> |
|---|---|
| Date | 2017-01-12 11:40 +0100 |
| Subject | [PATCH 22/37] PCI: dwc: Modify dbi accessors to access data of 4/2/1 bytes |
| Message-ID | <sYKXw-2QD-23@gated-at.bofh.it> |
| In reply to | #1557303 |
Previously dbi accessors can be used to access data of size 4
bytes. But there might be situations (like accessing
MSI_MESSAGE_CONTROL in order to set/get the number of required
MSI interrupts in EP mode) where dbi accessors must
be used to access data of size 2. This is in preparation for
adding endpoint mode support to designware driver.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
drivers/pci/dwc/pci-dra7xx.c | 8 ++--
drivers/pci/dwc/pci-exynos.c | 16 +++----
drivers/pci/dwc/pci-imx6.c | 58 +++++++++++------------
drivers/pci/dwc/pci-keystone-dw.c | 13 +++---
drivers/pci/dwc/pcie-armada8k.c | 38 +++++++--------
drivers/pci/dwc/pcie-artpec6.c | 6 +--
drivers/pci/dwc/pcie-designware-host.c | 16 +++----
drivers/pci/dwc/pcie-designware.c | 79 +++++++++++++++++++-------------
drivers/pci/dwc/pcie-designware.h | 14 +++---
drivers/pci/dwc/pcie-hisi.c | 14 +++---
10 files changed, 140 insertions(+), 122 deletions(-)
diff --git a/drivers/pci/dwc/pci-dra7xx.c b/drivers/pci/dwc/pci-dra7xx.c
index 76d0b40..8a1fccd 100644
--- a/drivers/pci/dwc/pci-dra7xx.c
+++ b/drivers/pci/dwc/pci-dra7xx.c
@@ -498,9 +498,9 @@ static int dra7xx_pcie_suspend(struct device *dev)
u32 val;
/* clear MSE */
- val = dw_pcie_readl_dbi(pci, base, PCI_COMMAND);
+ val = dw_pcie_read_dbi(pci, base, PCI_COMMAND, 0x4);
val &= ~PCI_COMMAND_MEMORY;
- dw_pcie_writel_dbi(pci, base, PCI_COMMAND, val);
+ dw_pcie_write_dbi(pci, base, PCI_COMMAND, 0x4, val);
return 0;
}
@@ -513,9 +513,9 @@ static int dra7xx_pcie_resume(struct device *dev)
u32 val;
/* set MSE */
- val = dw_pcie_readl_dbi(pci, base, PCI_COMMAND);
+ val = dw_pcie_read_dbi(pci, base, PCI_COMMAND, 0x4);
val |= PCI_COMMAND_MEMORY;
- dw_pcie_writel_dbi(pci, base, PCI_COMMAND, val);
+ dw_pcie_write_dbi(pci, base, PCI_COMMAND, 0x4, val);
return 0;
}
diff --git a/drivers/pci/dwc/pci-exynos.c b/drivers/pci/dwc/pci-exynos.c
index a109cf0..f6beb05 100644
--- a/drivers/pci/dwc/pci-exynos.c
+++ b/drivers/pci/dwc/pci-exynos.c
@@ -405,25 +405,25 @@ static void exynos_pcie_enable_interrupts(struct exynos_pcie *exynos_pcie)
exynos_pcie_msi_init(exynos_pcie);
}
-static u32 exynos_pcie_readl_dbi(struct dw_pcie *pci, void __iomem *base,
- u32 reg)
+static u32 exynos_pcie_read_dbi(struct dw_pcie *pci, void __iomem *base,
+ u32 reg, int size)
{
struct exynos_pcie *exynos_pcie = to_exynos_pcie(pci);
u32 val;
exynos_pcie_sideband_dbi_r_mode(exynos_pcie, true);
- val = readl(base + reg);
+ dw_pcie_read(base + reg, size, &val);
exynos_pcie_sideband_dbi_r_mode(exynos_pcie, false);
return val;
}
-static void exynos_pcie_writel_dbi(struct dw_pcie *pci, void __iomem *base,
- u32 reg, u32 val)
+static void exynos_pcie_write_dbi(struct dw_pcie *pci, void __iomem *base,
+ u32 reg, int size, u32 val)
{
struct exynos_pcie *exynos_pcie = to_exynos_pcie(pci);
exynos_pcie_sideband_dbi_w_mode(exynos_pcie, true);
- writel(val, base + reg);
+ dw_pcie_write(base + reg, size, val);
exynos_pcie_sideband_dbi_w_mode(exynos_pcie, false);
}
@@ -530,8 +530,8 @@ static int __init exynos_add_pcie_port(struct exynos_pcie *exynos_pcie,
}
static const struct dw_pcie_ops dw_pcie_ops = {
- .readl_dbi = exynos_pcie_readl_dbi,
- .writel_dbi = exynos_pcie_writel_dbi,
+ .read_dbi = exynos_pcie_read_dbi,
+ .write_dbi = exynos_pcie_write_dbi,
.link_up = exynos_pcie_link_up,
};
diff --git a/drivers/pci/dwc/pci-imx6.c b/drivers/pci/dwc/pci-imx6.c
index ecc8690..08ebe62 100644
--- a/drivers/pci/dwc/pci-imx6.c
+++ b/drivers/pci/dwc/pci-imx6.c
@@ -104,7 +104,7 @@ static int pcie_phy_poll_ack(struct imx6_pcie *imx6_pcie, int exp_val)
u32 wait_counter = 0;
do {
- val = dw_pcie_readl_dbi(pci, base, PCIE_PHY_STAT);
+ val = dw_pcie_read_dbi(pci, base, PCIE_PHY_STAT, 0x4);
val = (val >> PCIE_PHY_STAT_ACK_LOC) & 0x1;
wait_counter++;
@@ -125,17 +125,17 @@ static int pcie_phy_wait_ack(struct imx6_pcie *imx6_pcie, int addr)
int ret;
val = addr << PCIE_PHY_CTRL_DATA_LOC;
- dw_pcie_writel_dbi(pci, base, PCIE_PHY_CTRL, val);
+ dw_pcie_write_dbi(pci, base, PCIE_PHY_CTRL, 0x4, val);
val |= (0x1 << PCIE_PHY_CTRL_CAP_ADR_LOC);
- dw_pcie_writel_dbi(pci, base, PCIE_PHY_CTRL, val);
+ dw_pcie_write_dbi(pci, base, PCIE_PHY_CTRL, 0x4, val);
ret = pcie_phy_poll_ack(imx6_pcie, 1);
if (ret)
return ret;
val = addr << PCIE_PHY_CTRL_DATA_LOC;
- dw_pcie_writel_dbi(pci, base, PCIE_PHY_CTRL, val);
+ dw_pcie_write_dbi(pci, base, PCIE_PHY_CTRL, 0x4, val);
return pcie_phy_poll_ack(imx6_pcie, 0);
}
@@ -154,17 +154,17 @@ static int pcie_phy_read(struct imx6_pcie *imx6_pcie, int addr, int *data)
/* assert Read signal */
phy_ctl = 0x1 << PCIE_PHY_CTRL_RD_LOC;
- dw_pcie_writel_dbi(pci, base, PCIE_PHY_CTRL, phy_ctl);
+ dw_pcie_write_dbi(pci, base, PCIE_PHY_CTRL, 0x4, phy_ctl);
ret = pcie_phy_poll_ack(imx6_pcie, 1);
if (ret)
return ret;
- val = dw_pcie_readl_dbi(pci, base, PCIE_PHY_STAT);
+ val = dw_pcie_read_dbi(pci, base, PCIE_PHY_STAT, 0x4);
*data = val & 0xffff;
/* deassert Read signal */
- dw_pcie_writel_dbi(pci, base, PCIE_PHY_CTRL, 0x00);
+ dw_pcie_write_dbi(pci, base, PCIE_PHY_CTRL, 0x4, 0x00);
return pcie_phy_poll_ack(imx6_pcie, 0);
}
@@ -183,11 +183,11 @@ static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, int data)
return ret;
var = data << PCIE_PHY_CTRL_DATA_LOC;
- dw_pcie_writel_dbi(pci, base, PCIE_PHY_CTRL, var);
+ dw_pcie_write_dbi(pci, base, PCIE_PHY_CTRL, 0x4, var);
/* capture data */
var |= (0x1 << PCIE_PHY_CTRL_CAP_DAT_LOC);
- dw_pcie_writel_dbi(pci, base, PCIE_PHY_CTRL, var);
+ dw_pcie_write_dbi(pci, base, PCIE_PHY_CTRL, 0x4, var);
ret = pcie_phy_poll_ack(imx6_pcie, 1);
if (ret)
@@ -195,7 +195,7 @@ static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, int data)
/* deassert cap data */
var = data << PCIE_PHY_CTRL_DATA_LOC;
- dw_pcie_writel_dbi(pci, base, PCIE_PHY_CTRL, var);
+ dw_pcie_write_dbi(pci, base, PCIE_PHY_CTRL, 0x4, var);
/* wait for ack de-assertion */
ret = pcie_phy_poll_ack(imx6_pcie, 0);
@@ -204,7 +204,7 @@ static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, int data)
/* assert wr signal */
var = 0x1 << PCIE_PHY_CTRL_WR_LOC;
- dw_pcie_writel_dbi(pci, base, PCIE_PHY_CTRL, var);
+ dw_pcie_write_dbi(pci, base, PCIE_PHY_CTRL, 0x4, var);
/* wait for ack */
ret = pcie_phy_poll_ack(imx6_pcie, 1);
@@ -213,14 +213,14 @@ static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, int data)
/* deassert wr signal */
var = data << PCIE_PHY_CTRL_DATA_LOC;
- dw_pcie_writel_dbi(pci, base, PCIE_PHY_CTRL, var);
+ dw_pcie_write_dbi(pci, base, PCIE_PHY_CTRL, 0x4, var);
/* wait for ack de-assertion */
ret = pcie_phy_poll_ack(imx6_pcie, 0);
if (ret)
return ret;
- dw_pcie_writel_dbi(pci, base, PCIE_PHY_CTRL, 0x0);
+ dw_pcie_write_dbi(pci, base, PCIE_PHY_CTRL, 0x4, 0x0);
return 0;
}
@@ -289,10 +289,10 @@ static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie)
if ((gpr1 & IMX6Q_GPR1_PCIE_REF_CLK_EN) &&
(gpr12 & IMX6Q_GPR12_PCIE_CTL_2)) {
- val = dw_pcie_readl_dbi(pci, base, PCIE_PL_PFLR);
+ val = dw_pcie_read_dbi(pci, base, PCIE_PL_PFLR, 0x4);
val &= ~PCIE_PL_PFLR_LINK_STATE_MASK;
val |= PCIE_PL_PFLR_FORCE_LINK;
- dw_pcie_writel_dbi(pci, base, PCIE_PL_PFLR, val);
+ dw_pcie_write_dbi(pci, base, PCIE_PL_PFLR, 0x4, val);
regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
IMX6Q_GPR12_PCIE_CTL_2, 0 << 10);
@@ -454,8 +454,8 @@ static int imx6_pcie_wait_for_link(struct imx6_pcie *imx6_pcie)
return 0;
dev_dbg(dev, "DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n",
- dw_pcie_readl_dbi(pci, base, PCIE_PHY_DEBUG_R0),
- dw_pcie_readl_dbi(pci, base, PCIE_PHY_DEBUG_R1));
+ dw_pcie_read_dbi(pci, base, PCIE_PHY_DEBUG_R0, 0x4),
+ dw_pcie_read_dbi(pci, base, PCIE_PHY_DEBUG_R1, 0x4));
return -ETIMEDOUT;
}
@@ -468,8 +468,8 @@ static int imx6_pcie_wait_for_speed_change(struct imx6_pcie *imx6_pcie)
unsigned int retries;
for (retries = 0; retries < 200; retries++) {
- tmp = dw_pcie_readl_dbi(pci, base,
- PCIE_LINK_WIDTH_SPEED_CONTROL);
+ tmp = dw_pcie_read_dbi(pci, base,
+ PCIE_LINK_WIDTH_SPEED_CONTROL, 0x4);
/* Test if the speed change finished. */
if (!(tmp & PORT_LOGIC_SPEED_CHANGE))
return 0;
@@ -502,10 +502,10 @@ static int imx6_pcie_establish_link(struct imx6_pcie *imx6_pcie)
* started in Gen2 mode, there is a possibility the devices on the
* bus will not be detected at all. This happens with PCIe switches.
*/
- tmp = dw_pcie_readl_dbi(pci, base, PCIE_RC_LCR);
+ tmp = dw_pcie_read_dbi(pci, base, PCIE_RC_LCR, 0x4);
tmp &= ~PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK;
tmp |= PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN1;
- dw_pcie_writel_dbi(pci, base, PCIE_RC_LCR, tmp);
+ dw_pcie_write_dbi(pci, base, PCIE_RC_LCR, 0x4, tmp);
/* Start LTSSM. */
regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
@@ -519,10 +519,10 @@ static int imx6_pcie_establish_link(struct imx6_pcie *imx6_pcie)
if (imx6_pcie->link_gen == 2) {
/* Allow Gen2 mode after the link is up. */
- tmp = dw_pcie_readl_dbi(pci, base, PCIE_RC_LCR);
+ tmp = dw_pcie_read_dbi(pci, base, PCIE_RC_LCR, 0x4);
tmp &= ~PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK;
tmp |= PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN2;
- dw_pcie_writel_dbi(pci, base, PCIE_RC_LCR, tmp);
+ dw_pcie_write_dbi(pci, base, PCIE_RC_LCR, 0x4, tmp);
} else {
dev_info(dev, "Link: Gen2 disabled\n");
}
@@ -531,9 +531,9 @@ static int imx6_pcie_establish_link(struct imx6_pcie *imx6_pcie)
* Start Directed Speed Change so the best possible speed both link
* partners support can be negotiated.
*/
- tmp = dw_pcie_readl_dbi(pci, base, PCIE_LINK_WIDTH_SPEED_CONTROL);
+ tmp = dw_pcie_read_dbi(pci, base, PCIE_LINK_WIDTH_SPEED_CONTROL, 0x4);
tmp |= PORT_LOGIC_SPEED_CHANGE;
- dw_pcie_writel_dbi(pci, base, PCIE_LINK_WIDTH_SPEED_CONTROL, tmp);
+ dw_pcie_write_dbi(pci, base, PCIE_LINK_WIDTH_SPEED_CONTROL, 0x4, tmp);
ret = imx6_pcie_wait_for_speed_change(imx6_pcie);
if (ret) {
@@ -548,14 +548,14 @@ static int imx6_pcie_establish_link(struct imx6_pcie *imx6_pcie)
goto err_reset_phy;
}
- tmp = dw_pcie_readl_dbi(pci, base, PCIE_RC_LCSR);
+ tmp = dw_pcie_read_dbi(pci, base, PCIE_RC_LCSR, 0x4);
dev_info(dev, "Link up, Gen%i\n", (tmp >> 16) & 0xf);
return 0;
err_reset_phy:
dev_dbg(dev, "PHY DEBUG_R0=0x%08x DEBUG_R1=0x%08x\n",
- dw_pcie_readl_dbi(pci, base, PCIE_PHY_DEBUG_R0),
- dw_pcie_readl_dbi(pci, base, PCIE_PHY_DEBUG_R1));
+ dw_pcie_read_dbi(pci, base, PCIE_PHY_DEBUG_R0, 0x4),
+ dw_pcie_read_dbi(pci, base, PCIE_PHY_DEBUG_R1, 0x4));
imx6_pcie_reset_phy(imx6_pcie);
return ret;
}
@@ -579,7 +579,7 @@ static int imx6_pcie_link_up(struct dw_pcie *pci)
{
void __iomem *base = pci->dbi_base;
- return dw_pcie_readl_dbi(pci, base, PCIE_PHY_DEBUG_R1) &
+ return dw_pcie_read_dbi(pci, base, PCIE_PHY_DEBUG_R1, 0x4) &
PCIE_PHY_DEBUG_R1_XMLH_LINK_UP;
}
diff --git a/drivers/pci/dwc/pci-keystone-dw.c b/drivers/pci/dwc/pci-keystone-dw.c
index 7220c04..8318efe 100644
--- a/drivers/pci/dwc/pci-keystone-dw.c
+++ b/drivers/pci/dwc/pci-keystone-dw.c
@@ -386,8 +386,8 @@ void ks_dw_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie)
/* Disable BARs for inbound access */
ks_dw_pcie_set_dbi_mode(ks_pcie);
- dw_pcie_writel_dbi(pci, base, PCI_BASE_ADDRESS_0, 0);
- dw_pcie_writel_dbi(pci, base, PCI_BASE_ADDRESS_1, 0);
+ dw_pcie_write_dbi(pci, base, PCI_BASE_ADDRESS_0, 0x4, 0);
+ dw_pcie_write_dbi(pci, base, PCI_BASE_ADDRESS_1, 0x4, 0);
ks_dw_pcie_clear_dbi_mode(ks_pcie);
/* Set outbound translation size per window division */
@@ -490,8 +490,8 @@ void ks_dw_pcie_v3_65_scan_bus(struct pcie_port *pp)
ks_dw_pcie_set_dbi_mode(ks_pcie);
/* Enable BAR0 */
- dw_pcie_writel_dbi(pci, base, PCI_BASE_ADDRESS_0, 1);
- dw_pcie_writel_dbi(pci, base, PCI_BASE_ADDRESS_0, SZ_4K - 1);
+ dw_pcie_write_dbi(pci, base, PCI_BASE_ADDRESS_0, 0x4, 1);
+ dw_pcie_write_dbi(pci, base, PCI_BASE_ADDRESS_0, 0x4, SZ_4K - 1);
ks_dw_pcie_clear_dbi_mode(ks_pcie);
@@ -499,7 +499,8 @@ void ks_dw_pcie_v3_65_scan_bus(struct pcie_port *pp)
* For BAR0, just setting bus address for inbound writes (MSI) should
* be sufficient. Use physical address to avoid any conflicts.
*/
- dw_pcie_writel_dbi(pci, base, PCI_BASE_ADDRESS_0, ks_pcie->app.start);
+ dw_pcie_write_dbi(pci, base, PCI_BASE_ADDRESS_0, 0x4,
+ ks_pcie->app.start);
}
/**
@@ -510,7 +511,7 @@ int ks_dw_pcie_link_up(struct dw_pcie *pci)
u32 val;
void __iomem *base = pci->dbi_base;
- val = dw_pcie_readl_dbi(pci, base, DEBUG0);
+ val = dw_pcie_read_dbi(pci, base, DEBUG0, 0x4);
return (val & LTSSM_STATE_MASK) == LTSSM_STATE_L0;
}
diff --git a/drivers/pci/dwc/pcie-armada8k.c b/drivers/pci/dwc/pcie-armada8k.c
index 2656f86..6067749 100644
--- a/drivers/pci/dwc/pcie-armada8k.c
+++ b/drivers/pci/dwc/pcie-armada8k.c
@@ -75,7 +75,7 @@ static int armada8k_pcie_link_up(struct dw_pcie *pci)
u32 mask = PCIE_GLB_STS_RDLH_LINK_UP | PCIE_GLB_STS_PHY_LINK_UP;
void __iomem *base = pci->dbi_base;
- reg = dw_pcie_readl_dbi(pci, base, PCIE_GLOBAL_STATUS_REG);
+ reg = dw_pcie_read_dbi(pci, base, PCIE_GLOBAL_STATUS_REG, 0x4);
if ((reg & mask) == mask)
return 1;
@@ -92,45 +92,45 @@ static void armada8k_pcie_establish_link(struct armada8k_pcie *pcie)
if (!dw_pcie_link_up(pci)) {
/* Disable LTSSM state machine to enable configuration */
- reg = dw_pcie_readl_dbi(pci, base, PCIE_GLOBAL_CONTROL_REG);
+ reg = dw_pcie_read_dbi(pci, base, PCIE_GLOBAL_CONTROL_REG, 0x4);
reg &= ~(PCIE_APP_LTSSM_EN);
- dw_pcie_writel_dbi(pci, base, PCIE_GLOBAL_CONTROL_REG, reg);
+ dw_pcie_write_dbi(pci, base, PCIE_GLOBAL_CONTROL_REG, 0x4, reg);
}
/* Set the device to root complex mode */
- reg = dw_pcie_readl_dbi(pci, base, PCIE_GLOBAL_CONTROL_REG);
+ reg = dw_pcie_read_dbi(pci, base, PCIE_GLOBAL_CONTROL_REG, 0x4);
reg &= ~(PCIE_DEVICE_TYPE_MASK << PCIE_DEVICE_TYPE_SHIFT);
reg |= PCIE_DEVICE_TYPE_RC << PCIE_DEVICE_TYPE_SHIFT;
- dw_pcie_writel_dbi(pci, base, PCIE_GLOBAL_CONTROL_REG, reg);
+ dw_pcie_write_dbi(pci, base, PCIE_GLOBAL_CONTROL_REG, 0x4, reg);
/* Set the PCIe master AxCache attributes */
- dw_pcie_writel_dbi(pci, base, PCIE_ARCACHE_TRC_REG,
- ARCACHE_DEFAULT_VALUE);
- dw_pcie_writel_dbi(pci, base, PCIE_AWCACHE_TRC_REG,
- AWCACHE_DEFAULT_VALUE);
+ dw_pcie_write_dbi(pci, base, PCIE_ARCACHE_TRC_REG, 0x4,
+ ARCACHE_DEFAULT_VALUE);
+ dw_pcie_write_dbi(pci, base, PCIE_AWCACHE_TRC_REG, 0x4,
+ AWCACHE_DEFAULT_VALUE);
/* Set the PCIe master AxDomain attributes */
- reg = dw_pcie_readl_dbi(pci, base, PCIE_ARUSER_REG);
+ reg = dw_pcie_read_dbi(pci, base, PCIE_ARUSER_REG, 0x4);
reg &= ~(AX_USER_DOMAIN_MASK << AX_USER_DOMAIN_SHIFT);
reg |= DOMAIN_OUTER_SHAREABLE << AX_USER_DOMAIN_SHIFT;
- dw_pcie_writel_dbi(pci, base, PCIE_ARUSER_REG, reg);
+ dw_pcie_write_dbi(pci, base, PCIE_ARUSER_REG, 0x4, reg);
- reg = dw_pcie_readl_dbi(pci, base, PCIE_AWUSER_REG);
+ reg = dw_pcie_read_dbi(pci, base, PCIE_AWUSER_REG, 0x4);
reg &= ~(AX_USER_DOMAIN_MASK << AX_USER_DOMAIN_SHIFT);
reg |= DOMAIN_OUTER_SHAREABLE << AX_USER_DOMAIN_SHIFT;
- dw_pcie_writel_dbi(pci, base, PCIE_AWUSER_REG, reg);
+ dw_pcie_write_dbi(pci, base, PCIE_AWUSER_REG, 0x4, reg);
/* Enable INT A-D interrupts */
- reg = dw_pcie_readl_dbi(pci, base, PCIE_GLOBAL_INT_MASK1_REG);
+ reg = dw_pcie_read_dbi(pci, base, PCIE_GLOBAL_INT_MASK1_REG, 0x4);
reg |= PCIE_INT_A_ASSERT_MASK | PCIE_INT_B_ASSERT_MASK |
PCIE_INT_C_ASSERT_MASK | PCIE_INT_D_ASSERT_MASK;
- dw_pcie_writel_dbi(pci, base, PCIE_GLOBAL_INT_MASK1_REG, reg);
+ dw_pcie_write_dbi(pci, base, PCIE_GLOBAL_INT_MASK1_REG, 0x4, reg);
if (!dw_pcie_link_up(pci)) {
/* Configuration done. Start LTSSM */
- reg = dw_pcie_readl_dbi(pci, base, PCIE_GLOBAL_CONTROL_REG);
+ reg = dw_pcie_read_dbi(pci, base, PCIE_GLOBAL_CONTROL_REG, 0x4);
reg |= PCIE_APP_LTSSM_EN;
- dw_pcie_writel_dbi(pci, base, PCIE_GLOBAL_CONTROL_REG, reg);
+ dw_pcie_write_dbi(pci, base, PCIE_GLOBAL_CONTROL_REG, 0x4, reg);
}
/* Wait until the link becomes active again */
@@ -159,8 +159,8 @@ static irqreturn_t armada8k_pcie_irq_handler(int irq, void *arg)
* PCI device. However, they are also latched into the PCIe
* controller, so we simply discard them.
*/
- val = dw_pcie_readl_dbi(pci, base, PCIE_GLOBAL_INT_CAUSE1_REG);
- dw_pcie_writel_dbi(pci, base, PCIE_GLOBAL_INT_CAUSE1_REG, val);
+ val = dw_pcie_read_dbi(pci, base, PCIE_GLOBAL_INT_CAUSE1_REG, 0x4);
+ dw_pcie_write_dbi(pci, base, PCIE_GLOBAL_INT_CAUSE1_REG, 0x4, val);
return IRQ_HANDLED;
}
diff --git a/drivers/pci/dwc/pcie-artpec6.c b/drivers/pci/dwc/pcie-artpec6.c
index 4c7820a..a00b703 100644
--- a/drivers/pci/dwc/pcie-artpec6.c
+++ b/drivers/pci/dwc/pcie-artpec6.c
@@ -141,7 +141,7 @@ static int artpec6_pcie_establish_link(struct artpec6_pcie *artpec6_pcie)
* Enable writing to config regs. This is required as the Synopsys
* driver changes the class code. That register needs DBI write enable.
*/
- dw_pcie_writel_dbi(pci, base, MISC_CONTROL_1_OFF, DBI_RO_WR_EN);
+ dw_pcie_write_dbi(pci, base, MISC_CONTROL_1_OFF, 0x4, DBI_RO_WR_EN);
pp->io_base &= ARTPEC6_CPU_TO_BUS_ADDR;
pp->mem_base &= ARTPEC6_CPU_TO_BUS_ADDR;
@@ -161,8 +161,8 @@ static int artpec6_pcie_establish_link(struct artpec6_pcie *artpec6_pcie)
return 0;
dev_dbg(pci->dev, "DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n",
- dw_pcie_readl_dbi(pci, base, PCIE_PHY_DEBUG_R0),
- dw_pcie_readl_dbi(pci, base, PCIE_PHY_DEBUG_R1));
+ dw_pcie_read_dbi(pci, base, PCIE_PHY_DEBUG_R0, 0x4),
+ dw_pcie_read_dbi(pci, base, PCIE_PHY_DEBUG_R1, 0x4));
return -ETIMEDOUT;
}
diff --git a/drivers/pci/dwc/pcie-designware-host.c b/drivers/pci/dwc/pcie-designware-host.c
index e3a5104..044fcda 100644
--- a/drivers/pci/dwc/pcie-designware-host.c
+++ b/drivers/pci/dwc/pcie-designware-host.c
@@ -572,27 +572,27 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
dw_pcie_setup(pci);
/* setup RC BARs */
- dw_pcie_writel_dbi(pci, base, PCI_BASE_ADDRESS_0, 0x00000004);
- dw_pcie_writel_dbi(pci, base, PCI_BASE_ADDRESS_1, 0x00000000);
+ dw_pcie_write_dbi(pci, base, PCI_BASE_ADDRESS_0, 0x4, 0x00000004);
+ dw_pcie_write_dbi(pci, base, PCI_BASE_ADDRESS_1, 0x4, 0x00000000);
/* setup interrupt pins */
- val = dw_pcie_readl_dbi(pci, base, PCI_INTERRUPT_LINE);
+ val = dw_pcie_read_dbi(pci, base, PCI_INTERRUPT_LINE, 0x4);
val &= 0xffff00ff;
val |= 0x00000100;
- dw_pcie_writel_dbi(pci, base, PCI_INTERRUPT_LINE, val);
+ dw_pcie_write_dbi(pci, base, PCI_INTERRUPT_LINE, 0x4, val);
/* setup bus numbers */
- val = dw_pcie_readl_dbi(pci, base, PCI_PRIMARY_BUS);
+ val = dw_pcie_read_dbi(pci, base, PCI_PRIMARY_BUS, 0x4);
val &= 0xff000000;
val |= 0x00010100;
- dw_pcie_writel_dbi(pci, base, PCI_PRIMARY_BUS, val);
+ dw_pcie_write_dbi(pci, base, PCI_PRIMARY_BUS, 0x4, val);
/* setup command register */
- val = dw_pcie_readl_dbi(pci, base, PCI_COMMAND);
+ val = dw_pcie_read_dbi(pci, base, PCI_COMMAND, 0x4);
val &= 0xffff0000;
val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
PCI_COMMAND_MASTER | PCI_COMMAND_SERR;
- dw_pcie_writel_dbi(pci, base, PCI_COMMAND, val);
+ dw_pcie_write_dbi(pci, base, PCI_COMMAND, 0x4, val);
/*
* If the platform provides ->rd_other_conf, it means the platform
diff --git a/drivers/pci/dwc/pcie-designware.c b/drivers/pci/dwc/pcie-designware.c
index db39f13..ef545e7 100644
--- a/drivers/pci/dwc/pcie-designware.c
+++ b/drivers/pci/dwc/pcie-designware.c
@@ -61,21 +61,35 @@ int dw_pcie_write(void __iomem *addr, int size, u32 val)
return PCIBIOS_SUCCESSFUL;
}
-u32 dw_pcie_readl_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg)
+u32 dw_pcie_read_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg,
+ int size)
{
- if (pci->ops->readl_dbi)
- return pci->ops->readl_dbi(pci, base, reg);
+ int ret;
+ u32 val;
+
+ if (pci->ops->read_dbi)
+ return pci->ops->read_dbi(pci, base, reg, size);
- return readl(base + reg);
+ ret = dw_pcie_read(base + reg, size, &val);
+ if (ret)
+ dev_err(pci->dev, "read DBI address failed\n");
+
+ return val;
}
-void dw_pcie_writel_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg,
- u32 val)
+void dw_pcie_write_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg,
+ int size, u32 val)
{
- if (pci->ops->writel_dbi)
- pci->ops->writel_dbi(pci, base, reg, val);
- else
- writel(val, base + reg);
+ int ret;
+
+ if (pci->ops->write_dbi) {
+ pci->ops->write_dbi(pci, base, reg, size, val);
+ return;
+ }
+
+ ret = dw_pcie_write(base + reg, size, val);
+ if (ret)
+ dev_err(pci->dev, "write DBI address failed\n");
}
static u32 dw_pcie_readl_unroll(struct dw_pcie *pci, void __iomem *base,
@@ -83,7 +97,7 @@ static u32 dw_pcie_readl_unroll(struct dw_pcie *pci, void __iomem *base,
{
u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index);
- return dw_pcie_readl_dbi(pci, base, offset + reg);
+ return dw_pcie_read_dbi(pci, base, offset + reg, 0x4);
}
static void dw_pcie_writel_unroll(struct dw_pcie *pci, void __iomem *base,
@@ -91,7 +105,7 @@ static void dw_pcie_writel_unroll(struct dw_pcie *pci, void __iomem *base,
{
u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index);
- dw_pcie_writel_dbi(pci, base, offset + reg, val);
+ dw_pcie_write_dbi(pci, base, offset + reg, 0x4, val);
}
void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type,
@@ -122,20 +136,21 @@ void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type,
PCIE_ATU_UNR_REGION_CTRL2,
PCIE_ATU_ENABLE);
} else {
- dw_pcie_writel_dbi(pci, base, PCIE_ATU_VIEWPORT,
- PCIE_ATU_REGION_OUTBOUND | index);
- dw_pcie_writel_dbi(pci, base, PCIE_ATU_LOWER_BASE,
- lower_32_bits(cpu_addr));
- dw_pcie_writel_dbi(pci, base, PCIE_ATU_UPPER_BASE,
- upper_32_bits(cpu_addr));
- dw_pcie_writel_dbi(pci, base, PCIE_ATU_LIMIT,
- lower_32_bits(cpu_addr + size - 1));
- dw_pcie_writel_dbi(pci, base, PCIE_ATU_LOWER_TARGET,
- lower_32_bits(pci_addr));
- dw_pcie_writel_dbi(pci, base, PCIE_ATU_UPPER_TARGET,
- upper_32_bits(pci_addr));
- dw_pcie_writel_dbi(pci, base, PCIE_ATU_CR1, type);
- dw_pcie_writel_dbi(pci, base, PCIE_ATU_CR2, PCIE_ATU_ENABLE);
+ dw_pcie_write_dbi(pci, base, PCIE_ATU_VIEWPORT, 0x4,
+ PCIE_ATU_REGION_OUTBOUND | index);
+ dw_pcie_write_dbi(pci, base, PCIE_ATU_LOWER_BASE, 0x4,
+ lower_32_bits(cpu_addr));
+ dw_pcie_write_dbi(pci, base, PCIE_ATU_UPPER_BASE, 0x4,
+ upper_32_bits(cpu_addr));
+ dw_pcie_write_dbi(pci, base, PCIE_ATU_LIMIT, 0x4,
+ lower_32_bits(cpu_addr + size - 1));
+ dw_pcie_write_dbi(pci, base, PCIE_ATU_LOWER_TARGET, 0x4,
+ lower_32_bits(pci_addr));
+ dw_pcie_write_dbi(pci, base, PCIE_ATU_UPPER_TARGET, 0x4,
+ upper_32_bits(pci_addr));
+ dw_pcie_write_dbi(pci, base, PCIE_ATU_CR1, 0x4, type);
+ dw_pcie_write_dbi(pci, base, PCIE_ATU_CR2, 0x4,
+ PCIE_ATU_ENABLE);
}
/*
@@ -147,7 +162,7 @@ void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type,
val = dw_pcie_readl_unroll(pci, base, index,
PCIE_ATU_UNR_REGION_CTRL2);
else
- val = dw_pcie_readl_dbi(pci, base, PCIE_ATU_CR2);
+ val = dw_pcie_read_dbi(pci, base, PCIE_ATU_CR2, 0x4);
if (val == PCIE_ATU_ENABLE)
return;
@@ -192,7 +207,7 @@ static u8 dw_pcie_iatu_unroll_enabled(struct dw_pcie *pci)
u32 val;
void __iomem *base = pci->dbi_base;
- val = dw_pcie_readl_dbi(pci, base, PCIE_ATU_VIEWPORT);
+ val = dw_pcie_read_dbi(pci, base, PCIE_ATU_VIEWPORT, 0x4);
if (val == 0xffffffff)
return 1;
@@ -218,7 +233,7 @@ void dw_pcie_setup(struct dw_pcie *pci)
lanes = 0;
/* set the number of lanes */
- val = dw_pcie_readl_dbi(pci, base, PCIE_PORT_LINK_CONTROL);
+ val = dw_pcie_read_dbi(pci, base, PCIE_PORT_LINK_CONTROL, 0x4);
val &= ~PORT_LINK_MODE_MASK;
switch (lanes) {
case 1:
@@ -237,10 +252,10 @@ void dw_pcie_setup(struct dw_pcie *pci)
dev_err(pci->dev, "num-lanes %u: invalid value\n", lanes);
return;
}
- dw_pcie_writel_dbi(pci, base, PCIE_PORT_LINK_CONTROL, val);
+ dw_pcie_write_dbi(pci, base, PCIE_PORT_LINK_CONTROL, 0x4, val);
/* set link width speed control register */
- val = dw_pcie_readl_dbi(pci, base, PCIE_LINK_WIDTH_SPEED_CONTROL);
+ val = dw_pcie_read_dbi(pci, base, PCIE_LINK_WIDTH_SPEED_CONTROL, 0x4);
val &= ~PORT_LOGIC_LINK_WIDTH_MASK;
switch (lanes) {
case 1:
@@ -256,5 +271,5 @@ void dw_pcie_setup(struct dw_pcie *pci)
val |= PORT_LOGIC_LINK_WIDTH_8_LANES;
break;
}
- dw_pcie_writel_dbi(pci, base, PCIE_LINK_WIDTH_SPEED_CONTROL, val);
+ dw_pcie_write_dbi(pci, base, PCIE_LINK_WIDTH_SPEED_CONTROL, 0x4, val);
}
diff --git a/drivers/pci/dwc/pcie-designware.h b/drivers/pci/dwc/pcie-designware.h
index fe93f7f..0ef6ae7 100644
--- a/drivers/pci/dwc/pcie-designware.h
+++ b/drivers/pci/dwc/pcie-designware.h
@@ -144,9 +144,10 @@ struct pcie_port {
struct dw_pcie_ops {
u64 (*cpu_addr_fixup)(u64 cpu_addr);
- u32 (*readl_dbi)(struct dw_pcie *pcie, void __iomem *base, u32 reg);
- void (*writel_dbi)(struct dw_pcie *pcie, void __iomem *base, u32 reg,
- u32 val);
+ u32 (*read_dbi)(struct dw_pcie *pcie, void __iomem *base, u32 reg,
+ int size);
+ void (*write_dbi)(struct dw_pcie *pcie, void __iomem *base, u32 reg,
+ int size, u32 val);
int (*link_up)(struct dw_pcie *pcie);
};
@@ -164,9 +165,10 @@ struct dw_pcie {
int dw_pcie_read(void __iomem *addr, int size, u32 *val);
int dw_pcie_write(void __iomem *addr, int size, u32 val);
-u32 dw_pcie_readl_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg);
-void dw_pcie_writel_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg,
- u32 val);
+u32 dw_pcie_read_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg,
+ int size);
+void dw_pcie_write_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg,
+ int size, u32 val);
int dw_pcie_link_up(struct dw_pcie *pci);
int dw_pcie_wait_for_link(struct dw_pcie *pci);
void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index,
diff --git a/drivers/pci/dwc/pcie-hisi.c b/drivers/pci/dwc/pcie-hisi.c
index 560f6a4..f8f7d43 100644
--- a/drivers/pci/dwc/pcie-hisi.c
+++ b/drivers/pci/dwc/pcie-hisi.c
@@ -154,7 +154,7 @@ static int hisi_pcie_cfg_read(struct pcie_port *pp, int where, int size,
walker += (where & 0x3);
reg = where & ~0x3;
- reg_val = dw_pcie_readl_dbi(pci, base, reg);
+ reg_val = dw_pcie_read_dbi(pci, base, reg, 0x4);
if (size == 1)
*val = *(u8 __force *) walker;
@@ -181,15 +181,15 @@ static int hisi_pcie_cfg_write(struct pcie_port *pp, int where, int size,
walker += (where & 0x3);
reg = where & ~0x3;
if (size == 4)
- dw_pcie_writel_dbi(pci, base, reg, val);
+ dw_pcie_write_dbi(pci, base, reg, 0x4, val);
else if (size == 2) {
- reg_val = dw_pcie_readl_dbi(pci, base, reg);
+ reg_val = dw_pcie_read_dbi(pci, base, reg, 0x4);
*(u16 __force *) walker = val;
- dw_pcie_writel_dbi(pci, base, reg, reg_val);
+ dw_pcie_write_dbi(pci, base, reg, 0x4, reg_val);
} else if (size == 1) {
- reg_val = dw_pcie_readl_dbi(pci, base, reg);
+ reg_val = dw_pcie_read_dbi(pci, base, reg, 0x4);
*(u8 __force *) walker = val;
- dw_pcie_writel_dbi(pci, base, reg, reg_val);
+ dw_pcie_write_dbi(pci, base, reg, 0x4, reg_val);
} else
return PCIBIOS_BAD_REGISTER_NUMBER;
@@ -212,7 +212,7 @@ static int hisi_pcie_link_up_hip06(struct hisi_pcie *hisi_pcie)
void __iomem *base = pci->dbi_base;
u32 val;
- val = dw_pcie_readl_dbi(pci, base, PCIE_SYS_STATE4);
+ val = dw_pcie_read_dbi(pci, base, PCIE_SYS_STATE4, 0x4);
return ((val & PCIE_LTSSM_STATE_MASK) == PCIE_LTSSM_LINKUP_STATE);
}
--
1.7.9.5
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| From | Kishon Vijay Abraham I <kishon@ti.com> |
|---|---|
| Date | 2017-01-12 11:40 +0100 |
| Subject | [PATCH 15/37] Documentation: PCI: Guide to use PCI Endpoint Core Layer |
| Message-ID | <sYKXw-2QD-29@gated-at.bofh.it> |
| In reply to | #1557303 |
Add Documentation to help users use endpoint library to enable endpoint mode in the PCI controller and add new PCI endpoint functions. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> --- Documentation/PCI/00-INDEX | 2 + Documentation/PCI/endpoint/pci-endpoint.txt | 190 +++++++++++++++++++++++++++ 2 files changed, 192 insertions(+) create mode 100644 Documentation/PCI/endpoint/pci-endpoint.txt diff --git a/Documentation/PCI/00-INDEX b/Documentation/PCI/00-INDEX index 147231f..ba950b2 100644 --- a/Documentation/PCI/00-INDEX +++ b/Documentation/PCI/00-INDEX @@ -12,3 +12,5 @@ pci.txt - info on the PCI subsystem for device driver authors pcieaer-howto.txt - the PCI Express Advanced Error Reporting Driver Guide HOWTO +endpoint/pci-endpoint.txt + - guide to add endpoint controller driver and endpoint function driver. diff --git a/Documentation/PCI/endpoint/pci-endpoint.txt b/Documentation/PCI/endpoint/pci-endpoint.txt new file mode 100644 index 0000000..68a7839 --- /dev/null +++ b/Documentation/PCI/endpoint/pci-endpoint.txt @@ -0,0 +1,190 @@ + PCI ENDPOINT FRAMEWORK + Kishon Vijay Abraham I <kishon@ti.com> + +This document is a guide to use the PCI Endpoint Framework in order to create +endpoint controller driver, endpoint function driver and using configfs +interface to bind the function driver to the controller driver. + +1. Introduction + +*Linux* has a comprehensive PCI subsystem to support PCI controllers that +operates in Root Complex mode. The subsystem has capability to scan PCI bus, +assign memory resources and irq resources, load PCI driver (based on +vendorid, deviceid), support other services like hot-plug, power management, +advanced error reporting and virtual channels. + +However PCI controller IPs integrated in certain SoC is capable of operating +either in Root Complex mode or Endpoint mode. PCI Endpoint Framework will +add endpoint mode support in *Linux*. This will help to run Linux in an +EP system which can have a wide variety of use cases from testing or +validation, co-processor accelerator etc.. + +2. PCI Endpoint Core + +The PCI Endpoint Core layer comprises of 3 components: the Endpoint Controller +library, the Endpoint Function library and the configfs layer to bind the +endpoint function with the endpoint controller. + +2.1 PCI Endpoint Controller(EPC) Library + +The EPC library provides APIs to be used by the controller that can operate +in endpoint mode. It also provides APIs to be used by function driver/library +in order to implement a particular endpoint function. + +2.1.1 APIs for the PCI controller Driver + +This section lists the APIs that the PCI Endpoint core provides to be used +by the PCI controller driver. + +*) devm_pci_epc_create()/pci_epc_create() + + The PCI controller driver should implement the following ops: + * write_header: ops to populate configuration space header + * set_bar: ops to configure the BAR + * clear_bar: ops to reset the BAR + * alloc_addr_space: ops to allocate *in* PCI controller address space + * free_addr_space: ops to free the allocated address space + * raise_irq: ops to raise a legacy or MSI interrupt + * start: ops to start the PCI link + * stop: ops to stop the PCI link + + The PCI controller driver can then create a new EPC device by invoking + devm_pci_epc_create/pci_epc_create. + +*) devm_pci_epc_destroy()/pci_epc_destroy() + + The PCI controller driver can destroy the EPC device created by either + devm_pci_epc_create or pci_epc_create using devm_pci_epc_destroy() or + /pci_epc_destroy() + +2.1.2 APIs for the PCI Endpoint Function Driver + +This section lists the APIs that the PCI Endpoint core provides to be used +by the PCI endpoint function driver. + +*) pci_epc_write_header() + + The PCI endpoint function driver should use pci_epc_write_header() to + write the standard configuration header to the endpoint controller. + +*) pci_epc_set_bar() + + The PCI endpoint function driver should use pci_epc_set_bar() to configure + the Base Address Register in order for the host to assign PCI addr space. + Register space of the function driver is usually configured + using this API. + +*) pci_epc_clear_bar() + + The PCI endpoint function driver should use pci_epc_clear_bar() to reset + the BAR. + +*) pci_epc_raise_irq() + + The PCI endpoint function driver should use pci_epc_raise_irq() to raise + Legacy Interrupt or MSI Interrupt. + +*) pci_epc_start() + + The PCI endpoint function driver should invoke pci_epc_start() once it + has configured the endpoint function and wants to start the PCI link. + +*) pci_epc_stop() + + The PCI endpoint function driver should invoke pci_epc_stop() to stop + the PCI LINK. + +2.1.3 Other APIs + +There are other APIs provided by the EPC library. These are used for binding +the epf device with epc device. pci-ep-cfs.c can be used as reference for +using these APIs. + +*) pci_epc_get() + + Get a reference to the pci endpoint controller based on the device name of + the controller. + +*) pci_epc_put() + + Release the reference to the pci endpoint controller obtained using + pci_epc_get() + +*) pci_epc_add_epf() + + Add a pci endpoint function to a pci endpoint controller. A pcie device + can have upto 8 functions according to the specification. + +*) pci_epc_remove_epf() + + Remove the pci endpoint function from pci endpoint controller. + +2.2 PCI Endpoint Function(EPF) Library + +The EPF library provides APIs to be used by the function driver and the EPC +library in order to provide endpoint mode functionality. + +2.2.1 APIs for the PCI Endpoint Function Driver + +This section lists the APIs that the PCI Endpoint core provides to be used +by the PCI endpoint function driver. + +*) pci_epf_register_driver() + + The PCI Endpoint Function driver should implement the following ops: + * bind: ops to perform when a EPC device has been bound to EPF device + * unbind: ops to perform when a binding has been lost between a EPC + device and EPF device + * linkup: ops to perform when the EPC device has established a + connection with a host system + + The PCI Function driver can then register the PCI EPF driver by using + pci_epf_register_driver(). + +*) pci_epf_unregister_driver() + + The PCI Function driver can unregister the PCI EPF driver by using + pci_epf_unregister_driver(). + +*) pci_epf_alloc_space() + + The PCI Function driver can allocate space for a particular BAR using + pci_epf_alloc_space(). + +*) pci_epf_free_space() + + The PCI Function driver can free the allocated space + (using pci_epf_alloc_space) by invoking pci_epf_free_space(). + +2.2.2 APIs for the PCI Endpoint Controller Library +This section lists the APIs that the PCI Endpoint core provides to be used +by the PCI endpoint controller library. + +*) pci_epf_linkup() + + The PCI endpoint controller library invokes pci_epf_linkup() when the + EPC device has established the connection to the host. + +2.2.2 Other APIs +There are other APIs provided by the EPF library. These are used to notify +the function driver when the EPF device is bound to the EPC device. +pci-ep-cfs.c can be used as reference for using these APIs. + +*) pci_epf_create() + + Create a new PCI EPF device by passing the name of the PCI EPF device. + This name will be used to bind the the EPF device to a EPF driver. + +*) pci_epf_destroy() + + Destroy the created PCI EPF device. + +*) pci_epf_bind() + + pci_epf_bind() should be invoked when the EPF device has been bound to + a EPC device. + +*) pci_epf_unbind() + + pci_epf_unbind() should be invoked when the binding between EPC device + and EPF device is lost. -- 1.7.9.5
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