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| Started by | Andrew Jeffery <andrew@aj.id.au> |
|---|---|
| First post | 2016-12-20 08:40 +0100 |
| Last post | 2016-12-28 01:30 +0100 |
| Articles | 3 — 2 participants |
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[PATCH v4 0/5] pinctrl: aspeed: Implement remaining pins Andrew Jeffery <andrew@aj.id.au> - 2016-12-20 08:40 +0100
Re: [PATCH v4 3/5] pinctrl: aspeed-g4: Add mux configuration for all pins Linus Walleij <linus.walleij@linaro.org> - 2016-12-27 23:20 +0100
Re: [PATCH v4 4/5] pinctrl: aspeed-g5: Add mux configuration for all pins Linus Walleij <linus.walleij@linaro.org> - 2016-12-28 01:30 +0100
| From | Andrew Jeffery <andrew@aj.id.au> |
|---|---|
| Date | 2016-12-20 08:40 +0100 |
| Subject | [PATCH v4 0/5] pinctrl: aspeed: Implement remaining pins |
| Message-ID | <sQnbH-2wp-15@gated-at.bofh.it> |
Hi Linus,
This is v4 of the series implementing the remainder of the pinmux tables for
the AST2400 and AST2500 SoCs. v3 of the series can be found here:
https://lkml.org/lkml/2016/12/5/847
Cheers,
Andrew
Changes since v3:
* Add a patch fixing the AST2400 SCU compatible strings in the Aspeed pinctrl
bindings. They are mentioned to define the expectations on the pinctrl node's
parent and also in the examples to illustrate the relationship.
* Rework the g5 example bindings in patch 2/5 to reflect the LPC/LHC
bindings[1][2], and fix the SCU compatible string.
[1] https://lkml.org/lkml/2016/12/20/63
[2] https://lkml.org/lkml/2016/12/20/62
Significant changes since v2:
* The fix for touching bit SCU90[6] has been applied, so the patch has been
dropped.
* The MFD devicetree bindings patches have been split out into their own
series: https://lkml.org/lkml/2016/12/5/835
* Rework the "Read and write bits in LPC and GFX controllers" patch so that the
changes are backwards compatible with existing devicetrees. This will lead to
limited functionality, but no more limited than what systems with those
devicetrees already experience.
* A fix for the kerneldoc return value descriptions
Significant changes since v1:
* Fixes from v1 have been applied, so have been dropped for v2
* A new fix has appeared, "pinctrl-aspeed-g5: Never set SCU90[6]", as noted
above
* New bindings documents for the SoC Display and LPC Host Controllers, driven
by the patch "pinctrl: aspeed: Read and write bits in LPCHC and GFX
controllers"
* The v1 patch "pinctrl: aspeed: Enable capture of off-SCU pinmux state" has
been significantly reworked and is now titled "pinctrl: aspeed: Read and
write bits in LPCHC and GFX controllers"
Andrew Jeffery (5):
pinctrl: aspeed: dt: Fix compatibles for the System Control Unit
pinctrl: aspeed: Read and write bits in LPC and GFX controllers
pinctrl: aspeed-g4: Add mux configuration for all pins
pinctrl: aspeed-g5: Add mux configuration for all pins
pinctrl: aspeed: Fix kerneldoc return descriptions
.../devicetree/bindings/pinctrl/pinctrl-aspeed.txt | 127 +-
drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c | 1115 +++++++++++++-
drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c | 1524 +++++++++++++++++++-
drivers/pinctrl/aspeed/pinctrl-aspeed.c | 165 ++-
drivers/pinctrl/aspeed/pinctrl-aspeed.h | 33 +-
5 files changed, 2835 insertions(+), 129 deletions(-)
--
2.9.3
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| From | Linus Walleij <linus.walleij@linaro.org> |
|---|---|
| Date | 2016-12-27 23:20 +0100 |
| Subject | Re: [PATCH v4 3/5] pinctrl: aspeed-g4: Add mux configuration for all pins |
| Message-ID | <sT8g9-7WJ-3@gated-at.bofh.it> |
| In reply to | #1544968 |
On Tue, Dec 20, 2016 at 8:35 AM, Andrew Jeffery <andrew@aj.id.au> wrote: > The patch introducing the g4 pinctrl driver implemented a smattering of > pins to flesh out the implementation of the core and provide bare-bones > support for some OpenPOWER platforms. Now, update the bindings document > to reflect the complete functionality and implement the necessary pin > configuration tables in the driver. > > Cc: Timothy Pearson <tpearson@raptorengineering.com> > Signed-off-by: Andrew Jeffery <andrew@aj.id.au> > Acked-by: Joel Stanley <joel@jms.id.au> > Acked-by: Rob Herring <robh@kernel.org> Patch applied. Yours, Linus Walleij
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| From | Linus Walleij <linus.walleij@linaro.org> |
|---|---|
| Date | 2016-12-28 01:30 +0100 |
| Subject | Re: [PATCH v4 4/5] pinctrl: aspeed-g5: Add mux configuration for all pins |
| Message-ID | <sTahX-KT-9@gated-at.bofh.it> |
| In reply to | #1544968 |
On Tue, Dec 20, 2016 at 8:35 AM, Andrew Jeffery <andrew@aj.id.au> wrote: > The patch introducing the g5 pinctrl driver implemented a smattering of > pins to flesh out the implementation of the core and provide bare-bones > support for some OpenPOWER platforms and the AST2500 evaluation board. > Now, update the bindings document to reflect the complete functionality > and implement the necessary pin configuration tables in the driver. > > Signed-off-by: Andrew Jeffery <andrew@aj.id.au> > Acked-by: Joel Stanley <joel@jms.id.au> > Acked-by: Rob Herring <robh@kernel.org> Patch applied. Yours, Linus Walleij
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