Groups | Search | Server Info | Keyboard shortcuts | Login | Register [http] [https] [nntp] [nntps]
Groups > linux.kernel > #1541209 > unrolled thread
| Started by | Maxime Ripard <maxime.ripard@free-electrons.com> |
|---|---|
| First post | 2016-12-13 17:00 +0100 |
| Last post | 2016-12-14 10:40 +0100 |
| Articles | 2 — 1 participant |
Back to article view | Back to linux.kernel
This discussion starts older than the indexed window; earlier articles aren't shown. The article labeled Started by
below is the oldest one visible, not the original post.
Re: [PATCH 2/6] clk: sunxi-ng: set the parent rate when adjustin CPUX clock on A33 Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-12-13 17:00 +0100
Re: [PATCH 2/6] clk: sunxi-ng: set the parent rate when adjustin CPUX clock on A33 Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-12-14 10:40 +0100
| From | Maxime Ripard <maxime.ripard@free-electrons.com> |
|---|---|
| Date | 2016-12-13 17:00 +0100 |
| Subject | Re: [PATCH 2/6] clk: sunxi-ng: set the parent rate when adjustin CPUX clock on A33 |
| Message-ID | <sNXEK-2Zs-47@gated-at.bofh.it> |
[Multipart message — attachments visible in raw view] — view raw
On Tue, Dec 13, 2016 at 11:22:48PM +0800, Icenowy Zheng wrote: > The CPUX clock on A33, which is for the Cortex-A7 cores, is designed to > be changeable by changing the rate of PLL_CPUX. > > Add CLK_SET_RATE_PARENT flag to this clock. > > Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Thanks! Maxime -- Maxime Ripard, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com
[toc] | [next] | [standalone]
| From | Maxime Ripard <maxime.ripard@free-electrons.com> |
|---|---|
| Date | 2016-12-14 10:40 +0100 |
| Message-ID | <sOecx-4L4-3@gated-at.bofh.it> |
| In reply to | #1541209 |
[Multipart message — attachments visible in raw view] — view raw
On Wed, Dec 14, 2016 at 04:54:14AM +0800, Icenowy Zheng wrote: > > > 13.12.2016, 23:44, "Maxime Ripard" <maxime.ripard@free-electrons.com>: > > On Tue, Dec 13, 2016 at 11:22:48PM +0800, Icenowy Zheng wrote: > >> The CPUX clock on A33, which is for the Cortex-A7 cores, is designed to > >> be changeable by changing the rate of PLL_CPUX. > >> > >> Add CLK_SET_RATE_PARENT flag to this clock. > >> > >> Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> > > > > Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> > > Excuse me, have you merged this patch? Yes, sorry, that's what I meant :) Maxime -- Maxime Ripard, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com
[toc] | [prev] | [standalone]
Back to top | Article view | linux.kernel
csiph-web