Groups | Search | Server Info | Keyboard shortcuts | Login | Register [http] [https] [nntp] [nntps]
Groups > linux.kernel > #1531096 > unrolled thread
| Started by | Zumeng Chen <zumeng.chen@windriver.com> |
|---|---|
| First post | 2016-11-28 09:00 +0100 |
| Last post | 2016-11-28 14:50 +0100 |
| Articles | 3 — 2 participants |
Back to article view | Back to linux.kernel
[PATCH 1/1] net: macb: ensure ordering write to re-enable RX smoothly Zumeng Chen <zumeng.chen@windriver.com> - 2016-11-28 09:00 +0100
Re: [PATCH 1/1] net: macb: ensure ordering write to re-enable RX smoothly Nicolas Ferre <nicolas.ferre@atmel.com> - 2016-11-28 10:30 +0100
Re: [PATCH 1/1] net: macb: ensure ordering write to re-enable RX smoothly Zumeng Chen <zumeng.chen@windriver.com> - 2016-11-28 14:50 +0100
| From | Zumeng Chen <zumeng.chen@windriver.com> |
|---|---|
| Date | 2016-11-28 09:00 +0100 |
| Subject | [PATCH 1/1] net: macb: ensure ordering write to re-enable RX smoothly |
| Message-ID | <sIp10-7EQ-23@gated-at.bofh.it> |
When a hardware issue happened as described by inline comments, the register
write pattern looks like the following:
<write ~MACB_BIT(RE)>
+ wmb();
<write MACB_BIT(RE)>
There might be a memory barrier between these two write operations, so add wmb
to ensure an flip from 0 to 1 for NCR.
Signed-off-by: Zumeng Chen <zumeng.chen@windriver.com>
---
drivers/net/ethernet/cadence/macb.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/net/ethernet/cadence/macb.c b/drivers/net/ethernet/cadence/macb.c
index 533653b..2f9c5b2 100644
--- a/drivers/net/ethernet/cadence/macb.c
+++ b/drivers/net/ethernet/cadence/macb.c
@@ -1156,6 +1156,7 @@ static irqreturn_t macb_interrupt(int irq, void *dev_id)
if (status & MACB_BIT(RXUBR)) {
ctrl = macb_readl(bp, NCR);
macb_writel(bp, NCR, ctrl & ~MACB_BIT(RE));
+ wmb();
macb_writel(bp, NCR, ctrl | MACB_BIT(RE));
if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
--
2.4.11
[toc] | [next] | [standalone]
| From | Nicolas Ferre <nicolas.ferre@atmel.com> |
|---|---|
| Date | 2016-11-28 10:30 +0100 |
| Subject | Re: [PATCH 1/1] net: macb: ensure ordering write to re-enable RX smoothly |
| Message-ID | <sIqq6-f5-13@gated-at.bofh.it> |
| In reply to | #1531096 |
Le 28/11/2016 à 08:57, Zumeng Chen a écrit :
> When a hardware issue happened as described by inline comments, the register
> write pattern looks like the following:
>
> <write ~MACB_BIT(RE)>
> + wmb();
> <write MACB_BIT(RE)>
>
> There might be a memory barrier between these two write operations, so add wmb
> to ensure an flip from 0 to 1 for NCR.
>
> Signed-off-by: Zumeng Chen <zumeng.chen@windriver.com>
> ---
> drivers/net/ethernet/cadence/macb.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/net/ethernet/cadence/macb.c b/drivers/net/ethernet/cadence/macb.c
> index 533653b..2f9c5b2 100644
> --- a/drivers/net/ethernet/cadence/macb.c
> +++ b/drivers/net/ethernet/cadence/macb.c
> @@ -1156,6 +1156,7 @@ static irqreturn_t macb_interrupt(int irq, void *dev_id)
> if (status & MACB_BIT(RXUBR)) {
> ctrl = macb_readl(bp, NCR);
> macb_writel(bp, NCR, ctrl & ~MACB_BIT(RE));
> + wmb();
> macb_writel(bp, NCR, ctrl | MACB_BIT(RE));
>
> if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
It seems that there is exactly the same pattern in function
at91ether_interrupt() can you fix both locations in your patch please?
Thanks, best regards,
--
Nicolas Ferre
[toc] | [prev] | [next] | [standalone]
| From | Zumeng Chen <zumeng.chen@windriver.com> |
|---|---|
| Date | 2016-11-28 14:50 +0100 |
| Subject | Re: [PATCH 1/1] net: macb: ensure ordering write to re-enable RX smoothly |
| Message-ID | <sIutI-2IY-17@gated-at.bofh.it> |
| In reply to | #1531149 |
On 2016年11月28日 17:22, Nicolas Ferre wrote:
> Le 28/11/2016 à 08:57, Zumeng Chen a écrit :
>> When a hardware issue happened as described by inline comments, the register
>> write pattern looks like the following:
>>
>> <write ~MACB_BIT(RE)>
>> + wmb();
>> <write MACB_BIT(RE)>
>>
>> There might be a memory barrier between these two write operations, so add wmb
>> to ensure an flip from 0 to 1 for NCR.
>>
>> Signed-off-by: Zumeng Chen <zumeng.chen@windriver.com>
>> ---
>> drivers/net/ethernet/cadence/macb.c | 1 +
>> 1 file changed, 1 insertion(+)
>>
>> diff --git a/drivers/net/ethernet/cadence/macb.c b/drivers/net/ethernet/cadence/macb.c
>> index 533653b..2f9c5b2 100644
>> --- a/drivers/net/ethernet/cadence/macb.c
>> +++ b/drivers/net/ethernet/cadence/macb.c
>> @@ -1156,6 +1156,7 @@ static irqreturn_t macb_interrupt(int irq, void *dev_id)
>> if (status & MACB_BIT(RXUBR)) {
>> ctrl = macb_readl(bp, NCR);
>> macb_writel(bp, NCR, ctrl & ~MACB_BIT(RE));
>> + wmb();
>> macb_writel(bp, NCR, ctrl | MACB_BIT(RE));
>>
>> if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
> It seems that there is exactly the same pattern in function
> at91ether_interrupt() can you fix both locations in your patch please?
Indeed, I'll send v2 soon, thanks Nicolas.
Although I only have the environment to re-produce the error report
as follows: "not whole frame pointed by descriptor" for macb_interrupt.
Cheers,
Zumeng
>
> Thanks, best regards,
[toc] | [prev] | [standalone]
Back to top | Article view | linux.kernel
csiph-web