[PATCH 1/1] net: macb: ensure ordering write to re-enable RX smoothly

From	Zumeng Chen <zumeng.chen@windriver.com>
Newsgroups	linux.kernel
Subject	[PATCH 1/1] net: macb: ensure ordering write to re-enable RX smoothly
Date	2016-11-28 09:00 +0100
Message-ID	<sIp10-7EQ-23@gated-at.bofh.it> (permalink)
Organization	linux.* mail to news gateway

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When a hardware issue happened as described by inline comments, the register
write pattern looks like the following:

  <write ~MACB_BIT(RE)>
  + wmb();
  <write MACB_BIT(RE)>

There might be a memory barrier between these two write operations, so add wmb
to ensure an flip from 0 to 1 for NCR.

Signed-off-by: Zumeng Chen <zumeng.chen@windriver.com>
---
 drivers/net/ethernet/cadence/macb.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/net/ethernet/cadence/macb.c b/drivers/net/ethernet/cadence/macb.c
index 533653b..2f9c5b2 100644
--- a/drivers/net/ethernet/cadence/macb.c
+++ b/drivers/net/ethernet/cadence/macb.c
@@ -1156,6 +1156,7 @@ static irqreturn_t macb_interrupt(int irq, void *dev_id)
 		if (status & MACB_BIT(RXUBR)) {
 			ctrl = macb_readl(bp, NCR);
 			macb_writel(bp, NCR, ctrl & ~MACB_BIT(RE));
+			wmb();
 			macb_writel(bp, NCR, ctrl | MACB_BIT(RE));
 
 			if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
-- 
2.4.11

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[PATCH 1/1] net: macb: ensure ordering write to re-enable RX smoothly Zumeng Chen <zumeng.chen@windriver.com> - 2016-11-28 09:00 +0100
  Re: [PATCH 1/1] net: macb: ensure ordering write to re-enable RX  smoothly Nicolas Ferre <nicolas.ferre@atmel.com> - 2016-11-28 10:30 +0100
    Re: [PATCH 1/1] net: macb: ensure ordering write to re-enable RX  smoothly Zumeng Chen <zumeng.chen@windriver.com> - 2016-11-28 14:50 +0100

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