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| Started by | Mirza Krak <mirza.krak@gmail.com> |
|---|---|
| First post | 2016-11-07 09:40 +0100 |
| Last post | 2016-11-07 13:40 +0100 |
| Articles | 2 — 2 participants |
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[PATCH V4 1/6] clk: tegra: add TEGRA20_CLK_NOR to init table Mirza Krak <mirza.krak@gmail.com> - 2016-11-07 09:40 +0100
Re: [PATCH V4 1/6] clk: tegra: add TEGRA20_CLK_NOR to init table Thierry Reding <thierry.reding@gmail.com> - 2016-11-07 13:40 +0100
| From | Mirza Krak <mirza.krak@gmail.com> |
|---|---|
| Date | 2016-11-07 09:40 +0100 |
| Subject | [PATCH V4 1/6] clk: tegra: add TEGRA20_CLK_NOR to init table |
| Message-ID | <sANDb-tf-1@gated-at.bofh.it> |
From: Mirza Krak <mirza.krak@gmail.com>
Add TEGRA20_CLK_NOR to init table and set default rate to 92 MHz which
is max rate.
The maximum rate value of 92 MHz is pulled from the downstream L4T
kernel.
Signed-off-by: Mirza Krak <mirza.krak@gmail.com>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-on: Colibri T20/T30 on EvalBoard V3.x and GMI-Memory Board
Acked-by: Jon Hunter <jonathanh@nvidia.com>
---
Changes in v2:
- no changes
Changes in v3:
- Added comment in commit message where I got the maximum rates from.
Changes in V4:
- no changes
drivers/clk/tegra/clk-tegra20.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
index 837e5cb..13d3b5a 100644
--- a/drivers/clk/tegra/clk-tegra20.c
+++ b/drivers/clk/tegra/clk-tegra20.c
@@ -1047,6 +1047,7 @@ static struct tegra_clk_init_table init_table[] __initdata = {
{ TEGRA20_CLK_SDMMC3, TEGRA20_CLK_PLL_P, 48000000, 0 },
{ TEGRA20_CLK_SDMMC4, TEGRA20_CLK_PLL_P, 48000000, 0 },
{ TEGRA20_CLK_SPI, TEGRA20_CLK_PLL_P, 20000000, 0 },
+ { TEGRA20_CLK_NOR, TEGRA20_CLK_PLL_P, 92000000, 0 },
{ TEGRA20_CLK_SBC1, TEGRA20_CLK_PLL_P, 100000000, 0 },
{ TEGRA20_CLK_SBC2, TEGRA20_CLK_PLL_P, 100000000, 0 },
{ TEGRA20_CLK_SBC3, TEGRA20_CLK_PLL_P, 100000000, 0 },
--
2.1.4
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| From | Thierry Reding <thierry.reding@gmail.com> |
|---|---|
| Date | 2016-11-07 13:40 +0100 |
| Message-ID | <sARns-376-11@gated-at.bofh.it> |
| In reply to | #1515901 |
[Multipart message — attachments visible in raw view] — view raw
On Mon, Nov 07, 2016 at 09:30:00AM +0100, Mirza Krak wrote: > From: Mirza Krak <mirza.krak@gmail.com> > > Add TEGRA20_CLK_NOR to init table and set default rate to 92 MHz which > is max rate. > > The maximum rate value of 92 MHz is pulled from the downstream L4T > kernel. > > Signed-off-by: Mirza Krak <mirza.krak@gmail.com> > Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> > Tested-on: Colibri T20/T30 on EvalBoard V3.x and GMI-Memory Board > Acked-by: Jon Hunter <jonathanh@nvidia.com> > --- > > Changes in v2: > - no changes > > Changes in v3: > - Added comment in commit message where I got the maximum rates from. > > Changes in V4: > - no changes Applied, thanks. Thierry
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